Datasheet ISL24011 Datasheet (intersil)

查询ISL24011供应商

®

ISL24011

Octal Voltage Level Shifter for TFT/LCD Panels

Data Sheet October 21, 2005

High Voltage TFT-LCD Logic Driver

The ISL24011 is a high voltage TFT-LCD logic driver with
+40V and -20V output voltage swing capability. It is
manufactured using Intersil’s proprietary monolithic high
voltage bipolar process and is capable of driving a 4700pF
load in 500ns.

The ISL24011 will level shift a digital input signal to an output
voltage nearly equal to its output supply voltages. The
ISL24011 has 3 supplies. V

ON1

and V

are positive

ON2

supplies with a voltage range between +10V and +40V.
V

is the negative supply with a voltage range between

OFF

-5V and -20V. Outputs 1 through 6 are connected to V
and V
V

OFF

. Outputs 7 and 8 are connected to V

OFF

ON2

. This configuration enables outputs 1 through 6 to

and

ON1

provide slicing to the row drivers to reduce flicker, and
outputs 7 and 8 to control possible supply lines. V
should remain constant. It is possible to tie V

ON1

ON2

and V

ON2

supplies together, if independent control as described above
is not desired. V
to V

at all times.

ON1

is required to be greater than or equal

ON2

The ISL24011 is available in a 20 Ld TSSOP package. It is
specified for operation over the -40°C to +85°C industrial
temperature range.

Ordering Information

PART

NUMBER

ISL24011IVZ
(Note)

ISL24011IVZ-T
(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PAR T

MARKING

24011IVZ -40 to +85 20 Ld TSSOP

24011IVZ -40 to +85 20 Ld TSSOP

TEMP.

RANGE (°C) PACKAGE

(Pb-free)

(Pb-free)
Tape & Reel

PKG.

DWG. #

M20.173

M20.173

FN6196.0

Features

• 0V to 5.5V Input Voltage Range

• +40V and -20V Output Voltage Range

• 10mA Output Continuous Current (all 8 channels)

• 25mA Output Peak Current (all 8 channels)

• Rise/Fall Times 260ns/290ns

• Propagation Delay 230ns

• 50kHz Input Logic Frequency

• 20 Ld TSSOP Pb-Free Package

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• TFT-LCD panels

Pinout

ISL24011 (20 LD TSSOP)

TOP VIEW

20

GND

IN1
IN2
IN3
IN4
IN5
IN6
IN7

OFF

1
2
3
4
5
6
7
8
9IN8

10V

V

ON1

OUT1

19
18

OUT2

17

OUT3

16

OUT4

15

OUT5
OUT6

14

OUT7

13

OUT8

12
11

V

ON2

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2005. All Rights Reserved.

Functional Diagram

ISL24011

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

CONNECTED TO V

AND V

OFF

CONNECTED TO V

AND V

OFF

ON1

ON2

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

2

FN6196.0

October 21, 2005

ISL24011

Absolute Maximum Ratings (T

Driver Positive Supply Voltage Range, (VON) . . . . . . . . +5V to +40V

Power Supply Voltage Range, (V
Negative Supply Voltage Range, (V

Supply Turn-On Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/µs

Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . -0.5V to 5.5V

Output Voltage Range, All Outputs . . . . . V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

ON

= 25°C) Thermal Information

A

Thermal Resistance (Typical, Note 1)

to V

OFF

). . . . . . . +10V to +60V

OFF

) . . . . . . . . . . . . . -20V to -5V

-0.5V to VON +0.5V

OFF

20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 140

(continuous, all 8 channels . . . . . . . . . . . . . . . . . . . . . . . 80mA

I

OUT

T

AMBIENT

T

JUNCTION

T

STORAGE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

θ

JA

(°C/W)

NOTE:

is measured with the component mounted on a HIGH effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

= 22V, V

ON

OFF

= TC = T

J

A

= -5V, TA = -40°C to +85°C Unless Otherwise Specified. Typical values tested at 25°C

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

Power Supplies Recommended Operating Voltages -5

(V

OFF

I(V

) Supply Current All Inputs low or high

ON

)

5.0 8.0 mA

22

(VON)

V

No load
V

= V

ON1

= 22V

= -5V

+ V

ON2

-8.0 -5.0 mA

-10 ± 3.5 10 µA

(V

- 1.5V) 21.2 V

ON

-4.3 (V

OFF

+

1.5V)

V

ON

) Supply Current All Inputs low or high

I(V

OFF

I

IN

Input Leakage Each Input low or high

No load

High = 1.8V, Low = 0.8V

VOH High Level Output Voltage IOH = -100µA

V

ON

RL = 4700pF in parallel with 5kΩ

VOL Low Level Output Voltage IOH = +100µA

V

OFF

RL = 4700pF in parallel with 5kΩ

VIH High Level Input Voltage 1.8 V

VIL Low Level Input Voltage 0.8 V

tplh Low to High Prop Delay 50% to 50%, Tested with

190 400 ns
RL = 4700pF in parallel with 5kΩ,
f = 50kHz

tphl High to Low Prop Delay Measured at 50% to 50%

230 400 ns
f = 50kHz
RL = 4700pF in parallel with 5kΩ

ttlh Rise Time Measured at 10% to 90%

260 400 ns
f = 50kHz
RL = 4700pF in parallel with 5kΩ

tthl Fall Time Measured at 10% to 90%

290 500 ns
f = 50kHz
RL = 4700pF in parallel with 5kΩ

3

FN6196.0

October 21, 2005

Pin Descriptions

ISL24011

PIN NUMBER

TSSOP-20 PIN NAME

EQUIVALENT

CIRCUIT DESCRIPTION

1 GND 4 Ground pin

2 IN1 1 Level shifter input 1

3 IN2 1 Level shifter input 2

4 IN3 1 Level shifter input 3

5 IN4 1 Level shifter input 4

6 IN5 1 Level shifter input 5

7 IN6 1 Level shifter input 6

8 IN7 1 Level shifter input 7

9 IN8 1 Level shifter input 8

10 VOFF 4 Negative output supply for all channels

11 VON2 4 Positive output supply for channels 7 and 8. V

12 OUT8 3 Lever shifter output 8

13 OUT7 3 Lever shifter output 7

14 OUT6 2 Lever shifter output 6

15 OUT5 2 Lever shifter output 5

16 OUT4 2 Lever shifter output 4

17 OUT3 2 Lever shifter output 3

18 OUT2 2 Lever shifter output 2

19 OUT1 2 Lever shifter output 1

20 VON1 4 Positive output supply for channels 1 through 6. V

V

ON2

is required to be greater than or equal to V

ON2

is required to be less than or equal to

ON1

ON1

V

V

ON2

OFF

OUTPUTS 1-6 OUTPUTS 7-8

IN

V

OUT

V

OFF

ON1

V

ON2

OUT

V

OFF

CIRCUIT 1. CIRCUIT 2. CIRCUIT 3.

V

ON2

V

V

ON1

OFF

ESD CLAMP

GND

CIRCUIT 4.

4

FN6196.0

October 21, 2005

ISL24011

Typical Performance Curves T

25.0

V

22.5

ON1 & VON2

V

OFF

20.0
INPUT 50% DUTY CYCLE

17.5

15.0

12.5

(mA)

10.0

7.5

5.0

2.5

0.0
10 15 20 25 30 35 40 45 50 55 60 65 70 75

= 22V

= -5V

FREQUENCY (kHz)

= 25°C, Output load parallel RC (RL = 5kΩ, CL = 4700pF) unless otherwise specified.

A

V

OFF

V

ON1

V

ON2

FIGURE 1. SUPPLY CURRENT vs FREQUENCY 1 CHANNEL

TOGGLING

80.0

72.0

V

ON1 & VON2

V

64.0

56.0

48.0

40.0

(mA)

32.0

24.0

16.0

8.0

0.0

OFF

INPUT 50% DUTY CYCLE

10 15 20 25 30 35 40 45 50 55 60 65 70 75

= -5V

= 22V

FREQUENCY (kHz)

V

ON1

V

OFF

V

ON2

FIGURE 3. SUPPLY CURRENT vs FREQUENCY

6 CHANNELS TOGGLING

60.0
V

ON1 & VON2

54.0
V

OFF

48.0
INPUT 50% DUTY CYCLE

42.0

36.0

30.0

(mA)

24.0

18.0

12.0

6.0

0.0
10 15 20 25 30 35 40 45 50 55 60 65 70 75

= -5V

= 22V

FREQUENCY (kHz)

V

ON1

V

OFF

FIGURE 2. SUPPLY CURRENT vs FREQUENCY

4 CHANNELS TOGGLING

100.0
V

ON1 & VON2

90.0
V

OFF

80.0
INPUT 50% DUTY CYCLE

70.5

60.0

50.0

(mA)

40.0

30.0

20.0

10.0

0.0
10 15 20 25 30 35 40 45 50 55 60 65 70 75

= -5V

= 22V

FREQUENCY (kHz)

V

ON1

V

OFF

FIGURE 4. SUPPLY CURRENT vs FREQUENCY

8 CHANNELS TOGGLING

V

V

ON2

ON2

500

V

ON1 & VON2

450

V

OFF

400

50kHz 10% DUTY CYCLE

350
300
250

(ns)

200
150
100

50
0

10 12 15 17 19 22 24 26 28 31 33 35 38 40

= -5V

= 10-40V

V

ON1

& V

ON2

FALL TIME

RISE TIME

PROP DELAY

(V)

FIGURE 5. RISE TIME, FALL TIME AND PROP DELAY vs

V

ON1

& V

VOLTAGE WITH V

ON2

OFF

= -5V

5

500

450

400

FALL TIME

350

300

250

(ns)

200

150

100

50

0

10 12 15 17 19 22 24 26 28 31 33 35 38 40

RISE TIME

V

ON1 & VON2

V

OFF

50kHz 10% DUTY CYCLE

= -20V

= 10-40V

V

ON1

& V

ON2

PROP DELAY

(V)

FIGURE 6. RISE TIME, FALL TIME AND PROP DELAY vs

V

ON1

& V

VOLTAGE WITH V

ON2

= -20V

OFF

October 21, 2005

FN6196.0

ISL24011

Typical Performance Curves T

400

360

320

280

4700pF

240

200

(ns)

160

120

80

40

0

10 12 15 17 19 22 24 26 28 31 33 35 38 40

1800pF

V

ON1

3300pF

V

V

50kHz 10% DUTY CYCLE

& V

ON2

= 25°C, Output load parallel RC (RL = 5kΩ, CL = 4700pF) unless otherwise specified. (Continued)

A

ON1 & VON2

= -5V

OFF

(V)

FIGURE 7. RISE TIME vs CAPACITANCE vs SUPPLY

VOLTAGE WITH V

400

360

320

280

4700pF

240

200

(ns)

160

120

V

ON1 & VON2

80

V

OFF

40

50kHz 10% DUTY CYCLE

0

10 12 15 17 19 22 24 26 28 31 33 35 38 40

= 10-40V

= -5V

V

ON1

OFF

& V

= -5V

3300pF

(V)

ON2

1800pF

FIGURE 9. FALL TIME vs CAPACITANCE vs SUPPLY

VOLTAGE WITH V

OFF

= -5V

= 10-40V

500

450

400

350

4700pF

300

250

(ns)

200

150

V

ON1 & VON2

100

VOFF = -20V

50

50kHz 10% DUTY CYCLE

0

10 12 15 17 19 22 24 26 28 31 33 35 38 40

= 10-40V

V

ON1 & VON2

3300pF

1800pF

(V)

FIGURE 8. RISE TIME vs CAPACITANCE vs SUPPLY

VOLTAGE WITH V

500

450

400

4700pF

350

300

250

(ns)

200

150

V

ON1 & VON2

100

V

OFF

50

50kHz 10% DUTY CYCLE

0

10 12 15 17 19 22 24 26 28 31 33 35 38 40

= 10-40V

= -20V

V

ON1

OFF

& V

= -20V

3300pF

(V)

ON2

1800pF

FIGURE 10. FALL TIME vs CAPACITANCE vs SUPPLY

VOLTAGE WITH V

OFF

= -20V

300

270

240

210

4700pF

180

150

(ns)

120

90

V

ON1 & VON2

60

V

OFF

30

50kHz 10% DUTY CYCLE

0

10 12 15 17 19 22 24 26 28 31 33 35 38 40

= 10-40V

= -5V

V

ON1

& V

3300pF

(V)

ON2

1800pF

FIGURE 11. PROP DELAY vs CAPACITANCE vs SUPPLY

VOLTAGE WITH V

OFF

= -5V

6

300

270

240

4700pF

210

180

150

(ns)

120

90

V

ON1 & VON2

60

V

OFF

30

50kHz 10% DUTY CYCLE

0

10 12 15 17 19 22 24 26 28 31 33 35 38 40

= -20V

= 10-40V

V

ON1

& V

ON2

3300pF

1800pF

(V)

FIGURE 12. PROP DELAY vs CAPACITANCE vs SUPPLY

VOLTAGE WITH V

OFF

= -20V

FN6196.0

October 21, 2005

ISL24011

Typical Performance Curves T

FIGURE 13. TRANSIENT RESPONSE vs LOAD CAPACITANCE

= 25°C, Output load parallel RC (RL = 5kΩ, CL = 4700pF) unless otherwise specified. (Continued)

A

2V/DIV

5V/DIV

0

1800pF

0

PULSE INPUT

4700pF

V

ON1 & VON2

V

= -5V

OFF

50kHz 10% DUTY CYCLE

Application Information

General

The ISL24011 is an octal voltage level shifter. The part was
designed to level shift a digital input signal to +22V and -5V
for TFT-LCD displays and is capable of level shifting input
logic signals (0V to 5.5V) to outputs as large as +40V and

-20V.

Power Supply Decoupling

The ISL24011 requires a 1.0µF decoupling capacitor as
close to the V
possible, for a large load equal to 5kΩ in parallel with
4700pF (Figure 16). This will reduce any dv/dt between the
different supplies and prevent the internal ESD clamp from
turning on and damaging the part.

For lighter loads such as a series 200Ω resistor and a
3300pF capacitance, the decoupling capacitors can be
reduced to 0.47µF.

ON1

, V

ON2

and V

power supply pins, as

OFF

= 22V

400ns/DIV

Latch-up Proof

The ISL24011 is manufactured in a high voltage DI process
that isolates every transistor in its own tub making the part
latch-up proof.

Input Pin Connections

Unused inputs must be tied to ground. Failure to tie unused
input pins to ground will result in rail to rail oscillations on the
respective output pins and higher unwanted power
dissipation in the part. Under these conditions, the
temperature of the part could get very hot.

Limiting the Output Current

No output short circuit current limit exists on this part. All
applications need to limit the output current to less than
80mA. Adequate thermal heat sinking of the parts is also
required.

Application Diagram (TV)

Power Supply Sequence

The ISL24011 requires that V
V

at all times. Therefore, if V

ON1

supplies, then V

needs to be turned on before V

ON2

The reason for this requirement is shown in Circuit 4 in the
Pin Description Table. The ESD protection diode between
V

and V

ON2

drop greater than V
sequence: V

will forward bias if V

ON1

ON2

. Recommended power supply

ON2

, V

, V

ON1

The ESD protection scheme is based on diodes from the
pins to the V

supply and a dv/dt-triggered clamp. This

ON2

dv/dt-triggered clamp imposes a maximum supply turn-on
slew rate of 10V/µs. This clamp will trigger if the supply
powers up too fast, causing amps of current to flow. Ground
and V

are treated as I/O pins with this protection

ON1

scheme. In applications where the dv/dt supply ramp could
exceed 10V/µs, such as hot plugging, additional methods
should be employed to ensure the rate of rise is not
exceeded.

be greater than or equal to

ON2

and V

ON1

, then input logic signals.

OFF

ON2

becomes a diode

ON1

7

are different

.

ON1

DC/DC

CONVERTER

1.0µF

1.0µF

TIMING

CONTROLLER

FIGURE 14. TYPICAL TV APPLICATION CIRCUIT

V

ON1

ISL24011

LEVEL

SHIFTER

V

OFF

V

ON2

1.0µF

LCD PANEL

FN6196.0

October 21, 2005

ISL24011

Application Diagram (Monitor) Test Circuit

DC/DC

CONVERTER

V

OFF

1.0µF

TIMING

CONTROLLER

1.0µF

V

V

ON2

ON1VON1

VON SLICER

CIRCUIT

V

OFF

V

ON2

ISL24011

LEVEL SHIFTER

V

ON1

1.0µF

LCD PANEL

FIGURE 15. TYPICAL MONITOR APPLICATION CIRCUIT WITH

SLICER TO REDUCE FLICKER

1.0µF

V

ON2

1.0µF

OUT1

OUT8

C

C

2

5kΩ

3

1.0µF

IN1

IN8

V

ON1

V

C

OFF

1

ISL24011

If the output load is a series 200Ω resistor and a 3300pF
then C1, C2 and C3 can be reduced to 0.47pF.

INx

t

PHL

t

F

OUTx

t

PLH

t

R

FIGURE 16. TEST LOAD AND TIMING DEFINITIONS

4700pF

8

FN6196.0

October 21, 2005

ISL24011

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

-A-

0.05(0.002)

D

SEA TING PLANE

e

b

0.10(0.004) C AM BS

M

E1

-B-

A

-C-

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

L

c

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

M20.173

20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 ­A1 0.002 0.006 0.05 0.15 ­A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.252 0.260 6.40 6.60 3
E1 0.169 0.177 4.30 4. 50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N20 207

o

α

0

o

8

o

0

o

8

Rev. 1 6/98

NOTESMIN MAX MIN MAX

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

9

FN6196.0

October 21, 2005