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ISL24006

Data Sheet September 9, 2005

14-Channel Programmable Switchable I2C
TFT-LCD Reference Voltage Generator
with Integrated 4-Channel Static Gamma
Drivers

The ISL24006 is a 14-channel programmable switchable
reference voltage generator with four channels of static
gamma drivers integrated, for a complete 18-channel total
gamma solution for TFT-LCD displays. The 14-channel
programmable switchable configuration allows switching
between two gamma curves.

The ISL24006 is divided into two banks of seven generators:
one designed to cover the range from V
the remaining seven channels covering the range from
V

REFU_L

to V

REFU_H

. Each bank has its own separate high
and low reference inputs, with integrated buffers (four static
gamma drivers) to drive the column driver internal DAC
resistor string to within 0.2V from the top and bottom rails.
An output MUX is used to switch between the two curves in
less than 1µs. Switching is controlled using an external
select pin.

ISL24006 includes an I

2

C interface for programming the

offset values.

REFL_L

to V

REFL_H

FN6110.1

Features

• 14-channel programmable switchable

• 4-channel static

• Fast switch time (< 1µs)

• Programmable with 20mV resolution

• Digital supply 3.3V to 5V

• Supply current of 32mA (without load)

• Rail-to-Rail capability

2

C interface

;

•I

• Pb-free plus anneal available (RoHS compliant)

Applications

• TFT-LCD drive circuits

• Reference voltage generators

Pinout

ISL24006

(38-PIN QFN)

TOP VIEW

ISL24006 is available in the 38-pin QFN package and is
specified for operation over the -40°C to +85°C temperature
range.

Ordering Information

PAR T

NUMBER PACKAGE

ISL24006IR-T7 38-Pin QFN 7” MDP0046

ISL24006IR-T13 38-Pin QFN 13” MDP0046

ISL24006IRZ
(See Note)

ISL24006IRZ-T7
(See Note)

ISL24006IRZ-T13
(See Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

38-Pin QFN

(Pb-Free)

38-Pin QFN

(Pb-Free)

38-Pin QFN

(Pb-Free)

TAPE &

RE E L PK G. D WG. #

- MDP0046

7” MDP0046

13” MDP0046

OUT_REFU_H

AVD D

STD_REG

A0

SDA

SCL

OSC

DVDD

BANK_SEL

NC

GND

OUT_REFL_L

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

38

37

36

35

34

33

32

1

2

3

4

5

6

7

8

9

10

11

12

13

OUT14

14

OUT13

THERMAL

PAD

15

16

OUT11

OUT12

17

OUT10

18

OUT9

31

OUT_REFU_L

30

GND

29

BG

28

GND

27

VREFL_L

26

VREFL_H

25

NC

24

NC

23

VREFU_L

22

VREFU_H

21

AVDD

20

OUT_REFL_H

19

OUT8

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2005. All Rights Reserved.

ISL24006

Absolute Maximum Ratings (T

Supply Voltage between A
Supply Voltage between D

Maximum Continuous Output Current . . . . . . . . . . . . 20mA/channel

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The device outputs cannot withstand short­circuit condition for extended periods of time. To avoid damage, do not exceed absolute maximum rating of 20mA/channel.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T

and GND . . . . . . . . . . . . . . . . .+18V

VDD

and GND lesser of VS or +7V (max)

VDD

Electrical Specifications A

= 25°C)

A

= 15V, D

VDD

C

= 10pF to 1/2 A

L

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

= TC = T

J

VDD

VDD

A

= 5V, V

REFU_H

, TA = 25°C, unless otherwise specified.

= 14V, V

REFU_L

= 8.5V, V

REFL_H

= 6.5V, V

= 1V, RL = 1kΩ and

REFL_L

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SUPPLY

I

AVD D

I

DVDD

Supply Current No load 30 38 mA

Digital Supply Current 2.75 4 mA

ANALOG

V

OH

V

OL

V

OH

V

OL

PSRR Power Supply Rejection Ratio A

V

AC

I

B

REG Load Regulation I

OUT1 to OUT7 V

OUT1 to OUT7 V

OUT8 to OUT14 V

OUT8 to OUT14 V

= 14V, A

REFU_H

= 8.5V, A

REFU_L

= 6.5V, A

REFL_H

= 1.0V, A

REFL_L

is moved from 14V to 16V 42 50 dB

VDD

= 15V 13.94 13.98 14.02 V

VDD

= 15V 8.47 8.51 8.55 V

VDD

= 15V 6.44 6.48 6.52 V

VDD

= 15V 0.96 1.00 1.04 V

VDD

Accuracy -50 0 +50 mV

Input Bias Current,
V

REF(U_H, U_L, L_H, L_L)

V

= 1/2 A

REF

OUT

VDD

= 5mA step 0.5 mV/mA

250nA

BG Band Gap 1.1 1.3 1.4 V

SR Slew Rate 815 V/µs

t

S

Settling Time ±1/2 LSB 1 µs

DIGITAL

V

V

F

R

t

S

t

H

IH

IL

CLK

SDIN

Logic 1 Input Voltage D

Logic 0 Input Voltage 20%*

VDD

20%

-

V

V

D

VDD

Clock Frequency 400 kHz

S

Input Resistance SCL, SDA, STD_REG 1 GΩ

DIN

Setup Time 40 ns

Hold Time 40 ns

2

FN6110.1

September 9, 2005

Block Diagram

ISL24006

VREFU_HVREFU_L

OSC

SCL

SDA

STD_REG

A0

AVDD

DVDD

BG

C3

C0

C1

CONTROL

C2

I2C

INTERFACE

ANALOG

POWER

DIGITAL

POWER

REFERENCE

GENERATOR

INT/EXT

OSCILLATOR

MUX

MUX

DELAY

BANKA

HI

BANKA

LO

0
1

B

DAC HI

B

DAC LO

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

OUT REFU_H

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT REFU_L
OUT REFL_H

OUT8

OUT9

OUT10

OUT11

OUT12

OUT13

OUT14

OUT REFL_L

VREFL_H VREFL_L

3

BANK_SEL

FN6110.1

September 9, 2005