intersil ISL22446 DATA SHEET

®

www.BDTIC.com/Intersil

Quad Digitally Controlled Potentiometer (XDCP™)

ISL22446

Data Sheet February 29, 2008

Low Noise, Low Power, SPI® Bus, 128 Taps

The ISL22446 integrates four digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI serial interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the corresponding WR.

The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.

FN6181.1

Features

• Four potentiometers in one package

• 128 resistor taps

• SPI serial interface

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ VCC = 3.3V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T <

• 20 Ld TSSOP and 20 Ld TQFN package

• Pb-free (RoHS compliant)

+55°C

Pinouts

RH3

RL3

RW3

NC
SCK
SDO
GND
RW2

RL2

RH2

ISL22446

(20 LD TSSOP)

TOP VIEW

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

RW0
RL0
RH0
SHDN
VCC
SDI
CS
RH1
RL1
RW1

RL0

RW0

RH3

RL3

RW3

ISL22446

(20 LD TQFN)

TOP VIEW

RH0

O

20 19

1
2
3
4
5

6

NC

SHDN

VCC

SDI

CS

18

16

15

RH1
RL1

14
13

RW1

12

RH2

11

RL2

8179

7

SCK

SDO

10

RW2

GND

Ordering Information

PART NUMBER (Note) PART MARKING RESISTANCE OPTION (kΩ) TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. #

ISL22446UFV20Z* 22446 UFVZ 50 -40 to +125 20 Ld TSSOP M20.173
ISL22446UFRT20Z* 224 46UFZ 50 -40 to +125 20 Ld 4x4 TQFN L20.4x4A
ISL22446WFV20Z* 22446 WFVZ 10 -40 to +125 20 Ld TSSOP M20.173
ISL22446WFRT20Z* 224 46WFZ 10 -40 to +125 20 Ld 4x4 TQFN L20.4x4A
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved

Block Diagram

www.BDTIC.com/Intersil

Pin Descriptions

SCK

SDI

SDO

CS

SHDN

SPI

INTERFACE

ISL22446

POWER UP

INTERFACE,

CONTROL

AND STA TUS

LOGIC

NON-

VOLATILE

REGISTERS

V

CC

GND

WR3

WR2

WR1

WR0

RH3
RW3

RL3
RH2

RW2
RL2

RH1

RW1

RL1
RH0

RW0
RL0

TSSOP PIN

NUMBER

1 3 RH3 “High” terminal of DCP3
2 4 RL3 “Low” terminal of DCP3
3 5 RW3 “Wiper” terminal of DCP3
4 6 NC No connect
5 7 SCK SPI clock input
6 8 SDO SPI Open drain Data Output
7 9 GND Device ground pin
8 10 RW2 “Wiper” terminal of DCP2

9 11 RL2 “Low” terminal of DCP2
10 12 RH2 “High” terminal of DCP2
11 13 RW1 “Wiper” terminal of DCP1
12 14 RL1 “Low” terminal of DCP1
13 15 RH1 “High” terminal of DCP1
14 16 CS
15 17 SDI SPI Data Input
16 18 VCC Power supply pin
17 19 SHDN
18 20 RH0 “High” terminal of DCP0
19 1 RL0 “Low” terminal of DCP0
20 2 RW0 “Wiper” terminal of DCP0

*Note: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf

TQFN PIN

NUMBER SYMBOL DESCRIPTION

SPI Chip Select active low input

Shutdown active low input

EPAD* Exposed Die Pad internally connected to GND

2

FN6181.1

February 29, 2008

ISL22446

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V

IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Latchup (Note 3) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

ESD Ratings

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

1.

θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. For θ

3. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN

Analog Specifications Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

R

V

C

H/CL/CW

(Note 20)

I

VOLTAGE DIVIDER MODE (0V @ R

(Note 9)

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

a max negative pulse of -0.8V for all pins.

TOTAL

RH

R

LkgDCP

INL

RH to RL Resistance W option 10 kΩ

to RL ResistanceTolerance W and U option -20 +20 %

R

H

End-to-End Temperature Coefficient W option ±50 ppm/°C

, VRLVRH and VRL Terminal Voltages VRH and VRL to GND 0 V

Wiper Resistance VCC = 3.3V, wiper current = VCC/R

W

Potentiometer Capacitance

Leakage on DCP Pins

Integral Non-linearity Monotonic over all tap positions, W and U

i; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2 or 3)

L

+ 0.3

CC

CC

U option 50 kΩ

U option ±80 ppm/°C

Voltage at pin from GND to V

options

Thermal Resistance (Typical, Notes 1, 2) θ

20 Lead TSSOP. . . . . . . . . . . . . . . . . . 95 N/A

20 Lead TQFN . . . . . . . . . . . . . . . . . . 40 3.0

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

MIN

(Note 21)

TOTAL

CC

-1 1 LSB

TYP

(Note 4)

70 200 Ω

10/10/25 pF

0.1 1 µA

(°C/W) θJC (°C/W)

JA

pin, and using

MAX

(Note 21) UNIT

(Note 20)

(Note 20)

CC

(Note 5)

V

DNL

(Note 8)

ZSerror

(Note 6)

FSerror

(Note 7)

V

MATCH

(Note 10)

TC

(Note 11)

Differential Non-linearity Monotonic over all tap positions, W and U

options

Zero-scale Error W option 0 1 5 LSB

U option 0 0.5 2

Full-scale Error W option -5 -1 0 LSB

U option -2 -1 0

DCP to DCP Matching Any two DCPs at same tap position, same

voltage at all RH terminals, and same voltage
at all R

terminals

L

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

V

3

-0.5 0.5 LSB
(Note 5)

(Note 5)

(Note 5)

-2 2 LSB
(Note 5)

FN6181.1

February 29, 2008

ISL22446

www.BDTIC.com/Intersil

Analog Specifications Over recommended operating conditions, unless otherwise stated. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected; i = 0, 1, 2 or 3)

RINL

(Note 15)

RDNL

(Note 14)

Roffset

(Note 13)

R

MATCH

(Note 16)

Integral Non-linearity DCP register set between 10h and 7Fh;

Differential Non-linearity DCP register set between 10h and 7Fh;

Offset W option 0 1 7 MI

DCP to DCP Matching Any two DCPs at the same tap position with

monotonic over all tap positions

monotonic over all tap positions, W option
DCP register set between 10h and 7Fh;

monotonic over all tap positions, U option

U option 0 0.5 2 MI

the same terminal voltages

MIN

(Note 21)

-1 1 MI

-1 1 MI

-0.5 0.5 MI

-2 2 MI

Operating Specifications Over the recommended operating conditions, unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

SB

I

SD

I

LkgDig

t

WRT

(Note 20)

t

ShdnRec

(Note 20)

Vpor Power-on Recall Voltage Minimum V

VccRamp V

VCC Supply Current (Volatile
Write/Read)

VCC Supply Current (Non-volatile
Write/Read)

VCC Current (Standby) V

V

Current (Shutdown) V

CC

Leakage Current at Pins SHDN, SCK,
SDI, SDO and CS

Wiper Response Time after SPI Write
to WR Register

DCP Recall Time from Shutdown
Mode

Ramp Rate 0.2 V/ms

CC

f

= 5MHz; (for SPI Active, Read and

SCK

Volatile Write states only)
f

= 5MHz; (for SPI Active, Read and

SCK

Non-volatile Write states only)

= +5.5V @ +85°C, SPI interface in

CC

standby state

= +5.5V @ +125°C, SPI interface in

V

CC

standby state
V

= +3.6V @ +85°C, SPI interface in

CC

standby state

= +3.6V @ +125°C, SPI interface in

V

CC

standby state

= +5.5V @ +85°C, SPI interface in

CC

standby state
V

= +5.5V @ +125°C, SPI interface in

CC

standby state

= +3.6V @ +85°C, SPI interface in

V

CC

standby state

= +3.6V @ +125°C, SPI interface in

V

CC

standby state
Voltage at pin from GND to V

From rising edge of SHDN
stored position and RH connection

SCK rising edge of last bit of ACR data byte
to wiper stored position and RH connection

at which memory recall occurs 2.0 2.6 V

CC

CC

signal to wiper

MIN

(Note 21)

-1 1 µA

TYP

(Note 4)

TYP

(Note 4)

1.5 µs

1.5 µs

1.5 µs

MAX

(Note 21) UNIT

MAX

(Note 21) UNIT

0.5 mA

3mA

5µA

7µA

3µA

5µA

3µA

5µA

2µA

4µA

(Note 12)

(Note 12)

(Note 12)

(Note 12)

(Note 12)

(Note 12)

4

FN6181.1

February 29, 2008

ISL22446

www.BDTIC.com/Intersil

Operating Specifications Over the r ecommended operating conditions, unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

t

EEPROM SPECIFICATION

t

WC

(Note 18)

SERIAL INTERFACE SPECIFICATIONS

V

V

Hysteresis

V

R

(Note 19)

Cpin

(Note 20)

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

t

RI

t

FI

t

DIS

t

t

HO

t

RO

t

FO

t

CS

NOTES:

4. Typical values are for T

5. LSB: [V(R
incremental voltage when changing from one tap to an adjacent tap.

6. ZS error = V(RW)

7. FS error = [V(RW)

8. DNL = [V(RW)

9. INL = [V(RW)

Power-up Delay VCC above Vpor, to DCP Initial Value

D

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T <
Non-volatile Write Cycle Time 12 20 ms

SHDN, SCK, SDI, and CS Input Buffer

IL

LOW Voltage
SHDN, SCK, SDI, and CS Input Buffer

IH

HIGH Voltage
SHDN, SCK, SDI, and CS Input Buffer

Hysteresis
SDO Output Buffer LOW Voltage IOL = 4mA 0 0.4 V

OL

SDO pull-up resistor off-chip Maximum is determined by t

pu

SHDN

, SCK, SDI, SDO and CS Pin

Capacitance
SPI Frequency 5MHz
SPI Clock Cycle Time 200 ns
SPI Clock High Time 100 ns
SPI Clock Low Time 100 ns
Lead Time 250 ns
Lag Time 250 ns
SDI, SCK and CS Input Setup Time 50 ns
SDI, SCK and CS Input Hold Time 50 ns

H

SDI, SCK and CS Input Rise Time 10 ns
SDI, SCK and CS Input Fall Time 10 20 ns
SDO Output Disable Time 0 100 ns
SDO Output Valid Time 350 ns

V

SDO Output Hold Time 0 ns
SDO Output Rise Time Rpu = 2k, Cb = 30pF 60 ns
SDO Output Fall Time Rpu = 2k, Cb = 30pF 60 ns
CS Deselect Time 2µs

= +25°C and 3.3V supply voltage.

A

– V(RW)0]/127. V(RW)

W)127

/LSB.

0

– VCC]/LSB.

127

– V(RW)

i

– i • LSB – V(RW)]/LSB for i = 1 to 127

i

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

127

Register recall completed, and SPI Interface
in standby state

+55°C 50 Years

maximum bus load Cb = 30pF, f

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the

and tFO with

RO

= 5MHz

SCK

MIN

(Note 21)

-0.3 0.3*V

0.7*V

0.05*V

TYP

(Note 4)

CC

CC

10 pF

MAX

(Note 21) UNIT

3ms

CC

V

+ 0.3 V

CC

2kΩ

V

V

5

FN6181.1

February 29, 2008

T

ISL22446

www.BDTIC.com/Intersil

NOTES: (Continued)

10. V

11. for i = 16 to 1 12 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

TC

12. MI =
00 hex respectively.

13. Roffset = RW
Roffset = RW

14. RDNL = (RW

15. RINL = [RW

16. R

17. for i = 16 to 112, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is

18. t

19. R

20. Limits should be considered typical and are not production tested.

21. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.

= [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.

MATCH

MATCH

C

WC

pu

Max V RW()

()Min V RW()

----------------------------------------------------------------------------------------------

V

|RW

R

is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.

is specified for the highest data rate transfer for the device. Higher value pullup can be used at lower data rates.

()Min V R W()

Max V RW()

– RW

127

0
127

i

– (MI • i) – RW0]/MI, for i = 16 to 127.

i

= (RW

Max Ri()Min Ri()–[]

--------------------------------------------------------------- -

Max R i()Min R i()+[]2⁄

i

|/127. MI is a minimum increment. RW

0

/MI, when measuring between RW and RL.

/MI, when measuring between RW and RH.

– RW

)/MI -1, for i = 16 to 127.

i-1

– RW

i,x

()–

i

()+[]2⁄

)/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.

i,y

-------------------- -

×=

+165°C

i

i

6

10

the minimum value of the resistance over the temperature range.

10

------------------------- -

×=

+165°C

6

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature
range.

and RW0 are the measured resistances for the DCP register set to 7F hex and

127

6

FN6181.1

February 29, 2008

Timing Diagrams

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Input Timing

CS

SCK

t

SU

SDI

ISL22446

t

LEAD

t

H

MSB LSB

t

WL

t

CYC

t

...

WH

...

t

FI

t

CS

t

LAG

t

RI

SDO

HIGH IMPEDANCE

Output Timing

CS

SCK

t

V

SDO

SDI

ADDR

MSB LSB

XDCP Timing (for All Load Instructions)

CS

SCK

SDI

MSB LSB

...

t

HO

t

DIS

...

...

t

WRT

...

V

W

HIGH IMPEDANCE

SDO

7

FN6181.1

February 29, 2008

Typical Performance Curves

www.BDTIC.com/Intersil

100

VCC = 3.3V, T = +125°C

90
80
70
60
50
40
30

VCC = 3.3V, T = +20°C

20

WIPER RESISITANCE (Ω)

10

0

020406080100120

TAP POSITI ON (DECIMAL)

FIGURE 1. WIPER RESISTANCE vs T A P POSITION

[ I(RW) = V

CC/RTOTAL

] FOR 10kΩ (W)

= 3.3V, T = -40°C

V

CC

ISL22446

1.4

1.2

1.0

0.8

(µA)

0.6

SB

I

0.4

0.2

0

2.7 3.2 3.7 4.2 4.7 5.2

T = +125°C

T = +25°C

V

CC

FIGURE 2. STANDBY I

(V)

CC

vs V

CC

0.2

VCC = 2.7V

0.1

0

DNL (LSB)

-0.1

VCC = 5.5V

-0.2
0 20406080100120

TAP POSITION (DECIMAL)

T = +25°C

FIGURE 3. DNL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

1.3

1.1

0.9

0.7

(LSB)

0.5

ERROR

0.3

ZS

0.1

-0.1

-0.3

-40-20 0 20 40 6080100120

FIGURE 5. ZS

10k

VCC = 5.5V

VCC = 2.7V

50k

TEMPERATURE (°C)

vs TEMPERATURE FIGURE 6. FS

ERROR

0.2

0.1

0

INL (LSB)

-0.1

-0.2
0 20 40 60 80 100 120

VCC = 2.7V

VCC = 5.5V

TAP POSITION (DECIMAL)

T = +25°C

FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

0.0

-0.3
VCC = 2.7V

-0.6

(LSB)

-0.9

ERROR

ZS

-1.2

-1.5

-40 -20 0 20 40 60 80 100 120

50k

10k

TEMPERATURE (ºC)

vs TEMPERATURE

ERROR

VCC = 5.5V

8

FN6181.1

February 29, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

0.4

0.2

VCC = 5.5V

T = +25°C

ISL22446

0.4

0.2

T = +25°C

VCC = 5.5V

0

-0.2

DNL (LSB)

-0.4
VCC = 2.7V

-0.6

16 36 56 76 96 116

TAP POSITION (DECIMAL)

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

10kΩ (W)

1.0

0.5

CHANGE (%)

0.0

VCC = 5.5V

TOTAL

-0.5

END TO END R

-1.0

-40 -20 0 20 40 60 80 100 120

FIGURE 9. END TO END R

VCC = 2.7V

10k

TEMPERATURE (ºC)

TOTAL

50k

% CHANGE vs

TEMPERATURE

0

-0.2

INL (LSB)

-0.4

-0.6
16 36 56 76 96 116

TAP POSITION (DECIMAL)

VCC = 2.7V

FIGURE 8. INL vs TAP POSITION IN RHEOST AT MODE FOR

10kΩ (W)

105

90

75

60

45

TCv (ppm/°C)

50k

30

15

0

16 36 56 76 96

10k

TAP POSITION (DECIMAL)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

INPUT

300

250

200

150

TCr (ppm/°C)

100

50

0

16 36 56 76 96

50k

TAP POSITION (DECIMAL)

10k

WIPER AT MID POINT (POSITION 40h)
R

= 9.5kΩ

TOTAL

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (2.6MHz)

9

OUTPUT

FN6181.1

February 29, 2008

ISL22446

www.BDTIC.com/Intersil

Typical Performance Curves (Continued)

SCL

SIGNAL AT WIPER
(WIPER UNLOADED)

SIGNAL AT WIPER
(WIPER UNLOADED MOVEMENT
FROM 7Fh TO 00h)

WIPER MID POINT MOVEMENT
FROM 3Fh TO 40h

FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h FIGURE 14. LARGE SIGNAL SETTLING TIME

Pin Description

Potentiometers Pins

RHI AND RLI (i = 0, 1, 2, 3)

The high (RHi) and low (RLi) terminals of the ISL22446 are
equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WRi set to 127 decimal, the wiper will be
closest to RHi, and with the WRi set to 0, the wiper is closest
to RLi.

RWI (i = 0, 1, 2, 3)

RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.

SHDN

The SHDN pin forces the resistor to end-to-end open circuit
condition on RHi and shorts RWi to RLi. When SHDN
returned to logic high, the previous latch settings put RWi at
the same resistance setting prior to shutdown. This pin is
logically OR’d with SHDN bit in ACR register. SPI interface is
still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation.

RHi

RWi

RLi

FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE

is

Bus Interface Pins

SERIAL CLOCK (SCK)

This is the serial clock input of the SPI serial interface.

SERIAL DATA OUTPUT (SDO)

The SDO is an open drain serial data output pin. During a
read cycle, the data bits are shifted out at the falling edge of
the serial clock SCK, while the CS input is low.

SDO requires an external pull-up resistor for proper
operation.

SERIAL DATA INPUT (SDI)

The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI external host device. The data bits are
shifted in at the rising edge of the serial clock SCK, while the
CS

input is low.

CHIP SELECT (CS)

LOW enables the ISL22446, placing it in the active

CS
power mode. A HIGH to LOW transition on CS
prior to the start of any operation after power-up. When CS
HIGH, the ISL22446 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.

is required

is

Principles of Operation

The ISL22446 is an integrated circuit incorporating four
DCPs with its associated registers, non-volatile memory and
the SPI serial interface providing direct communication
between host and potentiometers and memory. The resistor
array is comprised of individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.

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The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.

When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi is recalled and
loaded into the corresponding WRi to set the wiper to the
initial value.

DCP Description

Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper
terminal (RW) is closest to its “Low” terminal (RL). When the
WR register of a DCP contains all ones (WR[6:0]= 7Fh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As
the value of the WR increases from all zeroes (0) to all ones
(127 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.

While the ISL22446 is being powered up, all four WRs are
reset to 40h (64 decimal), which locates RW roughly at the
center between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, all WRs will be reload with the value stored in
corresponding non-volatile Initial Value Registers (IVRs).

The WRs can be read or written to directly using the SPI
serial interface as described in the following sections. The
SPI interface register address bits have to be set to 0000b,
0001b, 0010b or 0011b to access the WR of DCP0, DCP1,
DCP2 or DCP3 respectively. The WRi and IVRi can be read
or written to directly using the SPI serial interface as
described in the following sections.

Memory Description

The ISL22446 contains seven non-volatile and five volatile 8-bit
registers. The memory map of ISL22446 is shown in Table 1.
The four non-volatile registers (IVRi) at address 0, 1, 2 and 3,
contain initial wiper value and volatile registers (WRi) contain
current wiper position. In addition, three non-volatile General
Purpose registers from address 4 to address 6 are available.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

8— ACR
7 Reserved

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

6
5
4

3
2
1
0

General Purpose
General Purpose
General Purpose

IVR3
IVR2
IVR1
IVR0

Not Available
Not Available
Not Available

WR3
WR2
WR1
WR0

The non-volatile IVRi and volatile WRi registers are
accessible with the same address.

The Access Control Register (ACR) contains information
and control bits described in Table 2.

The VOL bit (ACR[7]) determines whether the access is to
wiper registers WR or initial value registers IVR.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

BIT #76543210

Bit Name VOL SHDN WIP

00000

If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.

The SHDN bit (ACR[6]) disables or enables Shutdown mode.
This bit is logically OR’d with SHDN

pin. When this bit is 0,

DCP is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that non-

volatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write to the
IVRi, WRi or ACR while WIP bit is 1.

SPI Serial Interface

The ISL22446 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS
communication with the ISL22446. SCK and CS

must be LOW during

lines are
controlled by the host or master. The ISL22446 operates
only as a slave device.

All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.

Protocol Conventions

The first byte sent to the ISL22446 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.

TABLE 3. IDENTIFICATION BYTE FORMAT

01010000

(MSB) (LSB)

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The next byte sent to the ISL22446 contains the instruction
and register pointer information. The four MSBs are the
instruction and four LSBs are register address (see Table 4).

TABLE 4. IDENTIFICATION BYTE FORMAT

76543210

I3 I2 I1 I0 R3 R2 R1 R0

There are only two valid instruction sets:
1011(binary) - is a Read operation
11 00(binary) - is a Write operation

Write Operation

A Write operation to the ISL22446 is a three-byte operation.
It first requires the CS
valid Identification Byte, then a valid instruction byte followed
by Data Byte is sent to SDI pin. The host terminates the write
operation by pulling the CS
write to addresses 0000b to 0011b, the MSB at address 8
(ACR[7]) determines if the Data Byte is to be written to
volatile or both volatile and non-volatile registers. Refer to
“Memory Description” and Figure 16.

Device can receive more than one byte of data by auto
incrementing the address after each received byte. Note
after reaching the address 0110b, the internal pointer “rolls
over” to address 0000b.

transition from HIGH to LOW, then a

pin from LOW to HIGH. For a

The internal non-volatile write cycle starts after rising edge of
CS

and takes up to 20ms. Thus, non-volatile registers must

be written individually.

Read Operation

A read operation to the ISL22446 is a three-byte operation. It
requires first, the CS
valid Identification Byte, then a valid instruction byte
following by “dummy” Data Byte is sent to SDI pin. The SPI
host reads the data from SDO pin on falling edge of SCK.
The host terminates the read operation by pulling the CS
from LOW to HIGH (see Figure 16).

The ISL22446 will provide the Data Bytes to the SDO pin as
long as SCK is provided by the host from the registers
indicated by an internal pointer. This pointer initial value is
determined by the register address in the Read operation
instruction, and increments by one during transmission of
each Data Byte. After reaching the memory location 0110b,
the pointer “rolls over” to 0000b, and the device continues to
output the data for each received SCK clock.

In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.

transition from HIGH to LOW, then a

pin

CS

SCK

SDI

CS

SCK

SDI

SDO

0 1 0 1 0 0 I3 I2 I1 I0 R3 R2 R1 R0

0101 00 I3 I2 I1 I0 R3 R2 R1 R0

00

00

0

FIGURE 16. THREE BYTE WRITE SEQUENCE

0

FIGURE 17. THREE BYTE READ SEQUENCE

0 D6D5D4 D3D2 D1D0

DON’T CARE

0 D6D5D4 D3D2 D1D0

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Applications Information

Communicating with ISL22446

Communication with ISL22446 proceeds using SPI interface
through the ACR (address 1000b), IVRi (addresses 0000b,
0001b, 0010b and 0011b) and WRi (addresses 0000b,
0001b, 0010b and 0011b) registers.

The wiper of the potentiometer is controlled by the WRi
register. Writes and reads can be made directly to these
registers to control and monitor the wiper position without
any non-volatile memory changes. This is done by setting
MSB bit at address 1000b to 1.

The non-volatile IVRi stores the power up value of the wiper.
IVRs are accessible when MSB bit at address 1000b is set
to 0. Writing a new value to the IVRi register will set a new
power up position for the wiper. Also, writing to this register
will load the same value into the corresponding WRi as the
IVRi. Reading from the IVRi will not change the WRi, if its
contents are different.

Examples

A. Writing to the IVR

This sequence will write a new value (77h) to the IVR2
(non-volatile):

B. Reading from the WR

This sequence will read the value from the WR3 (volatile):
Write to ACR first to access the WRs
Send the ID byte, Instruction Byte, then the Data byte

010100001100100011000000

(Sent to SDI)

Read the data from WR3 (Addr 0011b)
Send the ID byte, Instruction Byte, then Read the Data byte

0101000010110011xxxxxxxx

(Out on SDO)

Set the ACR (Addr 1000b) for NV write (40h)
Send the ID byte, Instruction Byte, then the Data byte

010100001100100001000000

(Sent to SDI)

Set the IVR0 (Addr 0000b) to 77h
Send the ID byte, Instruction Byte, then the Data byte

010100001100001001110111

(Sent to SDI)

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Thin Quad Flat No-Lead Plastic Package
(TQFN)
Thin Micro Lead FramePlastic Package
(TMLFP)

L20.4x4A

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WGGD-1 ISSUE I)

MILLIMETERS

SYMBOL

A 0.70 0.75 0.80 -

A1 - 0.02 0.05 -

A2 - 0.55 0.80 9

A3 0.20 REF 9

b 0.18 0.25 0.30 5, 8

D 4.00 BSC -

D1 3.75 BSC 9

D2 1.95 2.10 2.25 7, 8

E 4.00 BSC -

E1 3.75 BSC 9

E2 1.95 2.10 2.25 7, 8

e 0.50 BSC -

k0.20 - - -

L 0.35 0.60 0.75 8

N202

Nd 5 3

Ne 5 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

NOTESMIN NOMINAL MAX

Rev. 0 11/04

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Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

0.05(0.002)

-A­D

e

b

0.10(0.004) C AM BS

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

E1

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE
PLANE

0.25

0.010

A2

L

c

M20.173

20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.252 0.260 6.40 6.60 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N20 207

o

α

0

o

8

o

0

o

8

Rev. 1 6/98

NOTESMIN MAX MIN MAX

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidi aries.

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