intersil ISL22446 DATA SHEET

www.BDTIC.com/Intersil

Quad Digitally Controlled Potentiometer (XDCP™)

ISL22446

Data Sheet February 29, 2008

Low Noise, Low Power, SPI® Bus, 128 Taps

The ISL22446 integrates four digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI serial interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the DCP’s IVR to the corresponding WR.

The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing.

FN6181.1

Features

• Four potentiometers in one package

• 128 resistor taps

• SPI serial interface

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ VCC = 3.3V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T <

• 20 Ld TSSOP and 20 Ld TQFN package

• Pb-free (RoHS compliant)

+55°C

Pinouts

RH3

RL3

RW3

NC SCK SDO GND RW2

RL2

RH2

ISL22446

(20 LD TSSOP)

TOP VIEW

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

RW0 RL0 RH0 SHDN VCC SDI CS RH1 RL1 RW1

RL0

RW0

RH3

RL3

RW3

ISL22446

(20 LD TQFN)

TOP VIEW

RH0

20 19

1 2 3 4 5

SHDN

VCC

SDI

RH1 RL1

14 13

RW1

RH2

RL2

8179

SCK

SDO

RW2

GND

Ordering Information

PART NUMBER (Note) PART MARKING RESISTANCE OPTION (kΩ) TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. #

ISL22446UFV20Z* 22446 UFVZ 50 -40 to +125 20 Ld TSSOP M20.173 ISL22446UFRT20Z* 224 46UFZ 50 -40 to +125 20 Ld 4x4 TQFN L20.4x4A ISL22446WFV20Z* 22446 WFVZ 10 -40 to +125 20 Ld TSSOP M20.173 ISL22446WFRT20Z* 224 46WFZ 10 -40 to +125 20 Ld 4x4 TQFN L20.4x4A *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

www.BDTIC.com/Intersil

Pin Descriptions

SCK

SDI

SDO

SHDN

SPI

INTERFACE

ISL22446

POWER UP

INTERFACE,

CONTROL

AND STA TUS

LOGIC

NON-

VOLATILE

REGISTERS

GND

WR3

WR2

WR1

WR0

RH3 RW3

RL3 RH2

RW2 RL2

RH1

RW1

RL1 RH0

RW0 RL0

TSSOP PIN

NUMBER

1 3 RH3 “High” terminal of DCP3 2 4 RL3 “Low” terminal of DCP3 3 5 RW3 “Wiper” terminal of DCP3 4 6 NC No connect 5 7 SCK SPI clock input 6 8 SDO SPI Open drain Data Output 7 9 GND Device ground pin 8 10 RW2 “Wiper” terminal of DCP2

9 11 RL2 “Low” terminal of DCP2 10 12 RH2 “High” terminal of DCP2 11 13 RW1 “Wiper” terminal of DCP1 12 14 RL1 “Low” terminal of DCP1 13 15 RH1 “High” terminal of DCP1 14 16 CS 15 17 SDI SPI Data Input 16 18 VCC Power supply pin 17 19 SHDN 18 20 RH0 “High” terminal of DCP0 19 1 RL0 “Low” terminal of DCP0 20 2 RW0 “Wiper” terminal of DCP0

*Note: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf

TQFN PIN

NUMBER SYMBOL DESCRIPTION

SPI Chip Select active low input

Shutdown active low input

EPAD* Exposed Die Pad internally connected to GND

FN6181.1

February 29, 2008

ISL22446

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V

IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Latchup (Note 3) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

ESD Ratings

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. For θ

3. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN

Analog Specifications Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

H/CL/CW

(Note 20)

VOLTAGE DIVIDER MODE (0V @ R

(Note 9)

, the “case temp” location is the center of the exposed metal pad on the package underside.

a max negative pulse of -0.8V for all pins.

TOTAL

LkgDCP

INL

RH to RL Resistance W option 10 kΩ

to RL ResistanceTolerance W and U option -20 +20 %

End-to-End Temperature Coefficient W option ±50 ppm/°C

, VRLVRH and VRL Terminal Voltages VRH and VRL to GND 0 V

Wiper Resistance VCC = 3.3V, wiper current = VCC/R

Potentiometer Capacitance

Leakage on DCP Pins

Integral Non-linearity Monotonic over all tap positions, W and U

i; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2 or 3)

+ 0.3

U option 50 kΩ

U option ±80 ppm/°C

Voltage at pin from GND to V

options

Thermal Resistance (Typical, Notes 1, 2) θ

20 Lead TSSOP. . . . . . . . . . . . . . . . . . 95 N/A

20 Lead TQFN . . . . . . . . . . . . . . . . . . 40 3.0

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

MIN

(Note 21)

TOTAL

-1 1 LSB

TYP

(Note 4)

70 200 Ω

10/10/25 pF

0.1 1 µA

(°C/W) θJC (°C/W)

pin, and using

MAX

(Note 21) UNIT

(Note 20)

(Note 5)

DNL

(Note 8)

ZSerror

(Note 6)

FSerror

(Note 7)

MATCH

(Note 10)

(Note 11)

Differential Non-linearity Monotonic over all tap positions, W and U

options

Zero-scale Error W option 0 1 5 LSB

U option 0 0.5 2

Full-scale Error W option -5 -1 0 LSB

U option -2 -1 0

DCP to DCP Matching Any two DCPs at same tap position, same

voltage at all RH terminals, and same voltage at all R

terminals

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

-0.5 0.5 LSB (Note 5)

(Note 5)

-2 2 LSB (Note 5)

FN6181.1

February 29, 2008

ISL22446

www.BDTIC.com/Intersil

Analog Specifications Over recommended operating conditions, unless otherwise stated. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected; i = 0, 1, 2 or 3)

RINL

(Note 15)

RDNL

(Note 14)

Roffset

(Note 13)

MATCH

(Note 16)

Integral Non-linearity DCP register set between 10h and 7Fh;

Differential Non-linearity DCP register set between 10h and 7Fh;

Offset W option 0 1 7 MI

DCP to DCP Matching Any two DCPs at the same tap position with

monotonic over all tap positions

monotonic over all tap positions, W option DCP register set between 10h and 7Fh;

monotonic over all tap positions, U option

U option 0 0.5 2 MI

the same terminal voltages

MIN

(Note 21)

-1 1 MI

-0.5 0.5 MI

-2 2 MI

Operating Specifications Over the recommended operating conditions, unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

CC1

CC2

LkgDig

WRT

(Note 20)

ShdnRec

(Note 20)

Vpor Power-on Recall Voltage Minimum V

VccRamp V

VCC Supply Current (Volatile Write/Read)

VCC Supply Current (Non-volatile Write/Read)

VCC Current (Standby) V

Current (Shutdown) V

Leakage Current at Pins SHDN, SCK, SDI, SDO and CS

Wiper Response Time after SPI Write to WR Register

DCP Recall Time from Shutdown Mode

Ramp Rate 0.2 V/ms

= 5MHz; (for SPI Active, Read and

SCK

Volatile Write states only) f

= 5MHz; (for SPI Active, Read and

SCK

Non-volatile Write states only)

= +5.5V @ +85°C, SPI interface in

standby state

= +5.5V @ +125°C, SPI interface in

standby state V

= +3.6V @ +85°C, SPI interface in

standby state

= +3.6V @ +125°C, SPI interface in

standby state

= +5.5V @ +85°C, SPI interface in

standby state V

= +5.5V @ +125°C, SPI interface in

standby state

= +3.6V @ +85°C, SPI interface in

standby state

= +3.6V @ +125°C, SPI interface in

standby state Voltage at pin from GND to V

From rising edge of SHDN stored position and RH connection

SCK rising edge of last bit of ACR data byte to wiper stored position and RH connection

at which memory recall occurs 2.0 2.6 V

signal to wiper

MIN

(Note 21)

-1 1 µA

TYP

(Note 4)

TYP

(Note 4)

1.5 µs

MAX

(Note 21) UNIT

MAX

(Note 21) UNIT

0.5 mA

3mA

5µA

7µA

3µA

5µA

3µA

5µA

2µA

4µA

(Note 12)

FN6181.1

February 29, 2008

ISL22446

www.BDTIC.com/Intersil

Operating Specifications Over the r ecommended operating conditions, unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

EEPROM SPECIFICATION

(Note 18)

SERIAL INTERFACE SPECIFICATIONS

Hysteresis

(Note 19)

Cpin

(Note 20)

SCK

CYC

LEAD

LAG

DIS

NOTES:

4. Typical values are for T

5. LSB: [V(R incremental voltage when changing from one tap to an adjacent tap.

6. ZS error = V(RW)

7. FS error = [V(RW)

8. DNL = [V(RW)

9. INL = [V(RW)

Power-up Delay VCC above Vpor, to DCP Initial Value

EEPROM Endurance 1,000,000 Cycles EEPROM Retention Temperature T < Non-volatile Write Cycle Time 12 20 ms

SHDN, SCK, SDI, and CS Input Buffer

LOW Voltage SHDN, SCK, SDI, and CS Input Buffer

HIGH Voltage SHDN, SCK, SDI, and CS Input Buffer

Hysteresis SDO Output Buffer LOW Voltage IOL = 4mA 0 0.4 V

SDO pull-up resistor off-chip Maximum is determined by t

SHDN

, SCK, SDI, SDO and CS Pin

Capacitance SPI Frequency 5MHz SPI Clock Cycle Time 200 ns SPI Clock High Time 100 ns SPI Clock Low Time 100 ns Lead Time 250 ns Lag Time 250 ns SDI, SCK and CS Input Setup Time 50 ns SDI, SCK and CS Input Hold Time 50 ns

SDI, SCK and CS Input Rise Time 10 ns SDI, SCK and CS Input Fall Time 10 20 ns SDO Output Disable Time 0 100 ns SDO Output Valid Time 350 ns

SDO Output Hold Time 0 ns SDO Output Rise Time Rpu = 2k, Cb = 30pF 60 ns SDO Output Fall Time Rpu = 2k, Cb = 30pF 60 ns CS Deselect Time 2µs

= +25°C and 3.3V supply voltage.

– V(RW)0]/127. V(RW)

W)127

/LSB.

– VCC]/LSB.

127

– V(RW)

– i • LSB – V(RW)]/LSB for i = 1 to 127

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

127

+55°C 50 Years

maximum bus load Cb = 30pF, f

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the

and tFO with

= 5MHz

SCK

MIN

(Note 21)

-0.3 0.3*V

0.7*V

0.05*V

TYP

(Note 4)

10 pF

MAX

(Note 21) UNIT

3ms

+ 0.3 V

2kΩ

FN6181.1

February 29, 2008

+ 10 hidden pages