intersil ISL22429 DATA SHEET

®

www.BDTIC.com/Intersil

Dual Digitally Controlled Potentiometer (XDCP™)

ISL22429

Data Sheet September 26, 2006

Low Noise, Low Power, SPI® Bus, 128 T aps,
Wiper Only

The ISL22429 integrates two digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI serial interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the corresponding WR.

The DCP can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.

Pinout

ISL22429

(10 LD MSOP)

TOP VIEW

FN6332.1

Features

• Two potentiometers in one package

• 128 resistor taps

• SPI serial interface

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ 3.3V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T <

• 10 Lead MSOP

• Pb-free plus anneal product (RoHS compliant)

+55°C

RW0NC

10

SHDN

9

V

8

CC

SDI

7

CS

SCK

SDO

GND

RW1

1

2

3

4

56

Ordering Information

RESISTANCE OPTION

PART NUMBER PART MARKING

ISL22429UFU10Z
(Notes 1, 2)

ISL22429WFU10Z
(Notes 1, 2)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

429UZ 50 -40 to +125 10 Ld MSOP

429WZ 10 -40 to +125 10 Ld MSOP

(kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M10.118

(Pb-free)

M10.118

(Pb-free)

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006. All Rights Reserved

Block Diagram

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SCK

SDI

SDO

CS

SPI

INTERFACE

ISL22429

POWER-UP

INTERFACE,

CONTROL

AND STA TUS

LOGIC

V

CC

V

CC

WR1

V

CC

RW1

NON-

VOLATILE

SHDN

REGISTERS

GND

Pin Descriptions

MSOP PIN SYMBOL DESCRIPTION

1NC
2 SCK SPI interface clock input
3 SDO Open drain SPI interface data output
4 GND Device ground pin
5 RW1 “Wiper” terminal of DCP1
6CS
7 SDI SPI interface data input
8V
9SHDN

10 RW0 “Wiper” terminal of DCP0

CC

Chip Select active low input

Power supply pin
Shutdown active low input

WR0

RW0

2

FN6332.1

September 26, 2006

ISL22429

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Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP pin with Respect to GND. . . . . . . -0.3V to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

Latchup (Note 4) . . . . . . . . . . . . . . . . . .Class II, Level B @ +125°C

ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV

(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3.

JA

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -0.8V for all pins.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

(Note 15)

C

(Note 15)

VOLTAGE DIVIDER MODE (measured at R

INL

(Note 10)

DNL

(Note 9)
ZSerror

(Note 7)

FSerror
(Note 8)

V

MATCH

(Note 11)

TC

(Note 12)

End-to-End Resistance W option 10 kΩ

End-to-End Resistance Tolerance W and U option -20 +20 %
End-to-End Temperature Coefficient W option ±50 ppm/°C

Wiper Resistance V

W

Wiper Capacitance

W

Integral Non-linearity Monotonic over all tap positions -1 1 LSB

Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

Zero-scale Error W option 0 1 5 LSB

Full-scale Error W option -5 -1 0 LSB

DCP to DCP Matching Any two DCPs at the same tap position -2 2 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

V

i, unloaded; i = 0 or 1)

W

+ 0.3

CC

CC

U option 50 kΩ

U option ±80 ppm/°C

= 3.3V @ +25°C,

CC

wiper current = V

U option 0 0.5 2

U option -2 -1 0

Thermal Resistance (Typical, Note 3)

10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Recommended Operating Conditions

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

TYP

(NOTE 5) MAX UNIT

70 Ω

CC/RTOTAL

25 pF

θ

(°C/W)

JA

(Note 15)

(Note 15)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

3

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ISL22429

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Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

I

SB

I

SD

I

LkgDig

t

WRT

(Note 15)

t

ShdnRec

(Note 15)

Vpor Power-on Recall Voltage Minimum V

VccRamp V

t

EEPROM SPECIFICATION

t

WC

(Note 13)

SERIAL INTERFACE SPECIFICATIONS

V

V

VCC Supply Current (volatile
write/read)

V

Supply Current (volatile

CC

write/read)
VCC Supply Current (non-volatile

write/read)

Supply Current (non-volatile

V

CC

write/read)
VCC Current (standby) V

VCC Current (shutdown) V

Leakage Current, at Pins SHDN, SCK,
SDI, SDO and CS

Wiper Response Time after SPI Write
to WR Register

DCP Recall Time from Shutdown
Mode

Ramp Rate 0.2 V/ms

CC

Power-up delay VCC above Vpor, to DCP Initial Value

D

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T <
Non-volatile Write Cycle Time 12 20 ms

SHDN, SCK, SDI, and CS Input Buffer

IL

LOW Voltage
SHDN, SCK, SDI, and CS Input Buffer

IH

HIGH Voltage

10k DCP, f
and write states)

50k DCP, f
and write states)

10k DCP, f
and write states)

50k DCP, f
and write states)

= +5.5V, 10k DCP, SPI interface in

CC

standby state

= +5.5V, 50k DCP, SPI interface in

V

CC

standby state

= +3.6V, 10k DCP, SPI interface in

V

CC

standby state
V

= +3.6V, 50k DCP, SPI interface in

CC

standby state

= +5.5V @ +85°C, SPI interface in

CC

standby state
V

= +5.5V@ +125°C, SPI interface in

CC

standby state

= +3.6V @ +85°C, SPI interface in

V

CC

standby state

= +3.6V @ +125°C, SPI interface in

V

CC

standby state
Voltage at pin from GND to V

From rising edge of SHDN
stored position and RH connection

SCK rising edge of last bit of ACR data byte
to wiper stored position and RH connection

Register recall completed, and SPI Interface
in standby state

= 5MHz; (for SPI active, read

SPI

= 5MHz; (for SPI active, read

SPI

= 5MHz; (for SPI active, read

SPI

= 5MHz; (for SPI active, read

SPI

CC

signal to wiper

at which memory recall occurs 2.0 2.6 V

CC

+55°C 50 Years

-1 1 µA

-0.3 0.3*V

0.7*V

TYP

(NOTE 5) MAX UNIT

1.4 mA

450 µA

3.5 mA

2.0 mA

1.22 mA

320 µA

800 µA

250 µA

3µA

5µA

2µA

4µA

1.5 µs

1.5 µs

1.5 µs

3ms

CC

VCC+0.3 V

CC

V

4

FN6332.1

September 26, 2006

ISL22429

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

Hysteresis SHDN, SCK, SDI, and CS Input Buffer

Hysteresis

V

R

SDO Output Buffer LOW Voltage IOL = 4mA 0 0.4 V

OL

SDO Pull-up Resistor Off-chip Maximum is determined by t

pu

(Note 14)

Cpin

(Note 15)

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t
t
t

t

DIS

t

t

HO

t

RO

t

FO

t

CS

SHDN

, SCK, SDI, SDO and CS Pin

Capacitance
SPI Frequency 5MHz
SPI Clock Cycle Time 200 ns
SPI Clock High Time 100 ns
SPI Clock Low Time 100 ns
Lead Time 250 ns
Lag Time 250 ns
SDI, SCK and CS Input Setup Time 50 ns
SDI, SCK and CS Input Hold Time 50 ns

H

SDI, SCK and CS Input Rise Time 10 ns

RI

SDI, SCK and CS Input Fall Time 10 20 ns

FI

SDO Output Disable Time 0 100 ns
SDO Output Valid Time 350 ns

V

SDO Output Hold Time 0 ns
SDO Output Rise Time Rpu = 2k, Cbus = 30pF 60 ns
SDO Output Fall Time Rpu = 2k, Cbus = 30pF 60 ns
CS Deselect Time 2µs

and tFO with

RO

maximum bus load Cbus = 30pF, f
5MHz

SCK

=

0.05*
V

CC

NOTES:

5. Typical values are for T

6. LSB: [V(R
incremental voltage when changing from one tap to an adjacent tap.

– V(RW)0]/127. V(RW)

W)127

7. ZS error = V(RW)

8. FS error = [V(RW)

9. DNL = [V(RW)

10. INL = [V(RW)

11. V

MATCH

12. for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

TC

V

is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.

13. t

WC

– V(RW)

i

– i • LSB – V(RW)]/LSB for i = 1 to 127

i

= [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.

Max V RW()

()Min V RW()

----------------------------------------------------------------------------------------------

Max V RW()

()Min V RW()

= +25°C and 3.3V supply voltage.

A

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the

127

/LSB.

0

– VCC]/LSB.

127

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

()–

i

i

()+[]2⁄

i

i

---------------- -

×=

165°C

6

10

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

14. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.

15. This parameter is not 100% tested.

TYP

(NOTE 5) MAX UNIT

V

2kΩ

10 pF

5

FN6332.1

September 26, 2006

Timing Diagrams

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Input Timing

CS

t

LEAD

ISL22429

t

CYC

t

CS

t

LAG

SCK

SDI

SDO

Output Timing

CS

SCK

SDO

SDI

t

SU

MSB LSB

HIGH IMPEDANCE

ADDR

t

H

t

WL

t

WH

...

t

FI

t

RI

...

...

t

V

MSB LSB

t

HO

...

t

DIS

XDCP Timing (for All Load Instructions)

CS

SCK

SDI

V

SDO

W

HIGH IMPEDANCE

MSB LSB

6

...

...

t

WRT

FN6332.1

September 26, 2006

Typical Performance Curves

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VCC

100

Vcc = 3.3V, T = 125ºC

90
80
70
60
50
40
30

Vcc = 3.3V, T = 20ºC

WIPER RESISITANCE (Ω)

20
10

0

0 20406080100120

TAP PO SITI ON ( D E C I MAL )

Vcc = 3.3V, T = -40ºC

ISL22429

1.4

1.2

1

VCC

0.8

0.6

Isb (µA)

0.4

0.2

0

2.73.23.74.24.75.2

T = 1 25

T = 25

ºC

ºC

Vcc, V

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[ I(RW) = V

CC/RTOTAL

] FOR 10kΩ (W)

0.2
Vcc = 2.7V

T = 25ºC

0.1

0

DNL (LSB)

-0. 1

Vcc = 5.5V

-0. 2
0 20 40 60 80 100 120

TAP PO S ITI O N ( DE C I MAL )

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

1.30

MODE FOR 10kΩ (W)

10k

1.10

0.90

0.70

0.50

0.30

ZSerror (LSB)

Vcc = 5.5V

Vcc = 2.7V

0.10

-0.10

50k

-0.30

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (ºC)

FIGURE 2. STANDBY I

CC

vs V

CC

0.2
T = 25º C

0.1

Vcc = 2.7V

0

INL (LSB)

-0.1
Vcc = 5.5V

-0.2

0 20406080100120

TAP PO SI TIO N (D ECI MAL )

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

0.00

-0. 30
Vcc = 2.7V Vcc = 5.5V

50k

-0. 60

-0. 90

FSerror (LSB)

10k

-1. 20

-1. 50

-40-200 20406080100120

TEMPERATURE (ºC)

FIGURE 5. ZSerror vs TEMPERATURE

FIGURE 6. FSerror vs TEMPERATURE

7

FN6332.1

September 26, 2006

Typical Performance Curves (Continued)

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ISL22429

1.00
Vcc = 2.7V

0.50

CHANGE (%)

0.00

TOTAL

-0.50

END TO END R

-1.00

-40 -20 0 20 40 60 80 100 120

FIGURE 7. END TO END R

Vcc = 5.5V

TEMPERATURE (º C)

TOTAL

TEMPERATURE

50k

10k

% CHANGE vs

105

90

10k

75
60
45

TCv (ppm/°C)

30

50k

15

0

16 36 56 76 96

TAP PO SI T IO N ( D ECIMAL)

FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm

FIGURE 9. MIDSCALE GLITCH, CODE 80h TO 7Fh

Pin Description

Potentiometer Pins

RWi (i = 0, 1)

RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.

SHDN

The SHDN pin forces the resistors to end-to-end open circuit
condition and shorts RWi to GND. When SHDN
to logic high, the previous latch settings put RWi at the same
resistance setting prior to shutdown. This pin is logically
OR’d with SHDN bit in ACR register. SPI interface is still
available in shutdown mode and all registers are accessible.
This pin must remain HIGH for normal operation.

8

is returned

FIGURE 10. LARGE SIGNAL SETTLING TIME

RW

FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE

Bus Interface Pins

Serial Clock (SCK)

This is the serial clock input of the SPI serial interface.

Serial Data Output (SDO)

The SDO is an open drain serial data output pin. During a
read cycle, the data bits are shifted out at the falling edge of
the serial clock SCK, while the CS

input is low.

FN6332.1

September 26, 2006

ISL22429

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SDO requires an external pull-up resistor for proper
operation.

Serial Data Input (SDI)

The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI external host device. The data bits are
shifted in at the rising edge of the serial clock SCK, while the
CS

input is low.

Chip Select (CS)

LOW enables the ISL22429, placing it in the active

CS
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS

is
HIGH, the ISL22429 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.

Principles of Operation

The ISL22429 is an integrated circuit incorporating two DCPs
with its associated registers, non-volatile memory and the SPI
serial interface providing direct communication between host
and potentiometers and memory. The resistor array is
comprised of individual resistors connected in se ries. At either
end of the array and between each resistor is an electronic
switch that transfers the potential at that point to the wiper.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.

memory reading, all WRs will be reload with the value stored
in corresponding non-volatile Initial Value Registers (IVRs).

The SPI interface register address bits have to be set to
0000b or 0001b to access the WR of DCP0 or DCP1
respectively. The WRi and IVRi can be read or written to
directly using the SPI serial interface as described in the
following sections.

Memory Description

The ISL22429 contains seven non-volatile and three volatile
8-bit registers. The memory map of ISL22429 is on Table 1.
The two non-volatile registers (IVRi) at address 0 and 1,
contain initial wiper value and volatile registers (WRi) contain
current wiper position. In addition, five non-volatile General
Purpose registers from address 2 to address 6 are available.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

8— ACR
7 Reserved
6

5
4
3
2

1
0

General Purpose
General Purpose
General Purpose
General Purpose
General Purpose

IVR1
IVR0

Not Available
Not Available
Not Available
Not Available
Not Available

WR1
WR0

When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi is recalled and
loaded into the corresponding WRi to set the wiper to the
initial value.

DCP Description

Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer and internally connected to Vcc and GND.
The RW pin of each DCP is connected to intermediate
nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by volatile Wiper Register (WR).
Each DCP has its own WR. When the WR of a DCP contains
all zeroes (WR[6:0] = 00h), its wiper terminal (RW) is closest
to GND. When the WR register of a DCP contains all ones
(WR[6:0] = 7Fh), its wiper terminal (RW) is closest to V
As the value of the WR increases from all zeroes (0) to all
ones (127 decimal), the wiper moves monotonically from the
position closest to GND to the closest to V

CC

.

While the ISL22429 is being powered up, all two WRs are
reset to 40h (64 decimal), which locates RW roughly at the
center between GND and Vcc. After the power supply
voltage becomes large enough for reliable non-volatile

CC

.

The non-volatile IVRi and volatile WRi registers are
accessible with the same address.

The Access Control Register (ACR) contains information
and control bits described below in Table 2.

The VOL bit (ACR[7]) determines whether the access is to
wiper registers WRi or initial value registers IVRi.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

BIT #76543210

Bit Name VOL SHDN WIP

00000

If VOL bit is 0, the non-volatile IVRi register is accessible. If
VOL bit is 1, only the volatile WRi is accessible. Note, value
is written to IVRi register also is written to the WRi. The
default value of this bit is 0.

The SHDN bit (ACR[6]) disables or enables Shutdown
mode. This bit is logically OR’d with SHDN

pin. When this bit
is 0, DCPs are in Shutdown mode. The default value of
SHDN bit is 1.

The WIP bit (ACR[5]) is read only bit. It indicates that
non-volatile write operation is in progress. The WIP bit can
be read repeatedly after a non-volatile write to determine if
the write has been completed. It is impossible to write to the
IVRi, WRi or ACR while WIP bit is 1.

9

FN6332.1

September 26, 2006

ISL22429

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SPI Serial Interface

The ISL22429 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS
communication with the ISL22429. SCK and CS
controlled by the host or master. The ISL22429 operates
only as a slave device.

All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.

must be LOW during

lines are

Protocol Conventions

The first byte sent to the ISL22429 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.

TABLE 3. IDENTIFICATION BYTE FORMAT

01010000

(MSB) (LSB)

The next byte sent to the ISL22429 contains the instruction
and register pointer information. The four MSBs are the
instruction and four LSBs are register address (see Table 4).

TABLE 4. IDENTIFICATION BYTE FORMAT

76543210

I3 I2 I1 I0 R3 R2 R1 R0

There are only two valid instruction sets:
1011(binary) - is a Read operation
11 00(binary) - is a Write operation

Write Operation

A Write operation to the ISL22429 is a three-byte operation.
It requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte

following by Data Byte is sent to SDI pin. The host
terminates the write operation by pulling the CS
LOW to HIGH. For a write to addresses 0000b or 0001b, the
MSB at address 8 (ACR[7]) determines if the Data Byte is to
be written to volatile or both volatile and non-volatile
registers. Refer to “Memory Description” and Figure 12.

Device can receive more than one byte of data by auto
incrementing the address after each received byte. Note
after reaching the address 0110b, the internal pointer “rolls
over” to address 0000b.

The internal non-volatile write cycle starts after rising edge of

and takes up to 20ms. Thus, non-volatile registers must

CS
be written individually.

pin from

Read Operation

A read operation to the ISL22429 is a three-byte operation. It
requires first, the CS
valid Identification Byte, then a valid instruction byte
following by “dummy” Data Byte is sent to SDI pin. The SPI
host reads the data from SDO pin on falling edge of SCK.
The host terminates the read operation by pulling the CS
from LOW to HIGH (see Figure 13).

The ISL22429 will provide the Data Bytes to the SDO pin as
long as SCK is provided by the host from the registers
indicated by an internal pointer. This pointer initial value is
determined by the register address in the Read operation
instruction, and increments by one during transmission of
each Data Byte. After reaching the memory location 0110b,
the pointer “rolls over” to 0000b, and the device continues to
output the data for each received SCK clock.

In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.

transition from HIGH to LOW, then a

pin

CS

SCK

SDI

0 1 0 1 0 0 I3 I2 I1 I0 R3 R2 R1 R0

00

10

0

FIGURE 12. THREE BYTE WRITE SEQUENCE

0 D6D5D4 D3D2 D1D0

September 26, 2006

FN6332.1

CS

y

xxxxxxx

x

A

T

www.BDTIC.com/Intersil

SCK

ISL22429

SDI

0 101 00 I3 I2 I1 I0 R3 R2 R1 R0

SDO

Applications Information

00

0

FIGURE 13. THREE BYTE READ SEQUENCE

any non-volatile memory changes. This is done by setting
MSB bit at address 1000b to 1.

Communicating with ISL22429

Communication with ISL22429 proceeds using SPI interface
through the ACR (address 1000b), IVRi (addresses 0000b,
0001b) and WRi (addresses 0000b, 0001b) registers.

The wiper of the potentiometer is controlled by the WRi
register. Writes and reads can be made directly to these
registers to control and monitor the wiper position without

The non-volatile IVRi stores the power up value of the wiper.
IVRs are accessible when MSB bit at address 1000b is set
to 0. Writing a new value to the IVRi register will set a new
power up position for the wiper. Also, writing to this register
will load the same value into the corresponding WRi as the
IVRi. Reading from the IVRi will not change the WRi, if its
contents are different.

Examples:

B. Reading from the WR:

This sequence will read the value from the WR1 (volatile):

Write to ACR first to access the volatile WRs
Send the ID byte, Instruction Byte, then the Data byte

0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0

(Sent to SDI)
Read the data from WR1 (Addr 0001b)
Send the ID b

0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 1

te, Instruction Byte, then Read the Data byte

(Out on SDO)

Don’t Care

0 D6D5D4 D3 D2 D1D0

. Writing to the IVR:

his sequence will write a new value (77h) to the IVR0(non-volatile):

Set the ACR (Addr 1000b) for NV write (40h)
Send the ID byte, Instruction Byte, then the Data byte

0 1 0 1 0 0 0 0 1 1 0 0 1 00001000000

(Sent to SDI)
Set the IVR0 (Addr 0000b) to 77h
Send the ID byte, Instruction Byte, then the Data byte

0 1 0 1 0 0 0 0 1 1 0 0 0 00001110111

(Sent to SDI)

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ISL22429

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.007 0.011 0.18 0.27 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

o

θ

α

5

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 0 12/02

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

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12

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