intersil ISL22429 DATA SHEET

®

www.BDTIC.com/Intersil

Dual Digitally Controlled Potentiometer (XDCP™)

ISL22429

Data Sheet September 26, 2006

Low Noise, Low Power, SPI® Bus, 128 T aps,
Wiper Only

The ISL22429 integrates two digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI serial interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the corresponding WR.

The DCP can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.

Pinout

ISL22429

(10 LD MSOP)

TOP VIEW

FN6332.1

Features

• Two potentiometers in one package

• 128 resistor taps

• SPI serial interface

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ 3.3V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T <

• 10 Lead MSOP

• Pb-free plus anneal product (RoHS compliant)

+55°C

RW0NC

10

SHDN

9

V

8

CC

SDI

7

CS

SCK

SDO

GND

RW1

1

2

3

4

56

Ordering Information

RESISTANCE OPTION

PART NUMBER PART MARKING

ISL22429UFU10Z
(Notes 1, 2)

ISL22429WFU10Z
(Notes 1, 2)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

429UZ 50 -40 to +125 10 Ld MSOP

429WZ 10 -40 to +125 10 Ld MSOP

(kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M10.118

(Pb-free)

M10.118

(Pb-free)

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006. All Rights Reserved

Block Diagram

www.BDTIC.com/Intersil

SCK

SDI

SDO

CS

SPI

INTERFACE

ISL22429

POWER-UP

INTERFACE,

CONTROL

AND STA TUS

LOGIC

V

CC

V

CC

WR1

V

CC

RW1

NON-

VOLATILE

SHDN

REGISTERS

GND

Pin Descriptions

MSOP PIN SYMBOL DESCRIPTION

1NC
2 SCK SPI interface clock input
3 SDO Open drain SPI interface data output
4 GND Device ground pin
5 RW1 “Wiper” terminal of DCP1
6CS
7 SDI SPI interface data input
8V
9SHDN

10 RW0 “Wiper” terminal of DCP0

CC

Chip Select active low input

Power supply pin
Shutdown active low input

WR0

RW0

2

FN6332.1

September 26, 2006

ISL22429

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP pin with Respect to GND. . . . . . . -0.3V to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

Latchup (Note 4) . . . . . . . . . . . . . . . . . .Class II, Level B @ +125°C

ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV

(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3.

JA

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -0.8V for all pins.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

(Note 15)

C

(Note 15)

VOLTAGE DIVIDER MODE (measured at R

INL

(Note 10)

DNL

(Note 9)
ZSerror

(Note 7)

FSerror
(Note 8)

V

MATCH

(Note 11)

TC

(Note 12)

End-to-End Resistance W option 10 kΩ

End-to-End Resistance Tolerance W and U option -20 +20 %
End-to-End Temperature Coefficient W option ±50 ppm/°C

Wiper Resistance V

W

Wiper Capacitance

W

Integral Non-linearity Monotonic over all tap positions -1 1 LSB

Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

Zero-scale Error W option 0 1 5 LSB

Full-scale Error W option -5 -1 0 LSB

DCP to DCP Matching Any two DCPs at the same tap position -2 2 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

V

i, unloaded; i = 0 or 1)

W

+ 0.3

CC

CC

U option 50 kΩ

U option ±80 ppm/°C

= 3.3V @ +25°C,

CC

wiper current = V

U option 0 0.5 2

U option -2 -1 0

Thermal Resistance (Typical, Note 3)

10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Recommended Operating Conditions

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

TYP

(NOTE 5) MAX UNIT

70 Ω

CC/RTOTAL

25 pF

θ

(°C/W)

JA

(Note 15)

(Note 15)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

3

FN6332.1

September 26, 2006

ISL22429

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

I

SB

I

SD

I

LkgDig

t

WRT

(Note 15)

t

ShdnRec

(Note 15)

Vpor Power-on Recall Voltage Minimum V

VccRamp V

t

EEPROM SPECIFICATION

t

WC

(Note 13)

SERIAL INTERFACE SPECIFICATIONS

V

V

VCC Supply Current (volatile
write/read)

V

Supply Current (volatile

CC

write/read)
VCC Supply Current (non-volatile

write/read)

Supply Current (non-volatile

V

CC

write/read)
VCC Current (standby) V

VCC Current (shutdown) V

Leakage Current, at Pins SHDN, SCK,
SDI, SDO and CS

Wiper Response Time after SPI Write
to WR Register

DCP Recall Time from Shutdown
Mode

Ramp Rate 0.2 V/ms

CC

Power-up delay VCC above Vpor, to DCP Initial Value

D

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T <
Non-volatile Write Cycle Time 12 20 ms

SHDN, SCK, SDI, and CS Input Buffer

IL

LOW Voltage
SHDN, SCK, SDI, and CS Input Buffer

IH

HIGH Voltage

10k DCP, f
and write states)

50k DCP, f
and write states)

10k DCP, f
and write states)

50k DCP, f
and write states)

= +5.5V, 10k DCP, SPI interface in

CC

standby state

= +5.5V, 50k DCP, SPI interface in

V

CC

standby state

= +3.6V, 10k DCP, SPI interface in

V

CC

standby state
V

= +3.6V, 50k DCP, SPI interface in

CC

standby state

= +5.5V @ +85°C, SPI interface in

CC

standby state
V

= +5.5V@ +125°C, SPI interface in

CC

standby state

= +3.6V @ +85°C, SPI interface in

V

CC

standby state

= +3.6V @ +125°C, SPI interface in

V

CC

standby state
Voltage at pin from GND to V

From rising edge of SHDN
stored position and RH connection

SCK rising edge of last bit of ACR data byte
to wiper stored position and RH connection

Register recall completed, and SPI Interface
in standby state

= 5MHz; (for SPI active, read

SPI

= 5MHz; (for SPI active, read

SPI

= 5MHz; (for SPI active, read

SPI

= 5MHz; (for SPI active, read

SPI

CC

signal to wiper

at which memory recall occurs 2.0 2.6 V

CC

+55°C 50 Years

-1 1 µA

-0.3 0.3*V

0.7*V

TYP

(NOTE 5) MAX UNIT

1.4 mA

450 µA

3.5 mA

2.0 mA

1.22 mA

320 µA

800 µA

250 µA

3µA

5µA

2µA

4µA

1.5 µs

1.5 µs

1.5 µs

3ms

CC

VCC+0.3 V

CC

V

4

FN6332.1

September 26, 2006