intersil ISL22426 DATA SHEET

®

Dual Digitally Controlled Potentiometer (XDCP™)

ISL22426

Data Sheet July 17, 2006

Low Noise, Low Power, SPI® Bus, 128 Taps

The ISL22426 integrates two digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI serial interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the corresponding WR.

The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.

Pinout

ISL22426

(14 LEAD TSSOP)

TOP VIEW

14

CC

SHDN

RH0

RL0

RW0

NC

1

2

3

4

5

6

7

SDIV

CS

13

RH1

12

11

RL1

RW1

10

9

GND

SDOSCK 8

FN6180.0

Features

• Two potentiometers in one package

• 128 resistor taps

• SPI serial interface

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ 3.3V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T <

• 14 Lead TSSOP

• Pb-free plus anneal product (RoHS compliant)

55°C

Ordering Information

RESISTANCE OPTION

PART NUMBER PART MARKING

ISL22426UFV14Z
(Notes 1, 2)

ISL22426WFV14Z
(Notes 1, 2)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

22426 UFVZ 50 -40 to +125 14 Ld TSSOP

22426 WFVZ 10 -40 to +125 14 Ld TSSOP

1

1-888-INTERSIL or 1-888-468-3774

(kΩ)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

(Pb-free)

(Pb-free)

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005. All Rights Reserved

M14.173

M14.173

Block Diagram

ISL22426

V

CC

SCK

SDI

SDO

CS

SHDN

SPI

INTERFACE

POWER UP

INTERFACE,

CONTROL

AND STA TUS

LOGIC

NON-

VOLATILE

REGISTERS

GND

Pin Descriptions

TSSOP PIN SYMBOL DESCRIPTION

1V

CC

2SHDNShutdown active low input
3 RH0 “High” terminal of DCP0
4 RL0 “Low” terminal of DCP0
5 RW0 “Wiper” terminal of DCP0
6NC
7 SCK SPI interface clock input
8 SDO Open drain SPI interface Data Output

9 GND Device ground pin
10 RW1 “Wiper” terminal of DCP1
11 RL1 “Low” terminal of DCP1
12 RH1 “High” terminal of DCP1
13 CS
14 SDI SPI interface Data Input

Power supply pin

Chip Select active low input

WR1

WR0

RH1

RW1

RL1

RH0
RW0

RL0

2

FN6180.0

July 17, 2006

ISL22426

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

Voltage at any DCP pin with Respect to GND. . . . . . . -0.3V to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

CC

+0.3

CC

ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV

(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3.

JA

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -0.8V for all pins.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTALRH

to RL resistance W option 10 kΩ

U option 50 kΩ

R

to RL resistance tolerance W and U option -20 +20 %

H

End-to-End Temperature Coefficient W option ±50 ppm/°C

U option ±80 ppm/°C

V

, VRLVRH and VRL Terminal Voltages VRH and VRL to GND 0 V

RH

R

C

H/CL/CW

(Note 21)

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ R

INL

Wiper resistance VCC = 3.3V @ +25°C, wiper current =

W

Potentiometer capacitance

Leakage on DCP pins

i; VCC @ RHi; measured at RWi, unloaded; i = 0 or 1)

L

V

CC/RTOTAL

Voltage at pin from GND to V

Integral non-linearity Monotonic over all tap positions -1 1 LSB

(Note 10)

DNL

Differential non-linearity Monotonic over all tap positions -0.5 0.5 LSB

(Note 9)
ZSerror

(Note 7)

FSerror
(Note 8)

V

MATCH

(Note 11)

TC

(Note 12)

Zero-scale error W option 0 1 5 LSB

U option 0 0.5 2

Full-scale error W option -5 -1 0 LSB

U option -2 -1 0

DCP to DCP matching Any two DCPs at same tap position, same

voltage at all RH terminals, and same voltage
at all R

terminals

L

Ratiometric temperature coefficient DCP register set to 40 hex ±4 ppm/°C

V

Thermal Resistance (Typical, Note 3)

θ

JA

(°C/W)

14 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Recommended Operating Conditions

Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C

Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(NOTE 5) MAX UNIT

(Note 21)

(Note 21)

V

(Note 6)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

CC

CC

70 200 Ω

10/10/25 pF

0.1 1 µA

-2 2 LSB

3

FN6180.0

July 17, 2006

ISL22426

Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected; i = 0 or 1)

RINL

(Note 16)

RDNL

(Note 15)

Roffset

Integral non-linearity DCP register set between 10h and 7Fh;

-1 1 MI

monotonic over all tap positions

Differential non-linearity DCP register set between 10h and 7Fh;

-0.5 0.5 MI

monotonic over all tap positions

Offset W option 0 1 7 MI

(Note 14)

U option 0 0.5 2 MI

R

MATCH

(Note 17)

DCP to DCP matching Any two DCPs at the same tap position with

the same terminal voltages

-2 2 MI

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

I

SB

I

SD

I

LkgDig

t

WRT

(Note 21)

t

ShdnRec

VCC supply current (volatile
write/read)

VCC supply current (non-volatile
write/read)

VCC current (standby) V

VCC current (shutdown) V

Leakage current, at pins SHDN, SCK,
SDI, SDO and CS

Wiper Response Time after SPI write
to WR register

DCP recall time from shutdown mode From rising edge of SHDN

(Note 21)

Vpor Power-on recall voltage Minimum V

VccRamp V

t

D

ramp rate 0.2 V/ms

CC

Power-up delay VCC above Vpor, to DCP Initial Value

f

= 5MHz; (for SPI Active, Read and

SCK

Volatile Write states only)
f

= 5MHz; (for SPI Active, Read and Non-

SCK

volatile Write states only)

= +5.5V @ +85°C, SPI interface in

CC

standby state
V

= +5.5V @ +125°C, SPI interface in

CC

standby state
V

= +3.6V @ +85°C, SPI interface in

CC

standby state

= +3.6V @ +125°C, SPI interface in

V

CC

standby state

= +5.5V @ +85°C, SPI interface in

CC

standby state
V

= +5.5V @ +125°C, SPI interface in

CC

standby state

= +3.6V @ +85°C, SPI interface in

V

CC

standby state
V

= +3.6V @ +125°C, SPI interface in

CC

standby state
Voltage at pin from GND to V

CC

signal to wiper

stored position and RH connection
SCK rising edge of last bit of ACR data byte

to wiper stored position and RH connection

at which memory recall occurs 2.0 2.6 V

CC

Register recall completed, and SPI Interface
in standby state

-1 1 µA

TYP

(NOTE 5) MAX UNIT

(Note 13)

(Note 13)

(Note 13)

(Note 13)

(Note 13)

TYP

(NOTE 5) MAX UNIT

0.5 mA

3mA

5µA

7µA

3µA

5µA

3µA

5µA

2µA

4µA

1.5 µs

1.5 µs

1.5 µs

3ms

4

FN6180.0

July 17, 2006