intersil ISL22416 DATA SHEET

®

www.BDTIC.com/Intersil

Single Digitally Controlled Potentiometer (XDCP™)

ISL22416

Data Sheet February 18, 2008

Low Noise, Low Power, SPI® Bus, 128 Taps

The ISL22416 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up, the device recalls the contents of the
DCP’s IVR to the WR.

The DCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

Pinout

ISL22416

(10 LD MSOP)

TOP VIEW

FN6227.1

Features

• 128 resistor taps

• SPI serial interface

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ +55°C

• 10 Ld MSOP and 10 Ld TDFN package

• Pb-free (RoHS compliant)

ISL22416

(10 LD TDFN)

TOP VIEW

CC

= 3.3V

SDI

CS

O

1

2

3

4

5

10

VCCSCK

9

RH

8

RW

7

RL

6

GND

SDO

SDI

CS

SHDN

10

1

2

3

4

5

VCCSCK

RH

9

RW

8

7

RL

GND

6

SDO

SHDN

Ordering Information

PART NUMBER

(Note) PART MARKING

ISL22416UFU10Z* 416UZ 50 -40 to +125 10 Ld MSOP M10.118
ISL22416UFRT10Z* 416U 50 -40 to +125 10 Ld 3x3 TDFN L10.3x3B
ISL22416WFU10Z* 416WZ 10 -40 to +125 10 Ld MSOP M10.118
ISL22416WFRT10Z* 416W 10 -40 to +125 10 Ld 3x3 TDFN L10.3x3B
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

RESISTANCE OPTION

(kΩ)

TEMP. RANGE

(°C)

PACKAGE

(Pb-free) PKG. DWG. #

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved

Block Diagram

www.BDTIC.com/Intersil

ISL22416

V

CC

SCK
SDO

SDI

CS

SHDN

SPI

INTERFACE

POWER-UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

IVR

NON-VOLATILE

REGISTER

GND

WR

Pin Descriptions

MSOP/TDFN PIN NUMBER SYMBOL DESCRIPTION

1 SCK SPI interface clock input
2 SDO Push-pull/Open Drain Data Output of the SPI serial interface
3 SDI Data Input of the SPI serial interface
4CS
5 SHDN Shutdown active low input
6 GND Device ground pin
7 RL “Low” terminal of DCP
8 RW “Wiper” terminal of DCP
9 RH “High” terminal of DCP

10 V

CC

Chip Select active low input

Power supply pin

RH

RW

RL

2

FN6227.1

February 18, 2008

ISL22416

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP pin with Respect to GND. . . . . . . -0.3V to V

IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Latchup (Note 1) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

ESD

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV

Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θ

JA

3. For θ

Analog Specifications Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

R

V

C

H/CL/CW

(Note 18)

I

VOLTAGE DIVIDER MODE (0V @ R

(Note 9)

(Note 8)
ZSerror

(Note 6)
FSerror

(Note 7)

(Note 10, 18)

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

TOTAL

R

, V

RH

LkgDCP

INL

DNL

TC

RH to RL Resistance W option 10 kΩ

R

to RL Resistance Tolerance W and U option -20 +20 %

H

End-to-End Temperature Coefficient W option ±50 ppm/°C

Wiper Resistance VCC = 3.3V, wiper current = VCC/R

W

RLVRH

V

and VRL Terminal Voltages VRH and VRL to GND 0 V

Potentiometer Capacitance 10/10/25 pF

Leakage on DCP Pins Voltage at pin from GND to V

; VCC @ RH; measured at RW, unloaded)

L

Integral Non-linearity Monotonic over all tap positions, W and U

Differential Non-linearity Monotonic over all tap positions, W and U

Zero-scale Error W option 0 1 5 LSB

Full-scale Error W option -5 -1 0 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex for W and U

+0.3

CC

CC

U option 50 kΩ

U option ±80 ppm/°C

option

option

U option 0 0.5 2

U option -2 -1 0

option

Thermal Resistance (Typical) θ

10 Lead MSOP (Note 2). . . . . . . . . . . . 120 N/A

10 Lead TDFN (Notes 2, 3) . . . . . . . . . 150 48.3

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C

Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

MIN

(Note )

TOTAL

CC

-1 1 LSB

-0.5 0.5 LSB

TYP

(Note 4)

0.1 1 µA

(°C/W) θJC (°C/W)

JA

MAX

(Note ) UNIT

(Note 18)

(Note 18)

70 200 Ω

CC

±4 ppm/°C

V

(Note 5)

(Note 5)

(Note 5)

(Note 5)

3

FN6227.1

February 18, 2008

ISL22416

www.BDTIC.com/Intersil

Analog Specifications Over recommended operating conditions, unless otherwise stated. (Continued)

MIN

SYMBOL PARAMETER TEST CONDITIONS

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

RINL

(Note 14)

RDNL

(Note 13)

Roffset

(Note 12)

Integral Non-linearity DCP register set between 10 hex and 7F

hex; monotonic over all tap positions;
W and U option

Differential Non-linearity W option -1 1 MI

U option -0.5 0.5 MI

Offset W option 0 1 5 MI

U option 0 0.5 2 MI

(Note )

-1 1 MI

Operating Specifications Over the recommended operating conditions, unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

SB

I

SD

I

LkgDig

t

WRT

(Note 18)

t

ShdnRec

(Note 18)

V

POR

Ramp VCC Ramp Rate 0.2 V/ms

V

CC

t

VCC Supply Current (Volatile
Write/Read)

VCC Supply Current (Non-volatile
Write/Read)

VCC Current (Standby) V

VCC Current (Shutdown) V

Leakage Current, at Pins SHDN, SCK,
SDI, SDO and CS

Wiper Response Time Wiper Response Time after SPI write to WR

DCP Recall Time from Shutdown
Mode

Power-on Recall Voltage Minimum VCC at which memory recall occurs 2.0 2.6 V

Power-up Delay VCC above V

D

f

= 5MHz; (for SPI Active, Read and

SCK

Volatile Write states only)
f

= 5MHz; (for SPI Active, Read and

SCK

Non-volatile Write states only)

= +5.5V @ +85°C, SPI interface in

CC

standby state

= +5.5V @ +125°C, SPI interface in

V

CC

standby state
V

= +3.6V @ +85°C, SPI interface in

CC

standby state

= +3.6V @ +125°C, SPI interface in

V

CC

standby state

= +5.5V @ +85°C, SPI interface in

CC

standby state
V

= +5.5V @ +125°C, SPI interface in

CC

standby state

= +3.6V @ +85°C, SPI interface in

V

CC

standby state

= +3.6V @ +125°C, SPI interface in

V

CC

standby state
Voltage at pin from GND to V

SDO is inactive

register
From rising edge of SHDN

stored position and RH connection
SCK rising edge of last bit of ACR data byte

to wiper stored position and RH connection

, to DCP Initial Value
Register recall completed, and SPI Interface
in standby state

POR

CC,

signal to wiper

MIN

(Note )

-1 1 µA

TYP

(Note 4)

TYP

(Note 4)

1.5 µs

1.5 µs

1.5 µs

MAX

(Note ) UNIT

MAX

(Note ) UNIT

0.5 mA

3mA

5µA

7µA

3µA

5µA

3µA

5µA

2µA

4µA

3ms

(Note 11)

(Note 11)

(Note 11)

(Note 11)

(Note 11)

4

FN6227.1

February 18, 2008

ISL22416

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

(Note )

EEPROM SPECIFICATION

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T ≤ +55°C 50 Years

MIN

t

WC

Non-volatile Write Cycle Time 12 20 ms

(Note 16)

SERIAL INTERFACE SPECIFICATIONS

V

SHDN, SCK, SDI, and CS Input Buffer

IL

-0.3 0.3*V

LOW Voltage

V

IH

Hysteresis

V

OL

R

pu

(Note 17)

Cpin

(Note 18)

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

V

t

HO

t

RO

t

FO

t

CS

SHDN, SCK, SDI, and CS Input Buffer
HIGH Voltage

SHDN, SCK, SDI, and CS Input Buffer
Hysteresis

SDO Output Buffer LOW Voltage IOL = 4mA 0 0.4 V
SDO Pull-up Resistor Off-chip Maximum is determined by t

maximum bus load Cb = 30pF, f

SHDN

, SCK, SDI, SDO and CS Pin

and tFO with

RO

= 5MHz

SCK

Capacitance
SPI Frequency 5MHz
SPI Clock Cycle Time 200 ns
SPI Clock High Time 100 ns
SPI Clock Low Time 100 ns
Lead Time 250 ns
Lag Time 250 ns
SDI, SCK and CS Input Setup Time 50 ns
SDI, SCK and CS Input Hold Time 50 ns
SDI, SCK and CS Input Rise Time 10 ns
SDI, SCK and CS Input Fall Time 10 20 ns
SDO Output Disable Time 0 100 ns
SDO Output Valid Time 350 ns
SDO Output Hold Time 0 ns
SDO Output Rise Time Rpu = 2k, Cbus = 30pF 60 ns
SDO Output Fall Time Rpu = 2k, Cbus = 30pF 60 ns
CS Deselect Time 2µs

0.7*V

0.05*
V

CC

CC

NOTES:

4. Typical values are for T

5. LSB: [V(R
incremental voltage when changing from one tap to an adjacent tap.

– V(RW)0]/127. V(RW)

W)127

6. ZS error = V(RW)

7. FS error = [V(RW)

8. DNL = [V(RW)

9. INL = [V(RW)

10. for i = 16 to 127 decimal, T = -40°C to 12 5°C. Max( ) is the ma ximum value of the wiper

----------------------------------------------------------------------------------------------

C

V

– V(RW)

i

– (i • LSB) – V(RW)0]/LSB for i = 1 to 127

i

Max V RW()

()Min V RW()

Max V RW()

()Min V RW()

= +25°C and 3.3V supply voltage.

A

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LS B is the

127

/LSB.

0

– VCC]/LSB.

127

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

()–

i

i

()+[]2⁄

i

×=

i

6

10

-------------------- -

+165°C

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

TYP

(Note 4)

MAX

(Note ) UNIT

CC

V

+ 0.3 V

CC

2kΩ

10 pF

V

V

5

FN6227.1

February 18, 2008