intersil ISL22416 DATA SHEET

®

www.BDTIC.com/Intersil

Single Digitally Controlled Potentiometer (XDCP™)

ISL22416

Data Sheet February 18, 2008

Low Noise, Low Power, SPI® Bus, 128 Taps

The ISL22416 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up, the device recalls the contents of the
DCP’s IVR to the WR.

The DCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

Pinout

ISL22416

(10 LD MSOP)

TOP VIEW

FN6227.1

Features

• 128 resistor taps

• SPI serial interface

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ +55°C

• 10 Ld MSOP and 10 Ld TDFN package

• Pb-free (RoHS compliant)

ISL22416

(10 LD TDFN)

TOP VIEW

CC

= 3.3V

SDI

CS

O

1

2

3

4

5

10

VCCSCK

9

RH

8

RW

7

RL

6

GND

SDO

SDI

CS

SHDN

10

1

2

3

4

5

VCCSCK

RH

9

RW

8

7

RL

GND

6

SDO

SHDN

Ordering Information

PART NUMBER

(Note) PART MARKING

ISL22416UFU10Z* 416UZ 50 -40 to +125 10 Ld MSOP M10.118
ISL22416UFRT10Z* 416U 50 -40 to +125 10 Ld 3x3 TDFN L10.3x3B
ISL22416WFU10Z* 416WZ 10 -40 to +125 10 Ld MSOP M10.118
ISL22416WFRT10Z* 416W 10 -40 to +125 10 Ld 3x3 TDFN L10.3x3B
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

RESISTANCE OPTION

(kΩ)

TEMP. RANGE

(°C)

PACKAGE

(Pb-free) PKG. DWG. #

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved

Block Diagram

www.BDTIC.com/Intersil

ISL22416

V

CC

SCK
SDO

SDI

CS

SHDN

SPI

INTERFACE

POWER-UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

IVR

NON-VOLATILE

REGISTER

GND

WR

Pin Descriptions

MSOP/TDFN PIN NUMBER SYMBOL DESCRIPTION

1 SCK SPI interface clock input
2 SDO Push-pull/Open Drain Data Output of the SPI serial interface
3 SDI Data Input of the SPI serial interface
4CS
5 SHDN Shutdown active low input
6 GND Device ground pin
7 RL “Low” terminal of DCP
8 RW “Wiper” terminal of DCP
9 RH “High” terminal of DCP

10 V

CC

Chip Select active low input

Power supply pin

RH

RW

RL

2

FN6227.1

February 18, 2008

ISL22416

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP pin with Respect to GND. . . . . . . -0.3V to V

IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Latchup (Note 1) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

ESD

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV

Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θ

JA

3. For θ

Analog Specifications Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

R

V

C

H/CL/CW

(Note 18)

I

VOLTAGE DIVIDER MODE (0V @ R

(Note 9)

(Note 8)
ZSerror

(Note 6)
FSerror

(Note 7)

(Note 10, 18)

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

TOTAL

R

, V

RH

LkgDCP

INL

DNL

TC

RH to RL Resistance W option 10 kΩ

R

to RL Resistance Tolerance W and U option -20 +20 %

H

End-to-End Temperature Coefficient W option ±50 ppm/°C

Wiper Resistance VCC = 3.3V, wiper current = VCC/R

W

RLVRH

V

and VRL Terminal Voltages VRH and VRL to GND 0 V

Potentiometer Capacitance 10/10/25 pF

Leakage on DCP Pins Voltage at pin from GND to V

; VCC @ RH; measured at RW, unloaded)

L

Integral Non-linearity Monotonic over all tap positions, W and U

Differential Non-linearity Monotonic over all tap positions, W and U

Zero-scale Error W option 0 1 5 LSB

Full-scale Error W option -5 -1 0 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex for W and U

+0.3

CC

CC

U option 50 kΩ

U option ±80 ppm/°C

option

option

U option 0 0.5 2

U option -2 -1 0

option

Thermal Resistance (Typical) θ

10 Lead MSOP (Note 2). . . . . . . . . . . . 120 N/A

10 Lead TDFN (Notes 2, 3) . . . . . . . . . 150 48.3

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C

Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

MIN

(Note )

TOTAL

CC

-1 1 LSB

-0.5 0.5 LSB

TYP

(Note 4)

0.1 1 µA

(°C/W) θJC (°C/W)

JA

MAX

(Note ) UNIT

(Note 18)

(Note 18)

70 200 Ω

CC

±4 ppm/°C

V

(Note 5)

(Note 5)

(Note 5)

(Note 5)

3

FN6227.1

February 18, 2008

ISL22416

www.BDTIC.com/Intersil

Analog Specifications Over recommended operating conditions, unless otherwise stated. (Continued)

MIN

SYMBOL PARAMETER TEST CONDITIONS

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

RINL

(Note 14)

RDNL

(Note 13)

Roffset

(Note 12)

Integral Non-linearity DCP register set between 10 hex and 7F

hex; monotonic over all tap positions;
W and U option

Differential Non-linearity W option -1 1 MI

U option -0.5 0.5 MI

Offset W option 0 1 5 MI

U option 0 0.5 2 MI

(Note )

-1 1 MI

Operating Specifications Over the recommended operating conditions, unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

SB

I

SD

I

LkgDig

t

WRT

(Note 18)

t

ShdnRec

(Note 18)

V

POR

Ramp VCC Ramp Rate 0.2 V/ms

V

CC

t

VCC Supply Current (Volatile
Write/Read)

VCC Supply Current (Non-volatile
Write/Read)

VCC Current (Standby) V

VCC Current (Shutdown) V

Leakage Current, at Pins SHDN, SCK,
SDI, SDO and CS

Wiper Response Time Wiper Response Time after SPI write to WR

DCP Recall Time from Shutdown
Mode

Power-on Recall Voltage Minimum VCC at which memory recall occurs 2.0 2.6 V

Power-up Delay VCC above V

D

f

= 5MHz; (for SPI Active, Read and

SCK

Volatile Write states only)
f

= 5MHz; (for SPI Active, Read and

SCK

Non-volatile Write states only)

= +5.5V @ +85°C, SPI interface in

CC

standby state

= +5.5V @ +125°C, SPI interface in

V

CC

standby state
V

= +3.6V @ +85°C, SPI interface in

CC

standby state

= +3.6V @ +125°C, SPI interface in

V

CC

standby state

= +5.5V @ +85°C, SPI interface in

CC

standby state
V

= +5.5V @ +125°C, SPI interface in

CC

standby state

= +3.6V @ +85°C, SPI interface in

V

CC

standby state

= +3.6V @ +125°C, SPI interface in

V

CC

standby state
Voltage at pin from GND to V

SDO is inactive

register
From rising edge of SHDN

stored position and RH connection
SCK rising edge of last bit of ACR data byte

to wiper stored position and RH connection

, to DCP Initial Value
Register recall completed, and SPI Interface
in standby state

POR

CC,

signal to wiper

MIN

(Note )

-1 1 µA

TYP

(Note 4)

TYP

(Note 4)

1.5 µs

1.5 µs

1.5 µs

MAX

(Note ) UNIT

MAX

(Note ) UNIT

0.5 mA

3mA

5µA

7µA

3µA

5µA

3µA

5µA

2µA

4µA

3ms

(Note 11)

(Note 11)

(Note 11)

(Note 11)

(Note 11)

4

FN6227.1

February 18, 2008

ISL22416

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

(Note )

EEPROM SPECIFICATION

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T ≤ +55°C 50 Years

MIN

t

WC

Non-volatile Write Cycle Time 12 20 ms

(Note 16)

SERIAL INTERFACE SPECIFICATIONS

V

SHDN, SCK, SDI, and CS Input Buffer

IL

-0.3 0.3*V

LOW Voltage

V

IH

Hysteresis

V

OL

R

pu

(Note 17)

Cpin

(Note 18)

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

V

t

HO

t

RO

t

FO

t

CS

SHDN, SCK, SDI, and CS Input Buffer
HIGH Voltage

SHDN, SCK, SDI, and CS Input Buffer
Hysteresis

SDO Output Buffer LOW Voltage IOL = 4mA 0 0.4 V
SDO Pull-up Resistor Off-chip Maximum is determined by t

maximum bus load Cb = 30pF, f

SHDN

, SCK, SDI, SDO and CS Pin

and tFO with

RO

= 5MHz

SCK

Capacitance
SPI Frequency 5MHz
SPI Clock Cycle Time 200 ns
SPI Clock High Time 100 ns
SPI Clock Low Time 100 ns
Lead Time 250 ns
Lag Time 250 ns
SDI, SCK and CS Input Setup Time 50 ns
SDI, SCK and CS Input Hold Time 50 ns
SDI, SCK and CS Input Rise Time 10 ns
SDI, SCK and CS Input Fall Time 10 20 ns
SDO Output Disable Time 0 100 ns
SDO Output Valid Time 350 ns
SDO Output Hold Time 0 ns
SDO Output Rise Time Rpu = 2k, Cbus = 30pF 60 ns
SDO Output Fall Time Rpu = 2k, Cbus = 30pF 60 ns
CS Deselect Time 2µs

0.7*V

0.05*
V

CC

CC

NOTES:

4. Typical values are for T

5. LSB: [V(R
incremental voltage when changing from one tap to an adjacent tap.

– V(RW)0]/127. V(RW)

W)127

6. ZS error = V(RW)

7. FS error = [V(RW)

8. DNL = [V(RW)

9. INL = [V(RW)

10. for i = 16 to 127 decimal, T = -40°C to 12 5°C. Max( ) is the ma ximum value of the wiper

----------------------------------------------------------------------------------------------

C

V

– V(RW)

i

– (i • LSB) – V(RW)0]/LSB for i = 1 to 127

i

Max V RW()

()Min V RW()

Max V RW()

()Min V RW()

= +25°C and 3.3V supply voltage.

A

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LS B is the

127

/LSB.

0

– VCC]/LSB.

127

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

()–

i

i

()+[]2⁄

i

×=

i

6

10

-------------------- -

+165°C

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

TYP

(Note 4)

MAX

(Note ) UNIT

CC

V

+ 0.3 V

CC

2kΩ

10 pF

V

V

5

FN6227.1

February 18, 2008

ISL22416

www.BDTIC.com/Intersil

NOTES: (Continued)

11. MI =

12. Roffset = RW

13. RDNL = (RW

14. RINL = [RW

15. for i = 16 to 127, T = -40°C to 125°C. Max( ) is the maximum value of the resistance and Min ( ) is

16. t

17. R

|RW

– RW

00 hex respectively.

127

Roffset = RW

Max Ri()Min Ri()–[]

--------------------------------------------------------------- -

TC

R

Max Ri()Min Ri()+[]2⁄

is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.

WC

is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.

pu

|/127. MI is a minimum increment. RW

0

/MI, when measuring between RW and RL.

0

/MI, when measuring between RW and RH.

127

– RW

i

– (MI • i) – RW0]/MI, for i = 1 to 127.

i

)/MI -1, for i = 1 to 127.

i-1

10

---------------- -

×=

165°C

6

the minimum value of the resistance over the temperature range.

and RW0 are the measured resistances for the DCP register set to 7F hex and

127

18. Limits should be considered typical and are not production tested.
Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.

Timing Diagrams

Input Timing

t

CS

CS

t

LEAD

t

CYC

t

LAG

SCK

SDI

SDO

Output Timing

CS

SCK

SDO

SDI

t

SU

MSB LSB

HIGH IMPEDANCE

ADDR

t

H

t

V

MSB

t

WL

...

t

WH

...

t

HO

t

FI

...

...

t

RI

t

DIS

LSB

6

FN6227.1

February 18, 2008

XDCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

ISL22416

CS

SCK

SDI

V

SDO

W

HIGH IMPEDANCE

MSB LSB

Typical Performance Curves

100

VCC = 3.3V, T = +125°C

90
80
70
60
50
40
30

VCC = 3.3V, T = +20°C

20

WIPER RESISITANCE (Ω)

10

0

020406080100120

TAP POSITI ON (DECIMAL)

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[ I(RW) = V

CC/RTOTAL

V

= 3.3V, T = -40°C

CC

] FOR 10kΩ (W)

...

...

1.4

1.2

1.0

0.8

(µA)

0.6

SB

I

0.4

0.2

0

2.7 3.2 3.7 4.2 4.7 5.2

t

WRT

T = +125°C

T = +25°C

V

(V)

CC

FIGURE 2. STANDBY I

CC

vs V

CC

t

WC

0.2

VCC = 2.7V

0.1

0

DNL (LSB)

-0.1

VCC = 5.5V

-0.2
0 20406080100120

TAP POSITION (DECIMAL)

T = +25°C

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

7

0.2

0.1

0

INL (LSB)

-0.1

-0.2
0 20 40 60 80 100 120

VCC = 2.7V

VCC = 5.5V

TAP POSITION (DECIMAL)

T = +25°C

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

FN6227.1

February 18, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

1.3

1.1

0.9

0.7

(LSB)

0.5

ERROR

0.3

ZS

0.1

-0.1

-0.3

-40 -20 0 20 40 60 80 100 120

FIGURE 5. ZS

10k

VCC = 5.5V

VCC = 2.7V

50k

TEMPERATURE (°C)

vs TEMPERATURE FIGURE 6. FS

ERROR

ISL22416

0.0

-0.3
VCC = 2.7V

-0.6

(LSB)

-0.9

ERROR

ZS

-1.2

-1.5

-40 -20 0 20 40 60 80 100 120

50k

10k

TEMPERATURE (ºC)

vs TEMPERATURE

ERROR

VCC = 5.5V

0.4

0.2

0

-0.2

DNL (LSB)

-0.4
VCC = 2.7V

-0.6

16 36 56 76 96 116

VCC = 5.5V

TAP POSITION (DECIMAL)

T = +25°C

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

10kΩ (W)

1.0

0.5

CHANGE (%)

0.0

VCC = 5.5V

TOTAL

-0.5

END TO END R

-1.0

-40 -20 0 20 40 60 80 100 120

FIGURE 9. END TO END R

VCC = 2.7V

10k

TEMPERATURE (ºC)

% CHANGE vs

TOTAL

50k

TEMPERATURE

0.4

0.2

0

-0.2

INL (LSB)

-0.4

-0.6
16 36 56 76 96 116

VCC = 5.5V

TAP POSITION (DECIMAL)

T = +25°C

VCC = 2.7V

FIGURE 8. INL vs TAP POSITION IN RHEOST AT MODE FOR

10kΩ (W)

105

90

75

60

45

TCv (ppm/°C)

50k

30

15

0

16 36 56 76 96

10k

TAP POSITION (DECIMAL)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

8

FN6227.1

February 18, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL22416

INPUT

300

250

200

150

TCr (ppm/°C)

100

50

0

16 36 56 76 96

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (2.6MHz)

SIGNAL AT WIPER
(WIPER UNLOADED)

50k

TAP POSITION (DECIMAL)

10k

WIPER AT MID POINT (POSITION 40h)
R

= 9.5kΩ

TOTAL

SCL

OUTPUT

SIGNAL AT WIPER
(WIPER UNLOADED MOVEMENT
FROM 7Fh TO 00h)

WIPER MID POINT MOVEMENT
FROM 3Fh TO 40h

FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h FIGURE 14. LARGE SIGNAL SETTLING TIME

Pin Description

Potentiometer Pins

RH AND RL

The high (RH) and low (RL) terminals of the ISL22416 are
equivalent to the fixed terminals of a mechanical
potentiometer. RH and RL are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WR set to 127 decimal, the wiper will be
closest to RH, and with the WR set to 0, the wiper is closest

SHDN

The SHDN pin forces the resistor to end-to-end open circuit
condition on RH and shorts RW to RL. When SHDN
returned to logic high, the previous latch settings put RW at
the same resistance setting prior to shutdown. This pin is
logically OR’d with SHDN bit in ACR register. SPI interface is
still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation.

RH

to RL.

RW

RW

RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.

RL

is

FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE

9

FN6227.1

February 18, 2008

ISL22416

www.BDTIC.com/Intersil

Bus Interface Pins

SERIAL CLOCK (SCK)

This is the serial clock input of the SPI serial interface.

SERIAL DATA OUTPUT (SDO)

The SDO is an open drain serial data output pin. During a
read cycle, the data bits are shifted out at the falling edge of
the serial clock SCK, while the CS input is low.

SDO requires an external pull-up resistor for proper
operation.

SERIAL DATA INPUT (SDI)

The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI external host device. The data bits are
shifted in at the rising edge of the serial clock SCK, while the
CS

input is low.

CHIP SELECT (CS)

LOW enables the ISL22416, placing it in the active

CS
power mode. A HIGH to LOW transition on CS
prior to the start of any operation after power up. When CS
HIGH, the ISL22416 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.

is required

is

Principles of Operation

The ISL22416 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and the
SPI serial interface providing direct communication between
host and potentiometer and memory. The resistor array is
comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.

When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.

DCP Description

The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position of
the wiper terminal within the DCP is controlled by a 7-bit
volatile Wiper Register (WR). When the WR of a DCP
contains all zeroes (WR<6:0>: 00h), it s wiper terminal (R W) is
closest to its “Low” terminal (RL). When the WR register of a
DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal

(RW) is closest to its “High” terminal (RH). As the value of the
WR increases from all zeroes (0) to all ones (127 decimal),
the wiper moves monotonically from the position closest to RL
to the closest to RH. At the same time, the resistance between
RW and RL increases monotonically, while the resistance
between RH and RW decreases monotonically.

While the ISL22416 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reload with the value stored in a
non-volatile Initial Value Register (IVR).

The WR and IVR can be read or written to directly using the
SPI serial interface as described in the following sections.

Memory Description

The ISL22416 contains one non-volatile 7-bit register, known
as the Initial V alue Register (IVR), volatile 7-bit Wiper Register
(WR), and volatile 8-bit Access Control Register (ACR). The
memory map is shown in Table 1. The non-volatile register
(IVR) at address 0, contain initial wiper position and volatile
registers (WR) contain current wiper position.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

2— ACR
1Reserved
0IVR WR

The non-volatile IVR and volatile WR registers are
accessible with the same address.

The Access Control Register (ACR) contains information
and control bits described in Table 2.

The VOL bit (ACR<7>) determines whether the access is to
wiper registers WR or initial value registers IVR.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

BIT # 765

BIT NAME VOL SHDN WIP

If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.

The SHDN bit (ACR<6>) disables or enables Shutdown mode.
This bit is logically OR’d with SHDN
is in Shutdown mode. Default value of SHDN bit is 1.

The WIP bit (ACR<5>) is read only bit. It indicates that
non-volatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write to the WR or
ACR while WIP bit is 1.

43210
00000

pin. When this bit is 0, DCP

10

FN6227.1

February 18, 2008

CS

www.BDTIC.com/Intersil

SCK

SDI

ISL22416

0 101 00 I3I2 I1I000 R1R0

00

0

FIGURE 16. THREE BYTE WRITE SEQUENCE

SPI Serial Interface

The ISL22416 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS
communication with the ISL22416. SCK and CS
controlled by the host or master. The ISL22416 operates
only as a slave device.

All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.

must be LOW during

lines are

Protocol Conventions

The first byte sent to the ISL22416 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.

TABLE 3. IDENTIFICATION BYTE FORMAT

01010000

(MSB) (LSB)

The next byte sent to the ISL22416 contains the instruction
and register pointer information. The four MSBs are the
instruction and two LSBs are register address (see Table 4).

TABLE 4. IDENTIFICATION BYTE FORMAT

0 D6D5D4 D3 D2 D1D0

determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” on page 10 and Figure 16.

The internal non-volatile write cycle starts after rising edge of
CS

and takes up to 20ms.

Read Operation

A read operation to the ISL22416 is a three byte operation. It
requires first, the CS
valid Identification Byte, then a valid instruction byte followed
by “dummy” Data Byte is sent to SDI pin. The SPI host reads
the data from SDO pin on falling edge of SCK. The host
terminates the read operation by pulling the CS
LOW to HIGH (see Figure 17).

In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.

transition from HIGH to LOW, then a

pin from

Applications Information

Communicating with ISL22416

Communication with ISL22416 proceeds using SPI interface
through the ACR (address 10b), IVR (address 00b) and WR
(address 00b) registers.

76543210

I3 I2 I1 I0 0 0 R1 R0

There are only two valid instruction sets:
1011(binary) - is a Read operation
11 00(binary) - is a Write operation
There are only two registers address possible for this DCP. If

the R1, R0 bits are zero, then the read or write is to ei ther the
IVR or the WR register (depends of VOL bit at ACR). If the R1
bit is 1 and R0 bit is 0, then the operation is on the ACR.

The wiper of the potentiometer is controlled by the WR
register. Writes and reads can be made directly to this
register to control and monitor the wiper position without any
non-volatile memory changes. This is done by setting MSB
bit at address 10b to 1.

The non-volatile IVR stores the power up value of the wiper.
IVR is accessible when MSB bit at address 10b is set to 0.
Writing a new value to the IVR register will set a new power
up position for the wiper. Also, writing to this register will load
the same value into the WR as the IVR. Reading from the
IVR will not change the WR, if its contents are different.

Write Operation

A Write operation to the ISL22416 is a three-byte operation.
It requires first, the CS
valid Identification Byte, then a valid instruction byte followed
by Data Byte is sent to SDI pin. The host terminates the write
operation by pulling the CS
write to address 0 (WR), the byte at address 2 (ACR<7>)

transition from HIGH to LOW, then a

pin from LOW to HIGH. For a

11

FN6227.1

February 18, 2008

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SCK

ISL22416

SDI

0 101 00 I3 I2 I1 I0 0 0 R1 R0

SDO

00

0

FIGURE 17. THREE BYTE READ SEQUENCE

Examples

A. Writing to the IVR

This sequence will write a new value (77h) to the IVR
(non-volatile):

Set the ACR (Addr 02h) for NV write (40h)
Send the ID byte, Instruction Byte, then the Data byte

010100001100001001000000

(Sent to DI)

Set the IVR (Addr 00h) to 77h
Send the ID byte, Instruction Byte, then the Data byte

010100001100000001110111

(Sent to DI)

DON’T CARE

0 D6D5D4 D3 D2 D1D0

B. Reading from the WR

This sequence will read the value from the WR (volatile):
Write to ACR first to access the WR
Send the ID byte, Instruction Byte, then the Data byte

010100001100001011000000

(Sent to DI)

Read the data from WR (Addr 00h)
Send the ID byte, Instruction Byte, then Read the Data byte

0101000010110000xxxxxxxx

(Out on DO)

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February 18, 2008

ISL22416

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Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

TOP VIEW

-H-

SIDE VIEW

12

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.007 0.011 0.18 0.27 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

o

θ

α

5

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 0 12/02

NOTESMIN MAX MIN MAX

-

-

13

FN6227.1

February 18, 2008

ISL22416

www.BDTIC.com/Intersil

Thin Dual Flat No-Lead Plastic Package (TDFN)

(DATUM B)

6

INDEX

AREA

(DATUM A)

NX (b)

5

SECTION "C-C"

6

INDEX

AREA

SEATING

PLANE

NX L

8

A

C

D

TOP VIEW

SIDE VIEW

D2

D2/2

12

N

N-1

e
(Nd-1)Xe

REF.

BOTTOM VIEW

(A1)

2X

A3

E2/2

NX b

5

C

L

e

CC

FOR ODD TERMINAL/SIDE

87

E

A

NX k

E2

0.10

ABC0.15

2X

0.15

//

M

9

TERMINAL TIP

0.10

0.08

L

CB

BAC

L10.3x3B

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A
A1
A3

b

D

D2

E

C

C

E2

e
k
L

0.70 0.75 0.80

- - 0.05

0.20 REF

0.18 0.25 0.30

3.00 BSC

2.23 2.38 2.48

3.00 BSC

1.49 1.64 1.74

0.50 BSC

0.20 - -

0.30 0.40 0.50

N102

Nd 5 3

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.

NOTESMIN NOMINAL MAX

-

-

-

5, 8

-

7, 8

-

7, 8

-

-

8

Rev. 0 2/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidi aries.

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14

FN6227.1

February 18, 2008