intersil ISL22414 DATA SHEET

®

ISL22414

Single Digitally Controlled Potentiometer (XDCP™)

Data Sheet July 17, 2007

Low Noise, Low Power, SPI® Bus, 256 Taps

The ISL22414 integrates a single digitally controlled
potentiometer (DCP), control logic and non-volatile memory
on a monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR control the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the WR.

The ISL22414 also has 14 General Purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.

The ISL22414 features a dual supply, that is beneficial for
applications requiring a bipolar range for DCP terminals
between V- and VCC.

The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.

Pinout

ISL22414

(10 LD MSOP)

TOP VIEW

SDO

SDI

CS

O

1
2
3
4

V-

5

10

VccSCK
RH

9

RW

8
7

RL
GND

6

FN6424.0

Features

• 256 resistor taps

• SPI serial interface with write/read capability

• Daisy Chain Configuration

• Shutdown mode

• Non-volatile EEPROM storage of wiper position

• 14 General Purpose non-volatile registers

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ +55°C

• Wiper resistance: 70Ω typical @ 1mA

• Standby current <2.5µA max

• Shutdown current <2.5µA max

• Dual power supply

- VCC = 2.25V to 5.5V

- V- = -2.25V to -5.5V

•10kΩ, 50kΩ or 100kΩ total resistance

• Extended industrial temperature range: -40 to +125°C

• 10 Lead MSOP

• Pb-free plus anneal product (RoHS compliant)

Ordering Information

PART

NUMBER

(NOTES 1, 2)

ISL22414TFU10Z 414TZ 100 -40 to +125 10 Ld MSOP M10.118
ISL22414UFU10Z 414UZ 50 -40 to +125 10 Ld MSOP M10.118
ISL22414WFU10Z 414WZ 10 -40 to +125 10 Ld MSOP M10.118

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

1

PART

MARKING

1-888-INTERSIL or 1-888-468-3774

RESISTANCE

OPTION

(kΩ)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

TEMP.

RANGE

(°C)

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2007. All Rights Reserved

PACKAGE

(Pb-Free)

PKG.

DWG. #

Block Diagram

ISL22414

VCC

SCK
SDO

SDI

CS

SPI

INTERFACE

POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC

NON-VOLATILE

REGISTERS

GND

WR
VOLATILE
REGISTER
AND
WIPER

CONTROL

CIRCUITRY

Pin Descriptions

MSOP PIN SYMBOL DESCRIPTION

1 SCK SPI interface clock input
2 SDO Data Output of the SPI serial interface
3 SDI Data Input of the SPI serial interface
4CS
5 V- Negative power supply pin
6 GND Device ground pin
7 RL “Low” terminal of DCP
8 RW “Wiper” terminal of DCP
9 RH “High” terminal of DCP

10 VCC Power supply pin

Chip Select active low input

V-

RH

RL
RW

2

FN6424.0

July 17, 2007

ISL22414

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-6V to 0.3V

Voltage at any DCP pin with Respect to GND. . . . . . . . . . V- to V

CC

+0.3

CC

IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +125°C

ESD

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

JA

Analog Specifications Over recommended operating conditions unless otherwise stated. Limits are established by characterization.

Thermal Resistance (Typical, Note 3) θ

(°C/W)

JA

10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C

Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V

CC

V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V

Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

SYMBOL PARAMETER TEST CONDITIONS

R

TOTAL

RH to RL resistance W option 10 kΩ

U option 50 kΩ

T option 100 kΩ
RH to RL resistance tolerance -20 +20 %
End-to-End Temperature

Coefficient

V

, V

RH

R

W

C

H/CL/CW

(Note 18)

I

LkgDCP

DCP terminal voltage VRH and VRL to GND V- V

RL

Wiper resistance RH - floating, VRL = V-, force Iw current to the

Potentiometer capacitance

Leakage on DCP pins

VOLTAGE DIVIDER MODE (V- @ RL; V

INL

(Note 9)

Integral non-linearity
Monotonic over all tap positions

@ RH; measured at RW, unloaded)

CC

W option ±150 ppm/°C

U, T option ±50 ppm/°C

wiper, I

= (VCC - VRL)/R

W

See Macro Model below. 10/10/25 pF

Voltage at pin from V- to V

W option -1.5 ±0.5 1.5 LSB

U, T option -1.0 ±0.2 1.0 LSB

DNL

(Note 8)

Differential non-linearity
Monotonic over all tap positions

W option -1.0 ±0.4 1.0 LSB

U, T option -0.5 ±0.15 0.5 LSB

ZSerror
(Note 6)

FSerror
(Note 7)

TC

(Notes 10, 18)

f

cutoff

(Note 18)

Zero-scale error W option 0 1 5 LSB

U, T option 0 0.5 2
Full-scale error W option -5 -1 0 LSB

U, T option -2 -1 0
Ratiometric temperature coefficient DCP register set to 80 hex ±4 ppm/°C

V

-3dB cut off frequency Wiper at midpoint (80hex) W option (10k) 1000 kHz

Wiper at midpoint (80hex) U option (50k) 250 kHz

Wiper at midpoint (80hex) T option (100k) 120 kHz

TOTAL

CC

MIN

(Note 19)

TYP

(Note 4)

MAX

(Note 19) UNIT

CC

70 250 Ω

-1 0.1 1 µA

V

(Note 5)

(Note 5)

(Note 5)

(Note 5)

(Note 5)

(Note 5)

3

FN6424.0

July 17, 2007

ISL22414

Analog Specifications Over recommended operating conditions unless otherwise stated. Limits are established by characterization.

(Continued)

MIN

SYMBOL PARAMETER TEST CONDITIONS

(Note 19)

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

RINL

Integral non-linearity W option -3 ±1.5 3 MI

(Note 14)

U, T option -1 ±0.3 1 MI

RDNL

Differential non-linearity W option -1.5 ±0.4 1.5 MI

(Note 13)

U, T option -0.5 ±0.15 0.5 MI

Roffset

Offset W option 0 1 5 MI

(Note 12)

U, T option 0 0.5 2 MI

TC

(Notes 15, 18)

Resistance temperature coefficient DCP register set between 32 hex and FF hex ±50 ppm/°C

R

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization.

MIN

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

VCC Supply Current
(volatile write/read)

V- Supply Current

V-1

(volatile write/read)

V

= 5.5V, V- = 5.5V, f

CC

= 5MHz; (for SPI

SCK

Active, Read and Volatile Write states only)
V

= 2.25V , V- = -2.25V , f

CC

Active, Read and Volatile Write states only)
V- = -5.5V, V

Active, Read and Volatile Write states only)
V- = -2.25V , V

CC

CC

= 5.5V, f

= 2.25V , f

= 5MHz; (for SPI

SCK

= 5MHz; (for SPI

SCK

= 5MHz; (for SPI

SCK

Active, Read and Volatile Write states only)

I

CC2

I

I

VCC Supply Current
(non-volatile write/read)

V- Supply Current

V-2

(non-volatile write/read)
V- Supply Current

(non-volatile write/read)
VCC Current (standby) V

SB

V

= 5.5V, V- = 5.5V, f

CC

Active, Read and Non-volatile Write states only)
V

= 2.25V , V- = -2.25V , f

CC

Active, Read and Non-volatile Write states only)
V- = -5.5V, V

CC

= 5.5V, f

= 5MHz; (for SPI

SCK

= 5MHz; (for SPI

SCK

= 5MHz; (for SPI

SCK

Active, Read and Non-volatile Write states only)
V- = -2.25V , V

Active, Read and Non-volatile Write states only)

= +5.5V , V- = -5.5V @ +85°C, SPI interface

CC

in standby state
V

= +5.5V, V- = -5.5V @ +125°C, SPI

CC

= 2.25V , f

CC

= 5MHz; (for SPI

SCK

interface in standby state
V

= +2.25V, V- = -2.25V @ +85°C, SPI

CC

interface in standby state
V

= +2.25V, V- = -2.25V @ +125°C, SPI

CC

interface in standby state

(Note 19)

-1 -0.18 mA

-0.4 -0.06 mA

-2 -1.2 mA

-0.7 -0.4 mA

TYP

(Note 4)

MAX

(Note 19) UNIT

(Note 11)

(Note 11)

(Note 11)

(Note 11)

(Note 11)

(Note 11)

TYP

(Note 4)

MAX

(Note 19) UNIT

0.36 1 mA

0.13 0.4 mA

12mA

0.3 0.7 mA

0.2 1.5 µA

12.5µA

0.1 1 µA

0.5 2 µA

4

FN6424.0

July 17, 2007

ISL22414

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization. (Continued)

MIN

SYMBOL PARAMETER TEST CONDITIONS

I

V-SB

V- Current (standby) V- = -5.5V , V

in standby state
V-

= -5.5V, V

interface in standby state
V-

= -2.25V, V

= +5.5V @ +85°C, SPI interface

CC

= +5.5V @ +125°C, SPI

CC

= +2.25V @ +85°C, SPI

CC

(Note 19)

-2.5 -0.7 µA

-4 -3 µA

-1.5 -0.3 µA

interface in standby state
V-

= -2.25V, V

interface in standby state

I

VCC Current (shutdown) V

SD

= +5.5V , V- = -5.5V @ +85°C, SPI interface

CC

in standby state
V

= +5.5V, V- = -5.5V @ +125°C, SPI

CC

= +2.25V @ +125°C, SPI

CC

-3 -1 µA

interface in standby state
V

= +2.25V, V- = -2.25V @ +85°C, SPI

CC

interface in standby state
V

= +2.25V, V- = -2.25V @ +125°C, SPI

CC

interface in standby state

I

V-SD

V- Current (shutdown) V- = -5.5V , V

= +5.5V @ +85°C, SPI interface

CC

-2.5 -0.7 µA

in standby state
V-

= -5.5V, V

= +5.5V @ +125°C, SPI

CC

-4 -3 µA

interface in standby state
V-

I

LkgDig

t

WRT

(Note 18)

t

ShdnRec

(Note 18)

interface in standby state
V-

interface in standby state

Leakage current, at pins SCK, SDI,
SDO and CS

Voltage at pin from GND to V

DCP wiper response time CS

DCP recall time from shutdown mode CS

connection

= -2.25V, V

= -2.25V, V

rising edge to wiper new position 1.5 µs

rising edge to wiper stored position and RH

= +2.25V @ +85°C, SPI

CC

= +2.25V @ +125°C, SPI

CC

CC

-1.5 -0.3 µA

-3 -1 µA

-0.5 0.5 µA

Vpor Power-on recall voltage Minimum Vcc at which memory recall occurs 1.9 2.1 V

VccRamp V

t

D

ramp rate 0.2 V/ms

CC

Power-up delay VCC above Vpor, to DCP Initial Value Register

recall completed, and SPI Interface in standby
state

EEPROM SPECIFICATION

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T ≤ +55ºC 50 Years

t

WC

(Note 16)

Non-volatile Write Cycle time 12 20 ms

SERIAL INTERFACE SPECIFICATIONS

V

SCK, SDI, and CS input buffer LOW

IL

-0.3 0.3*V

voltage

V

Hysteresis

SCK, SDI, and CS input buffer HIGH

IH

voltage
SCK, SDI, and CS input buffer

0.7*V

0.05*V

hysteresis

V

SDO output buffer LOW voltage IOL = 4mA for Open Drain output, pull-up

OL

voltage Vpu = V

CC

00.4V

TYP

(Note 4)

0.2 1.5 µA

12.5µA

0.1 1 µA

0.5 2 µA

1.5 µs

CC

CC

MAX

(Note 19) UNIT

5ms

CC

VCC+0.3 V

V

V

5

FN6424.0

July 17, 2007

ISL22414

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization. (Continued)

MIN

SYMBOL PARAMETER TEST CONDITIONS

R

pu

(Note 17)

Cpin

(Note 18)

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

SO

t

V

t

HO

t

RO

t

FO

t

CS

SDO pull-up resistor off-chip Maximum is determined by t

maximum bus load Cb = 30pF, f

SCK, SDI, SDO and CS

pin

capacitance
SPI frequency 5MHz
SPI clock cycle time 200 ns
SPI clock high time 100 ns
SPI clock low time 100 ns
Lead time 250 ns
Lag time 250 ns
SDI, SCK and CS input setup time 50 ns
SDI, SCK and CS input hold time 50 ns
SDI, SCK and CS input rise time 10 ns
SDI, SCK and CS input fall time 10 20 ns
SDO output Disable time 0 100 ns
SDO output setup time 50 ns
SDO output valid time 150 ns
SDO output hold time 0 ns
SDO output rise time Rpu = 2k, Cbus = 30pF 60 ns
SDO output fall time Rpu = 2k, Cbus = 30pF 60 ns
CS deselect time 2µs

and tFO with

RO

SCK

= 5MHz

(Note 19)

NOTES:

4. Typical values are for T

5. LSB: [V(RW)
incremental voltage when changing from one tap to an adjacent tap.

255

6. ZS error = V(RW)

7. FS error = [V(RW)

8. DNL = [V(RW)

9. INL = [V(RW)

10. for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

TC

V

11. MI =

|RW

– V(RW)

i

– i • LSB – V(RW)]/LSB for i = 1 to 255

i

Max V RW()

()Min V RW()

----------------------------------------------------------------------------------------------

()Min V RW()

Max V RW()

– RW

255

= +25°C and 3.3V supply voltage.

A

– V(RW)0]/255. V(RW)

/LSB.

0

– VCC]/LSB.

255

]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

()–

i

()+[]2⁄

i

|/255. MI is a minimum increment. RW

0

and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the

255

10

i

-----------------

×=

165° C

+

i

6

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

and RW0 are the measured resistances for the DCP register set to FF hex and

255

00 hex respectively.

12. Roffset = RW
Roffset = RW

13. RDNL = (RW

14. RINL = [RW

15. for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is

TC

R

16. t

17. R

is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.

WC

is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.

pu

/MI, when measuring between RW and RL.

0

/MI, when measuring between RW and RH.

255

– RW

i

– (MI • i) – RW0]/MI, for i = 1 to 255.

i

Max Ri()Min Ri()–[]

--------------------------------------------------------------- -

Max Ri()Min Ri()+[]2⁄

)/MI -1, for i = 1 to 255.

i-1

10

---------------- -

×=

165°C

+

6

the minimum value of the resistance over the temperature range.

18. Limits should be considered typical and are not production tested.

19. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.

TYP

(Note 4)

MAX

(Note 19) UNIT

2kΩ

10 pF

6

FN6424.0

July 17, 2007

DCP Macro Model

RH

ISL22414

R

TOTAL

C

H

C

W

C

L

10pF

RL

10pF

Timing Diagrams

Input Timing

CS

SCK

t

SU

SDI

SDO

Output Timing

CS

HIGH IMPEDANCE

25pF

RW

t

LEAD

t

H

MSB LSB

t

WL

t

CYC

...

t

WH

...

t

FI

t

CS

t

LAG

t

RI

SCK

t

SO

SDO

SDI

ADDR

MSB LSB

t

V

XDCP Timing (for All Load Instructions)

CS

SCK

SDI

V

SDO

W

HIGH IMPEDANCE

MSB LSB

t

HO

...

...

t

WRT

...

...

t

DIS

7

FN6424.0

July 17, 2007

Typical Performance Curves

ISL22414

80

70

60

50

40

30

WIPER RESISTANCE (Ω)

20

10

0

0 50 100 150 200 250

TAP POSITION (DECIMAL)

T = +125ºC

T = +25ºC

T = -40ºC

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

0.50

0.25

[ I(RW) = V

CC/RTOTAL

] FOR 10kΩ (W)

T = +25ºC

VCC = 2.25V

2.0

1.5

1.0
I

0.5

0

-0.5

-1.0

STANDBY CURRENT (µA)

-1.5

-2.0

-40 0 40 80 120
TEMPERATURE (°C)

FIGURE 2. STANDBY I

0.50

0.25

CC

VCC = 5.5V

CC

I

V-

AND IV- vs TEMPERATURE

T = +25ºC

0

DNL (LSB)

-0.25

VCC = 5.5V

-0.50
0 50 100 150 200 250

TAP POSITION (DECIMAL)

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

2.0
10k

1.6

1.2

0.8

ZS ERROR (LSB)

VCC = 2.25V VCC = 5.5V

0.4

50k

0

INL (LSB)

-0.25

VCC = 2.25V

-0.50
0 50 100 150 200 250

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

0

-1
VCC = 2.25V

-2

-3

FS ERROR (LSB)

-4

10k

50k

VCC = 5.5V

0

-40 0 40 80 120
TEMPERATURE (ºC)

FIGURE 5. ZS ERROR vs TEMPERATURE

8

-5

-40 0 40 80 120
TEMPERATURE (ºC)

FIGURE 6. FS ERROR vs TEMPERATURE

FN6424.0

July 17, 2007

Typical Performance Curves (Continued)

0.5

T = +25ºC

0.25

0

RDNL (MI)

-0.25

-0.50
0 50 100 150 200 250

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

VCC = 5.5V

VCC = 2.25V

TAP POSITION (DECIMAL)

10kΩ (W)

ISL22414

2.0
T = +25ºC

1.5

1.0

0.5

RINL (MI)

0

VCC = 5.5V

-0.5
0 50 100 150 200 250

VCC = 2.25V

TAP POSITION (DECIMAL)

FIGURE 8. INL vs TAP POSITION IN RHEOST AT MODE FOR

10kΩ (W)

1.60

1.20

0.80

CHANGE (%)

0.40

TOTAL

R

0.00

-0.40

-40 0 40 80 120
TEMPERATURE (ºC)

FIGURE 9. END TO END R

TEMPERATURE

500

400

300

10k

% CHANGE vs

TOTAL

5.5V

2.25V

50k

10k

200

160

10k

120

80

TCv (ppm/ºC)

40

0

16 66 116 166

TAP POSITION (DECIMAL)

216 266

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

INPUT

OUTPUT

50k

200

TCr (ppm/ºC)

100

0

16 66 116 166 216

TAP POSITION (D ECIMAL)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm

9

50k

WIPER AT MID POINT (POSITION 80h)
R

= 10kΩ

TOTAL

FIGURE 12. FREQUENCY RESPONSE (1MHz)

FN6424.0

July 17, 2007

Typical Performance Curves (Continued)

SCL

ISL22414

CS

WIPER

FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h

Pin Description

Potentiometer Pins

RH AND RL

The high (RH) and low (RL) terminals of the ISL22414 are
equivalent to the fixed terminals of a mechanical
potentiometer. RH and RL are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WR set to 255 decimal, the wiper will be
closest to RH, and with the WR set to 0, the wiper is closest
to RL.

RW

RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.

Bus Interface Pins

SERIAL CLOCK (SCK)

This is the serial clock input of the SPI serial interface.

SERIAL DATA OUTPUT (SDO)

The SDO is a serial data output pin. During a read cycle, the
data bits are shifted out on the falling edge of the serial clock
SCK and will be available to the master on the following
rising edge of SCK.

The output type is configured through ACR[1] bit for Push­Pull or Open Drain operation. Default setting for this pin is
Push-Pull. An external pull up resistor is required for Open
Drain output operation. Note, the external pull up voltage not
allowed beyond VCC.

SERIAL DATA INPUT (SDI)

The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI remote host device. The data bits are

WIPER UNLOADED,
MOVEMENT FROM 0h to FFh

FIGURE 14. LARGE SIGNAL SETTLING TIME

shifted in at the rising edge of the serial clock SCK, while the
CS

input is low.

CHIP SELECT (CS)

LOW enables the ISL22414, placing it in the active

CS
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS

is
HIGH, the ISL22414 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.

Principles of Operation

The ISL22414 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and the
SPI serial interface providing direct communication between
host and potentiometer and memory. The resistor array is
comprised of individual resistors connected in a series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.

When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the content of the IVR is recalled and
loaded into the WR to set the wiper to the initial position.

DCP Description

The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). When the WR of a DCP
contains all zeroes (WR[7:0]= 00h), its wiper terminal (RW)

10

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ISL22414

is closest to its “Low” terminal (RL). When the WR register of
a DCP contains all ones (WR[7:0]= FFh), its wiper terminal
(RW) is closest to its “High” terminal (RH). As the value of
the WR increases from all zeroes (0) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the closest to RH. At the same time, the
resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.

While the ISL22414 is being powered up, the WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reloaded with the value stored in a
non-volatile Initial Value Register (IVR).

The WR and IVR can be read or written to directly using the
SPI serial interface as described in the following sections.

Memory Description

The ISL22414 contains one non-volatile 8-bit Initial Value
Register (IVR), fourteen non-volatile 8-bit General Purpose
(GP) registers, volatile 8-bit Wiper Register (WR), and
volatile 8-bit Access Control Register (ACR). The memory
map of ISL22414 is in T able 1.

TABLE 1. MEMORY MAP

ADDRESS

(hex) NON-VOLATILE VOLATILE

10 N/A ACR

F Reserved
E General Purpose N/A
D General Purpose N/A
C General Purpose N/A
B General Purpose N/A
A General Purpose N/A

9 General Purpose N/A
8 General Purpose N/A
7 General Purpose N/A
6 General Purpose N/A
5 General Purpose N/A
4 General Purpose N/A
3 General Purpose N/A
2 General Purpose N/A
1 General Purpose N/A
0IVR WR

The non-volatile register (IVR) at address 0, contains initial
wiper position and volatile register (WR) contains current
wiper position.

The register at address 0Fh is a read-only reserved register.
Information read from this register should be ignored.

The non-volatile IVR and volatile WR registers are
accessible with the same address.

The Access Control Register (ACR) contains information
and control bits described below in Table 2.

The VOL bit (ACR[7]) determines whether the access to
wiper registers WR or initial value registers IVR.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

BIT # 76543210

BIT

VOL SHDN WIP 0 0 0 SDO 0

NAME

If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.

The SHDN

bit (ACR[6]) disables or enables Shutdown
mode. When this bit is 0, DCP is in Shutdown mode, i.e.
DCP is forced to end-to-end open circuit and RW is shorted
to RL as shown on Figure 15. Default value of SHDN

RH

RW

RL

FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE

Setting SHDN

bit to 1 is returned wiper to prior to Shutdown

bit is 1.

Mode position.
The WIP bit (ACR[5]) is a read-only bit. It indicates that non-

volatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write or read to
the WR or ACR while WIP bit is 1.

The SDO bit (ACR[1]) configures type of SDO output pin.
The default value of SDO bit is 0 for Push - Pull output. SDO
pin can be configured as Open Drain output for some
application. In this case, an external pull up resistor is
required. See “Applications Information” on page 13.

SPI Serial Interface

The ISL22414 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS
communication with the ISL22414. SCK and CS
controlled by the host or master. The ISL22414 operates
only as a slave device.

must be LOW during

lines are

11

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ISL22414

All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.

Protocol Conventions

The SPI protocol contains Instruction Byte followed by one
or more Data Bytes. A valid Instruction Byte contains
instruction as the three MSBs, with the following five register
address bits (see Table 3).

The next byte sent to the ISL22414 is the Data Byte.

TABLE 3. INSTRUCTION BYTE FORMAT

BIT # 76543210

I2 I1 I0 R4 R3 R2 R1 R0

Table 4 contains a valid instruction set for ISL22414.
There are only sixteen register addresses possible for this

DCP. If the [R4:R0] bits are zero, then the read or write is to
either the IVR or the WR register (depend s of VOL bit at
ACR). If the [R4:R0] are 10000, then the operation is on the
ACR.

Write Operation

A Write operation to the ISL22414 is a two or more bytes
operation. It requires first, the CS transition from HIGH to
LOW. Then host send a valid Instruction Byte, followed by
one or more Data Bytes to SDI pin. The host terminates the
write operation by pulling the CS

pin from LOW to HIGH.
Instruction is executed on rising edge of CS. For a write to
address 0, the MSB of the byte at address 10h (ACR[7])
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” and Figure 16. Note, the internal non-volatile
write cycle starts with the rising edge of CS

and requires up
to 20ms. During non-volatile write cycle the read operation to
ACR register is allowed to check WIP bit.

Read Operation

A Read operation to the ISL22414 is a four byte operation. It
requires first, the CS
host send a valid Instruction Byte, followed by “dummy” Data
Byte, NOP Instruction Byte and another “dummy” Data Byte
to SDI pin. The SPI host receives the Instruction Byte
(instruction code + register address) and requested Data
Byte from SDO pin on the rising edge of SCK during third
and fourth bytes respectively. The host terminates the read
operation by pulling the CS
Figure 17). Reading from the IVR will not change the WR, if
its contents are different.

transition from HIGH to LOW. Then

pin from LOW to HIGH (see

TABLE 4. INSTRUCTION SET

INSTRUCTION SET

000XXXXXNOP
001XXXXXACR READ
011XXXXXACR WRITE
1 0 0 R4 R3 R2 R1 R0 WR, IVR, GP or ACR READ
1 1 0 R4 R3 R2 R1 R0 WR, IVR, GP or ACR WRITE

where X means “do not care”

CS

SCK

SDI

SDO

1 3 4 5 7 8 9 10 11 12 13 14 15 1626

WR INSTRUCTION

ADDR

DATA BYTE

OPERATIONI2 I1 I0 R4 R3 R2 R1 R0

12

FIGURE 16. TWO BYTE WRITE SEQUENCE

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ISL22414

CS

SCK

SDI

SDO

1 8 16 24 32

RD ADDR

FIGURE 17. FOUR BYTE READ SEQUENCE

Applications Information

Communicating with ISL22414

Communication with ISL22414 proceeds using SPI interface
through the ACR (address 10000b), IVR (address 00000b),
WR (addresses 00000b) and General Purpose registers
(addresses from 00001b to 01110b).

The wiper of the potentiometer is controlled by the WR
register. Writes and reads can be made directly to these
register to control and monitor the wiper position without any
non-volatile memory changes. This is done by setting MSB
bit at address 10000b to 1 (ACR[7] = 1).

The non-volatile IVR stores the power up position of the
wiper. IVR is accessible when MSB bit at address 10000b is
set to 0 (ACR[7] = 0). Writing a new value to the IVR register
will set a new power up position for the wiper. Also, writing to
this register will load the same value into the corresponding
WR as the IVR. Reading from the IVR will not change the
WR, if its contents are different.

Daisy Chain Configuration

When application needs more then one ISL22414, it can
communicate with all of them without additional CS
daisy chaining the DCPs as shown on Figure 18. In Daisy
Chain configuration the SDO pin of previous chip is
connected to SDI pin of the following chip, and each CS
SCK pins are connected to the corresponding
microcontroller pins in parallel, like regular SPI interface
implementation. The Daisy Chain configuration can also be
used for simultaneous setting of multiple DCPs. Note, the
number of daisy chained DCPs is limited only by the driving
capabilities of SCK and CS

pins of microcontroller; for larger
number of SPI devices buffering of SCK and CS
required.

Daisy Chain Write Operation

The write operation starts by HIGH to LOW transition on CS
line, followed by N number of two bytes write instructions on
SDI line with reversed chain access sequence: the
instruction byte + data byte for the last DCP in chain is going
first, as shown on Figure 19, where N is a number of DCPs
in chain. The serial data is going through DCPs from DCP0

lines by

and

lines is

NOP

RD ADDR READ DATA

to DCP(N-1) as follow: DCP0 --> DCP1 --> DCP2 --> ... -->
DCP(N-1). The write instruction is executed on the rising
edge of CS

for all N DCPs simultaneously.

Daisy Chain Read Operation

The read operation consists two parts: first, send read
instructions (N two bytes operation) with valid address;
second, read the requested data while sending NOP
instructions (N two bytes operation) as shown on Figure 20,
and Figure 21.

The first part starts by HIGH to LOW transition on CS

line,
followed by N two bytes read instruction on SDI line with
reversed chain access sequence: the instruction byte +
dummy data byte for the last DCP in chain is going first,
followed by LOW to HIGH transition on CS

line. The read
instructions are executed during second part of read
sequence. It also starts by HIGH to LOW transition on CS
line, followed by N number of two bytes NOP instructions on
SDI line and LOW to HIGH transition of CS

. The data is read
on every even byte during second part of read sequence
while every odd byte contains instruction code + address
from which the data is being read.

Wiper Transition

When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the
sudden transition from a very low impedance “make” to a
much higher impedance “break within an extremely short
period of time (<50ns). Two such code transitions are EFh to
F0h, and 0Fh to 10h. Note, that all switchin g transients will
settle well within the settling time as stated in the datasheet.
A small capacitor can be added externally to reduce the
amplitude of these voltage transients, but that will also
reduce the useful bandwidth of the circuit, thus may not be a
good solution for some applications. It may be a good idea,
in that case, to use fast amplifiers in a signal chain for fast
recovery.

13

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µC

CS

SCK

MOSI
MISO

CS

SCK

SDI

ISL22414

N DCP IN A CHAIN

DCP0 DCP1 DCP2 DCP(N-1)

CS
SCK

SDI SDO

FIGURE 18. DAISY CHAIN CONFIGURATION

16 CLKLS 16 CLKS

WR D C

CS
SCK

SDI SDO

P2

WR D C

CS
SCK

SDI SDO

P1

16 CLKS

WR D C

CS
SCK

SDI SDO

P0

CS

SCK

SDI

SDO

SDO 0

SDO 1

SDO 2

WR D C P2

WR D C P1

WR D C

FIGURE 19. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP

1 2 10 11 12 13 14 15 1634567 8 9

DATA IN

INSTRUCTION

ADDR

DATA OUT

P2

14

FIGURE 20. TWO BYTE OPERATION

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CS

SCK

SDI

ISL22414

16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS

RD DCP2

RD DCP1

RD DCP0

NOP

NOP

NOP

SDO

DCP2 OUT DCP1 OUT

FIGURE 21. DAISY CHAIN READ SEQUENCE OF N = 3 DCP

DCP0 OUT

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ISL22414

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.007 0.011 0.18 0.27 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

o

θ

α

5

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 0 12/02

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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16

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