intersil ISL22349 DATA SHEET

®

Quad Digitally Controlled Potentiometers (XDCP™)

ISL22349

Data Sheet September 15, 2006

Low Noise, Low Power, I2C® Bus, 128 T aps,
Wiper Only

The ISL22349 integrates four digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.

The DCPs can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.

Pinout

ISL22349

(14 LD TSSOP)

TOP VIEW

FN6331.2

Features

• Four potentiometers in one package

• 128 resistor taps

•I2C serial interface

- Three address pins, up to eight devices/bus

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical

• Shutdown mode

• Shutdown current 6.5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T <

• 14 Ld TSSOP

• Pb-free plus anneal product (RoHS compliant)

+55°C

RW0

RW3

A2

SCL
SDA
GND
RW2
RW1

1
2
3
4
5
6
7

14

SHDN

13

V

12

CC

NC

11

A1

10

A0

9

NC

8

Ordering Information

PART NUMBER PART MARKING

ISL22349UFV14Z
(Notes 1, 2)

ISL22349WFV14Z
(Notes 1, 2)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

22349 UFVZ 50 -40 to +125 14 Ld TSSOP

22349 WFVZ 10 -40 to +125 14 Ld TSSOP

RESISTANCE OPTION

(kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M14.173

(Pb-Free)

M14.173

(Pb-Free)

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006. All Rights Reserved

ISL22349

Block Diagram

V

CC

SCL

SDA

A0
A1
A2

SHDN

I2C

INTERFACE

POWER-UP

INTERFACE,

CONTROL

AND STA TUS

LOGIC

NON-

VOLATILE

REGISTERS

GND

Pin Descriptions

TSSOP PIN SYMBOL DESCRIPTION

1 RW3 “Wiper” terminal of DCP3
2 A2 Device address input for the I
3 SCL Open drain I

2

C interface clock input
4 SDA Open drain serial data I/O for the I
5 GND Device ground pin and the RL connection for each DCP
6 RW2 “Wiper” terminal of DCP2
7 RW1 “Wiper” terminal of DCP1
8NC
9 A0 Device address input for the I

10 A1 Device address input for the I
11 NC
12 V

CC

13 SHDN

Power supply pin and the RH connection for each DCP
Shutdown active low input

14 RW0 “Wiper” terminal of DCP0

2

C interface

2

C interface

2

C interface

2

C interface

WR3

WR2

WR1

WR0

V

CC

RW3

V

CC

RW2

V

CC

RW1

V

CC

RW0

2

FN6331.2

September 15, 2006

ISL22349

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

CC

+0.3

CC

ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV

(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3.

JA

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -0.8V for all pins.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

End-to-End Resistance W option 10 kΩ

U option 50 kΩ
End-to-End Resistance Tolerance W and U option -20 +20 %
End-to-End Temperature Coefficient W option ±50 ppm/°C

U option ±80 ppm/°C

R

Wiper Resistance V

W

(Note 13)

C

(Note 13)

Wiper Capacitance 25 pF

W

VOLTAGE DIVIDER MODE (measured at R

INL

Integral Non-linearity Monotonic over all tap positions -1 1 LSB

i, unloaded; i = 0, 1, 2, or 3)

W

= 3.3V @ +25°C,

CC

wiper current = V

(Note 10)

DNL

Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

(Note 9)
ZSerror

(Note 7)

FSerror
(Note 8)

V

MATCH

(Note 11)

TC

Zero-scale Error W option 0 1 5 LSB

U option 0 0.5 2
Full-scale Error W option -5 -1 0 LSB

U option -2 -1 0
DCP to DCP Matching Any two DCPs at the same tap position -2 2 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

V

(Note 12)

Thermal Resistance (Typical, Note 3)

14 Ld TSSOP package . . . . . . . . . . . . . . . . . . . . . . +100

Maximum Junction Temperature (Plastic Package)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50°C to +150°C

Recommended Operating Conditions

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

V

Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

TYP

(NOTE 5) MAX UNIT

70 Ω

CC/RTOTAL

θ

(°C/W)

JA

(Note 13)

(Note 13)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

3

FN6331.2

September 15, 2006

ISL22349

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

VCC Supply Current (volatile
write/read)

Supply Current (volatile

V

CC

write/read, non-volatile read)
VCC Supply Current (non-volatile

write/read)
VCC Supply Current (non-volatile

write/read)

I

SB

I

SD

I

LkgDig

t

WRT

VCC Current (standby) V

VCC Current (shutdown) V

Leakage Current, at Pins A0, A1, A2,
SHDN

, SDA, and SCL

DCP Wiper Response Time SCL falling edge of last bit of DCP data byte

(Note 13)
t

ShdnRec

(Note 13)

DCP Recall Time from Shutdown
Mode

Vpor Power-on Recall Voltage Minimum V

VccRamp V

t

D

Ramp Rate 0.2 V/ms

CC

Power-up Delay Vcc above Vpor, to DCP Initial Value

EEPROM SPECIFICATION

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T <

t

WC

(Note 14)

Non-volatile Write Cycle Time 12 20 ms

V

= +3.6V, 10k DCP, f

CC

2

I

C active, read and write states)

V

= +3.6V, 50k DCP, f

CC

2

I

C active, read and write states)

V

= +5.5V, 10k DCP, f

CC

2

I

C active, read and write states)

V

= +5.5V, 50k DCP, f

CC

2

I

C active, read and write states)

= +5.5V, 10k DCP, I2C interface in

CC

standby state
V

= +3.6V, 10k DCP, I2C interface in

CC

= 400kHz; (for

SCL

= 400kHz; (for

SCL

= 400kHz; (for

SCL

= 400kHz; (for

SCL

standby state
V

= +5.5V, 50k DCP, I2C interface in

CC

standby state

= +3.6V, 50k DCP, I2C interface in

V

CC

standby state

= +5.5V @ +85°C, I2C interface in

CC

standby state

= +5.5V @ +125°C, I2C interface in

V

CC

standby state
V

= +3.6V @ +85°C, I2C interface in

CC

standby state
V

= +3.6V @ +125°C, I2C interface in

CC

standby state
Voltage at pin from GND to V

CC

to wiper new position
From rising edge of SHDN

signal to wiper

stored position and RH connection
SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

at which memory recall occurs 2.0 2.6 V

CC

Register recall completed, and I

2

C Interface

in standby state

+55°C 50 Years

-1 1 µA

TYP

(NOTE 5) MAX UNIT

2.5 mA

0.65 mA

4.0 mA

3.0 mA

2.4 mA

525 µA

1.6 mA

350 µA

5µA

6.5 µA

4µA

5.5 µA

1.5 µs

1.5 µs

1.5 µs

3ms

4

FN6331.2

September 15, 2006