intersil ISL22349 DATA SHEET

®

Quad Digitally Controlled Potentiometers (XDCP™)

ISL22349

Data Sheet September 15, 2006

Low Noise, Low Power, I2C® Bus, 128 T aps,
Wiper Only

The ISL22349 integrates four digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.

The DCPs can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.

Pinout

ISL22349

(14 LD TSSOP)

TOP VIEW

FN6331.2

Features

• Four potentiometers in one package

• 128 resistor taps

•I2C serial interface

- Three address pins, up to eight devices/bus

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical

• Shutdown mode

• Shutdown current 6.5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T <

• 14 Ld TSSOP

• Pb-free plus anneal product (RoHS compliant)

+55°C

RW0

RW3

A2

SCL
SDA
GND
RW2
RW1

1
2
3
4
5
6
7

14

SHDN

13

V

12

CC

NC

11

A1

10

A0

9

NC

8

Ordering Information

PART NUMBER PART MARKING

ISL22349UFV14Z
(Notes 1, 2)

ISL22349WFV14Z
(Notes 1, 2)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

22349 UFVZ 50 -40 to +125 14 Ld TSSOP

22349 WFVZ 10 -40 to +125 14 Ld TSSOP

RESISTANCE OPTION

(kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M14.173

(Pb-Free)

M14.173

(Pb-Free)

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006. All Rights Reserved

ISL22349

Block Diagram

V

CC

SCL

SDA

A0
A1
A2

SHDN

I2C

INTERFACE

POWER-UP

INTERFACE,

CONTROL

AND STA TUS

LOGIC

NON-

VOLATILE

REGISTERS

GND

Pin Descriptions

TSSOP PIN SYMBOL DESCRIPTION

1 RW3 “Wiper” terminal of DCP3
2 A2 Device address input for the I
3 SCL Open drain I

2

C interface clock input
4 SDA Open drain serial data I/O for the I
5 GND Device ground pin and the RL connection for each DCP
6 RW2 “Wiper” terminal of DCP2
7 RW1 “Wiper” terminal of DCP1
8NC
9 A0 Device address input for the I

10 A1 Device address input for the I
11 NC
12 V

CC

13 SHDN

Power supply pin and the RH connection for each DCP
Shutdown active low input

14 RW0 “Wiper” terminal of DCP0

2

C interface

2

C interface

2

C interface

2

C interface

WR3

WR2

WR1

WR0

V

CC

RW3

V

CC

RW2

V

CC

RW1

V

CC

RW0

2

FN6331.2

September 15, 2006

ISL22349

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

CC

+0.3

CC

ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV

(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3.

JA

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -0.8V for all pins.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

End-to-End Resistance W option 10 kΩ

U option 50 kΩ
End-to-End Resistance Tolerance W and U option -20 +20 %
End-to-End Temperature Coefficient W option ±50 ppm/°C

U option ±80 ppm/°C

R

Wiper Resistance V

W

(Note 13)

C

(Note 13)

Wiper Capacitance 25 pF

W

VOLTAGE DIVIDER MODE (measured at R

INL

Integral Non-linearity Monotonic over all tap positions -1 1 LSB

i, unloaded; i = 0, 1, 2, or 3)

W

= 3.3V @ +25°C,

CC

wiper current = V

(Note 10)

DNL

Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

(Note 9)
ZSerror

(Note 7)

FSerror
(Note 8)

V

MATCH

(Note 11)

TC

Zero-scale Error W option 0 1 5 LSB

U option 0 0.5 2
Full-scale Error W option -5 -1 0 LSB

U option -2 -1 0
DCP to DCP Matching Any two DCPs at the same tap position -2 2 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

V

(Note 12)

Thermal Resistance (Typical, Note 3)

14 Ld TSSOP package . . . . . . . . . . . . . . . . . . . . . . +100

Maximum Junction Temperature (Plastic Package)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50°C to +150°C

Recommended Operating Conditions

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

V

Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

TYP

(NOTE 5) MAX UNIT

70 Ω

CC/RTOTAL

θ

(°C/W)

JA

(Note 13)

(Note 13)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

3

FN6331.2

September 15, 2006

ISL22349

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

VCC Supply Current (volatile
write/read)

Supply Current (volatile

V

CC

write/read, non-volatile read)
VCC Supply Current (non-volatile

write/read)
VCC Supply Current (non-volatile

write/read)

I

SB

I

SD

I

LkgDig

t

WRT

VCC Current (standby) V

VCC Current (shutdown) V

Leakage Current, at Pins A0, A1, A2,
SHDN

, SDA, and SCL

DCP Wiper Response Time SCL falling edge of last bit of DCP data byte

(Note 13)
t

ShdnRec

(Note 13)

DCP Recall Time from Shutdown
Mode

Vpor Power-on Recall Voltage Minimum V

VccRamp V

t

D

Ramp Rate 0.2 V/ms

CC

Power-up Delay Vcc above Vpor, to DCP Initial Value

EEPROM SPECIFICATION

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T <

t

WC

(Note 14)

Non-volatile Write Cycle Time 12 20 ms

V

= +3.6V, 10k DCP, f

CC

2

I

C active, read and write states)

V

= +3.6V, 50k DCP, f

CC

2

I

C active, read and write states)

V

= +5.5V, 10k DCP, f

CC

2

I

C active, read and write states)

V

= +5.5V, 50k DCP, f

CC

2

I

C active, read and write states)

= +5.5V, 10k DCP, I2C interface in

CC

standby state
V

= +3.6V, 10k DCP, I2C interface in

CC

= 400kHz; (for

SCL

= 400kHz; (for

SCL

= 400kHz; (for

SCL

= 400kHz; (for

SCL

standby state
V

= +5.5V, 50k DCP, I2C interface in

CC

standby state

= +3.6V, 50k DCP, I2C interface in

V

CC

standby state

= +5.5V @ +85°C, I2C interface in

CC

standby state

= +5.5V @ +125°C, I2C interface in

V

CC

standby state
V

= +3.6V @ +85°C, I2C interface in

CC

standby state
V

= +3.6V @ +125°C, I2C interface in

CC

standby state
Voltage at pin from GND to V

CC

to wiper new position
From rising edge of SHDN

signal to wiper

stored position and RH connection
SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

at which memory recall occurs 2.0 2.6 V

CC

Register recall completed, and I

2

C Interface

in standby state

+55°C 50 Years

-1 1 µA

TYP

(NOTE 5) MAX UNIT

2.5 mA

0.65 mA

4.0 mA

3.0 mA

2.4 mA

525 µA

1.6 mA

350 µA

5µA

6.5 µA

4µA

5.5 µA

1.5 µs

1.5 µs

1.5 µs

3ms

4

FN6331.2

September 15, 2006

ISL22349

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Cont inued)

SYMBOL PARAMETER TEST CONDITIONS MIN

SERIAL INTERFACE SPECS

V

V

A2, A1, A0, SHDN, SDA, and SCL

IL

Input Buffer LOW Voltage
A2, A1, A0, SHDN, SDA, and SCL

IH

-0.3 0.3*V

0.7*V

Input Buffer HIGH Voltage

Hysteresis

(Note 13)

t

SU:STA

t

HD:STA

t

SU:DAT

SDA and SCL Input Buffer Hysteresis 0.05*

V

OL

Cpin

SDA Output Buffer LOW Voltage,
Sinking 4mA

A2, A1, A0, SHDN

, SDA, and SCL Pin

Capacitance

f

SCL

t

sp

SCL Frequency 400 kHz
Pulse Width Suppression Time at SDA

and SCL Inputs

t

AA

t

BUF

SCL Falling Edge to SDA Output Data
Valid

Time the Bus Must be Free Before the

Start of a New Transmission

t

LOW

t

HIGH

Clock LOW Time Measured at the 30% of VCC crossing 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing 600 ns
START Condition Setup Time SCL rising edge to SDA falling edge; both

STAR T Condition Hold Time From SDA falling edge crossing 30% of VCC

Input Data Setup Time From SDA exiting the 30% to 70% of VCC

Any pulse narrower than the max spec is
suppressed

SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of V

CC

window

SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of V
during the following START condition

crossing 70% of V

CC

to SCL falling edge crossing 70% of V

CC

CC

V

CC

00.4V

1300 ns

600 ns

600 ns

100 ns
window, to SCL rising edge crossing 30% of
V

CC

t

HD:DAT

t

SU:STO

t

HD:STO

t

DH

t

R

t

F

Input Data Hold Time From SCL rising edge crossing 70% of VCC

to SDA entering the 30% to 70% of V
window

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC,

to SDA rising edge crossing 30% of V

STOP Condition Hold Time for Read,
or Volatile Only Write

Output Data Hold Time From SCL falling edge crossing 30% of VCC,

From SDA rising edge to SCL falling edge;
both crossing 70% of V

CC

until SDA enters the 30% to 70% of V
window

SDA and SCL Rise Time From 30% to 70% of V

SDA and SCL Fall Time From 70% to 30% of V

CC

CC

CC

CC

CC

0ns

600 ns

1300 ns

0ns

20 +

0.1 * Cb
20 +

0.1 * Cb

Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF

Rpu

SDA and SCL Bus Pull-up Resistor
Off-chip

Maximum is determined by tR and t

F

For Cb = 400pF, max is about 2~2.5kΩ

1kΩ

For Cb = 40pF, max is about 15~20kΩ

t

SU:A

A2, A1 and A0 Setup Time Before START condition 600 ns

TYP

(NOTE 5) MAX UNIT

CC

VCC+0.3 V

10 pF

50 ns

900 ns

250 ns

250 ns

CC

V

V

5

FN6331.2

September 15, 2006

ISL22349

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

t

HD:A

A2, A1 and A0 Hold Time After STOP condition 600 ns

NOTES:

5. Typical values are for T

6. LSB: [V(R

– V(RW)0]/127. V(RW)

W)127

= +25°C and 3.3V supply voltage.

A

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively . LSB is the

127

incremental voltage when changing from one tap to an adjacent tap.

7. ZS error = V(RW)

8. FS error = [V(RW)

9. DNL = [V(RW)

10. INL = [V(RW)

11. V

12. for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

= [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.

MATCH

----------------------------------------------------------------------------------------------

TC

V

Max V RW()

/LSB.

0

– VCC]/LSB.

127

– V(RW)

i

– i • LSB – V(RW)0]/LSB for i = 1 to 127.

i

Max V RW()

()Min V RW()

()Min V RW()

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

()–

i

i

()+[]2⁄

i

×=

i

6

10

---------------- -

165°C

minimum value of the resistance over the temperature range.

13. This parameter is not 100% tested.
is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile

14. t

WC

write cycle.

SDA vs SCL Timing

TYP

(NOTE 5) MAX UNIT

SCL

t

SU:STA

(INPUT TIMING)

(OUTPUT TIMING)

SDA

SDA

A0, A1, and A2 Pin Timing

SCL

SDA

A0, A1, OR A2

t

HD:STA

t

F

START

t

SU:A

t

SU:DAT

t

HIGH

CLK 1

t

LOW

t

HD:DAT

t

t

DH

STOP

sp

t

SU:STO

t

BUF

t

R

t

AA

t

HD:A

6

FN6331.2

September 15, 2006

Typical Performance Curves

VCC

100

Vcc = 3.3V, T = 125ºC

90
80
70
60
50
40
30

Vcc = 3.3V, T = 20ºC

WIPER RESISITANCE (Ω)

20
10

0

0 20406080100120

TAP PO SIT ION ( D E C IMAL)

Vcc = 3.3V, T = -40º C

ISL22349

1.4

1.2

1

VCC

0.8

0.6

Isb (µA)

0.4

0.2

0

2.73.23.74.24.75.2

T = 1 25

T = 25

ºC

ºC

Vcc, V

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[ I(RW) = V

CC/RTOTAL

] FOR 10kΩ (W)

0.2
Vcc = 2.7V

T = 25ºC

0.1

0

DNL (LSB)

-0. 1

Vcc = 5.5V

-0. 2
0 20 40 60 80 100 120

TAP PO S I T I ON (D E C I MAL )

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

1.30
10k

1.10

0.90

0.70

0.50

0.30

ZSerror (LSB)

Vcc = 5.5V

Vcc = 2.7V

0.10

-0.10

50k

-0.30

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (ºC)

FIGURE 2. STANDBY I

CC

vs V

CC

0.2
T = 25ºC

0.1

Vcc = 2.7V

0

INL (LSB)

-0.1
Vcc = 5.5V

-0.2

0 20406080100120

TAP PO SI TION ( D E C IMAL)

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

0.00

-0. 30
Vcc = 2.7V Vcc = 5.5V

50k

-0. 60

-0. 90

FSerror (LSB)

10k

-1. 20

-1. 50

-40-200 20406080100120

TEMPERATURE (ºC)

FIGURE 5. ZSerror vs TEMPERATURE

7

FIGURE 6. FSerror vs TEMPERATURE

September 15, 2006

FN6331.2

Typical Performance Curves (Continued)

ISL22349

1.00
Vcc = 2.7V

0.50

CHANGE (%)

0.00

TOTAL

-0.50

END TO END R

-1.00

-40 -20 0 20 40 60 80 100 120

FIGURE 7. END TO END R

Vcc = 5.5V

TEMPERATURE (º C)

TOTAL

TEMPERATURE

50k

10k

% CHANGE vs

105

90

10k

75
60
45

TCv (ppm/°C)

30

50k

15

0

16 36 56 76 96

TAP PO SI T IO N (DE C IMAL)

FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm

FIGURE 9. MIDSCALE GLITCH, CODE 3Fh TO 40h

Pin Descriptions

Potentiometers Pins

RWi (i = 0, 1, 2 or 3)

RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.

SHDN

The SHDN pin forces the resistor to end-to-end open circuit
condition and shorts all RWi to GND. When SHDN
returned to logic high, the previous latch settings put RWi at
the same resistance setting prior to shutdown. This pin is
logically OR’d with SHDN bit in ACR register. I
still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation.

8

is

2

C interface is

FIGURE 10. LARGE SIGNAL SETTLING TIME

RW

FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE

FN6331.2

September 15, 2006

ISL22349

Bus Interface Pins

Serial Data Input/Output (SDA)

2

The SDA is a bidirectional serial data input/output pin for I

C
interface. It receives device address, operation code, wiper
address and data from an I

2

C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.

SDA requires an external pull-up resistor, since it is an open
drain input/output.

Serial Clock (SCL)

This is the serial clock input of the I

2

C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.

Device Address (A2 - A0)

The address inputs are used to set the least significant 3 bits
of the 7-bit I

2

C interface slave address. A match in the slave
address serial data stream must match with the Address
input pins in order to initiate communication with the
ISL22349. A maximum of 8 ISL22349 devices may occupy

2

the I

C serial bus.

Principles of Operation

The ISL22349 is an integrated circuit incorporating four
DCPs with their associated registers, non-volatile memory
and an I
between a host and the potentiometers and memory. The
resistor arrays are comprised of individual resistors
connected in series. At either end of the array and between
each resistor is an electronic switch that transfers the
potential at that point to the wiper.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.

2

C serial interface providing direct communication

ones (127 decimal), the wiper moves monotonically from the
position closest to GND to the closest to V

CC

.

While the ISL22349 is being powered up, all four WRs are
reset to 40h (64 decimal), which locates RW roughly at the
center between GND and V

. After the power supply

CC

voltage becomes large enough for reliable non-volatile
memory reading, all WRs will be reload with the value stored
in corresponding non-volatile Initial Value Registers (IVRs).

The WRs can be read or written to directly using the I

2

C

serial interface as described in the following sections. The

2

I

C interface Address Byte has to be set to 00h, 01h, 02h or
03h to access the WR of DCP0, DCP1, DCP2 or DCP3
respectively.

Memory Description

The ISL22349 contains seven non-volatile and five volatile
8-bit registers. The memory map of ISL22349 is on Table 1.
The four non-volatile registers (IVRi) at address 0, 1, 2 and
3, contain initial wiper value and volatile registers (WRi)
contain current wiper position. In addition, three non-volatile
General Purpose registers from address 4 to address 6 are
available.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

8— ACR
7 Reserved
6

5
4

3
2
1
0

General Purpose
General Purpose
General Purpose

IVR3
IVR2
IVR1
IVR0

Not Available
Not Available
Not Available

WR3
WR2
WR1
WR0

When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi are recalled and
loaded into the corresponding WRi to set the wipers to the
initial value.

DCP Description

Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer and internally connected to Vcc and GND.
The RW pin of each DCP is connected to intermediate
nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by volatile Wiper Register (WR).
Each DCP has its own WR. When the WR of a DCP contains
all zeroes (WR[6:0] = 00h), its wiper terminal (RW) is closest
to GND. When the WR register of a DCP contains all ones
(WR[6:0] = 7Fh), its wiper terminal (RW) is closest to V
As the value of the WR increases from all zeroes (0) to all

9

CC

.

The non-volatile IVRi and volatile WRi registers are
accessible with the same address.

The Access Control Register (ACR) contains information
and control bits described below in Table 2. The VOL bit at
access control register (ACR[7]) determines whether the
access is to wiper registers WRi or initial value registers
IVRi.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

VOL SHDN WIP

00000

If VOL bit is 0, the non-volatile IVRi registers are accessible.
If VOL bit is 1, only the volatile WRi are accessible. Note,
value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.

The SHDN bit (ACR[6]) disables or enables Shutdown
mode. This bit is logically OR’d with SHDN

pin. When this bit
is 0, DCPs are in Shutdown mode. Default value of SHDN bit
is 1.

FN6331.2

September 15, 2006

The WIP bit (ACR[5]) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WRi or ACR while WIP bit is 1.

I2C Serial Interface

The ISL22349 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22349
operates as a slave device in all applications.

All communication over the I

2

C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 12). On power-up of the ISL22349 the SDA pin is in
the input mode.

2

All I

C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22349 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met. A
START condition is ignored during the power-up of the
device.

ISL22349

All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 12). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).

The ISL22349 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22349 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.

A valid Identification Byte contains 1010b as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1, and A0. The LSB is the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation (See Table 3).

2

C interface operations must be terminated by a STOP

TABLE 3. IDENTIFICATION BYTE FORMAT

Logic values at pins A2, A1, and A0 respectively

1010A2A1A0R/W

(MSB) (LSB)

SCL

SDA

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

START DATA DATA STOP

FIGURE 12. VALID DATA CHANGES, START AND STOP CONDITIONS

HIGH IMPEDANCE

START ACK

FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER

STABLE CHANGE

DATA

STABLE

81 9

HIGH IMPEDANCE

10

FN6331.2

September 15, 2006

SIGNALS FROM

THE MASTER

S
T
A

IDENTIFICATION

R
T

BYTE

ISL22349

WRITE

ADDRESS

BYTE

DATA

BYTE

S
T
O
P

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

10100

FIGURE 14. BYTE WRITE SEQUENCE

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

S
T

A

IDENTIFICATION

R

BYTE WITH

T

R/W

10100

= 0

A
C
K

ADDRESS

BYTE

0000A0A1A2 A0A1A2

A
C
K

FIGURE 15. READ SEQUENCE

Write Operation

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22349 responds with an ACK. At this time, the device
enters its standby state (See Figure 14). Device can receive
more than one byte of data by auto incrementing the
address after each received byte. Note after reaching the
address 08h, the internal pointer “rolls over” to address 00h.

The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write. Thus, non-volatile registers must be
written individually.

0000A0A1A2 0

A
C
K

S
T
A

IDENTIFICATION

R

BYTE WITH

T

R/W

11100

= 1

A
C
K

A
C
K

FIRST READ

DATA BYTE

A
C
K

A
C
K

A
C
K

LAST READ
DATA BYTE

S
T

A

O

C

P

K

Read Operation

A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 15). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W
Address Byte, a second START, and a second Identification
byte with the R/W

bit set to “1”. After each of the three bytes,
the ISL22349 responds with an ACK. Then the ISL22349
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
ACK

and a STOP condition) following the last bit of the last

Data Byte (See Figure 15).

bit set to “0”, an

11

The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 08h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.

In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.

FN6331.2

September 15, 2006

ISL22349

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

-A-

0.05(0.002)

D

SEATING PLANE

e

b

0.10(0.004) C AM BS

E1

-B-

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

L

c

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.041 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 2 4/06

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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12

FN6331.2

September 15, 2006