intersil ISL22346WMVEP DATA SHEET
®
www.BDTIC.com/Intersil
Quad Digitally Controlled Potentiometers (XDCP™)
ISL22346WMVEP
Data Sheet December 17, 2007
Low Noise, Low Power I2C® Bus, 128 Taps
The ISL22346WMVEP integrates four digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2
I
C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper . At power-up, the device reca lls the content s of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as a three-terminal potentiometers
or as a two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments and
signal processing.
Device Information
The specifications for an Enhanced Product (EP) device are
defined in a Vendor Item Drawing (VID), which is controlled
by the Defense Supply Center in Columbus (DSCC).
“Hot-links” to the applicable VID and other supporting
application information are provided on our website.
Pinout
ISL22346WMVEP
(20 LD TSSOP)
TOP VIEW
RW0
RH3
RL3
RW3
A2
SCL
SDA
GND
RW2
RL2
RH2
1
2
3
4
5
6
7
8
9
10
20
RL0
19
RH0
18
SHDN
17
VCC
16
A1
15
A0
14
RH1
13
RL1
12
RW1
11
FN6624.0
Features
• Specifications per DSCC VID V62/08605-01XE
• Full Mil-Temp Electrical Performance from -55°C to +125°C
• Controlled Baseline with One Wafer Fabrication Site and
One Assembly/Test Site
• Full Homogeneous Lot Processing in Wafer Fab
• No Combination of Wafer Fabrication Lots in Assembly
• Full Traceability Through Assembly and Test by
Date/Trace Code Assignment
• Enhanced Process Change Notification
• Enhanced Obsolescence Management
• Eliminates Need for Up-Screening a COTS Component
• Four Potentiometers in One Package
• 128 Resistor Taps
2
C Serial Interface
•I
- Three Address Pins, Up To Eight Devices/Bus
• Non-volatile Storage of Wiper Position
• Wiper Resistance: 70Ω Typical @ 3.3V
• Shutdown Mode
• Shutdown Current 5µA Max
• Power Supply: 2.7V to 5.5V
•10kΩ Total Resistance
• High Reliability
- Endurance: 1,000,000 Data Changes Per Bit Per
Register
- Register Data Retention:
- 10 years @ T ≤ +125°C
- 15 years @ T ≤ +90°C
- 50 years @ T ≤ +55°C
• 20 Ld TSSOP
Ordering Information
VENDOR PART NUMBER
(Notes 1, 2) VENDOR ITEM DRAWING PART MARKING
ISL22346WMVEP V62/08605-01XE 22346 WMVEP 10 -55 to +125 20 Ld TSSOP M20.173
NOTES:
1. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Devices must be procured to the VENDOR PART NUMBER.
1
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
RESISTANCE OPTION
(kΩ)
| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
TEMP.
RANGE (°C) PACKAGE
Copyright Intersil Americas Inc. 2007. All Rights Reserved
PKG.
DWG. #
ISL22346WMVEP
www.BDTIC.com/Intersil
Block Diagram
V
CC
SCL
SDA
A2
SHDN
A0
A1
I2C
INTERFACE
POWER-UP
INTERFACE,
CONTROL
AND STA TUS
LOGIC
NON-
VOLATILE
REGISTERS
GND
Pin Descriptions
TSSOP PIN SYMBOL DESCRIPTION
1 RH3 “High” terminal of DCP3
2 RL3 “Low” terminal of DCP3
3 RW3 “Wiper” terminal of DCP3
2
4 A2 Device address input for the I
5 SCL Open drain I2C interface clock input
6 SDA Open drain Serial data I/O for the I
7 GND Device ground pin
8 RW2 “Wiper” terminal of DCP2
9 RL2 “Low” terminal of DCP2
10 RH2 “High” terminal of DCP2
11 RW1 “Wiper” terminal of DCP1
12 RL1 “Low” terminal of DCP1
13 RH1 “High” terminal of DCP1
14 A0 Device address input for the I
15 A1 Device address input for the I
16 VCC Power supply pin
17 SHDN
Shutdown active low input
18 RH0 “High” terminal of DCP0
19 RL0 “Low” terminal of DCP0
20 RW0 “Wiper” terminal of DCP0
C interface
2
C interface
2
C interface
2
C interface
WR3
WR2
WR1
WR0
RH3
RW3
RL3
RH2
RW2
RL2
RH1
RW1
RL1
RH0
RW0
RL0
2
FN6624.0
December 17, 2007
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