intersil ISL22319 DATA SHEET

®

www.BDTIC.com/Intersil

Single Digitally Controlled Potentiometer (XDCP™)

ISL22319

Data Sheet July 3, 2006

Low Noise, Low Power, I2C® Bus,
128 T a ps, Wiper Only

The ISL22319 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the content of the
DCP’s IVR to the WR.

The DCP can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.

FN6310.0

Features

• 128 resistor taps

2

•I

C serial interface

- Two address pins, up to four devices/bus

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ 3.3V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

°C

- Register data retention: 50 years @

• 8 Ld MSOP

• Pb-free plus anneal product (RoHS compliant)

T55≤

Pinout

ISL22319

(8 LD MSOP)

TOP VIEW

VCCSCL

8

RW

7

6

SHDN

5

GND

SDA

A1

A0

1

2

3

4

Ordering Information

PART NUMBER PART MARKING

ISL22319UFU8Z
(Notes 1, 2)

ISL22319WFU8Z
(Notes 1, 2)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

319UZ 50 -40 to +125 8 Ld MSOP

319WZ 10 -40 to +125 8 Ld MSOP

RESISTANCE OPTION

(kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M8.118

(Pb-Free)

M8.118

(Pb-Free)

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006. All Rights Reserved

Block Diagram

www.BDTIC.com/Intersil

ISL22319

V

CC

SCL

SDA

A0
A1

SHDN

I2C

INTERFACE

POWER-UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC

NON-VOLATILE
REGISTERS

GND

Pin Descriptions

MSOP PIN SYMBOL DESCRIPTION

2

1 SCL Open drain I
2 SDA Open drain serial data I/O for the I2C interface
3 A1 Device address input for the I
4 A0 Device address input for the I
5 GND Device ground pin
6SHDN
7 RW “Wiper” terminal of DCP
8V

CC

Shutdown active low input

Power supply pin

C interface clock input

2

C interface

2

C interface

WR

RW

2

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP Pin with

respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @+125°C

ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV

(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied .

NOTES:

3. θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

(Note 14)

C

(Note 14)

I

LkgRW

VOLTAGE DIVIDER MODE ( measured at R

INL

(Note 10)

DNL

(Note 9)
ZSerror

(Note 7)

FSerror
(Note 8)

TC

(Note 1 1, 14)

End-to-End Resistance W option 10 kΩ

End-to-End Resistance Tolerance -20 +20 %
End-to-End Temperature Coefficient W option ±50 ppm/°C

Wiper Resistance V

W

Wiper Capacitance 25 pF

W

Leakage on RW Pin Voltage at pin from GND to V

, unloaded)

W

Integral Non-linearity -1 1 LSB

Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

Zero-scale Error W option 0 1 5 LSB

Full-scale Error W option -5 -1 0 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

V

+0.3

CC

CC

U option 50 kΩ

U option ±80 ppm/°C

= 3.3V @ 25°C,

CC

wiper current = V

U option 0 0.5 2

U option -2 -1 0

Thermal Resistance (Typical, Note 3) θ

10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Maximum Junction Temperature (Plastic Package). . . . . . . . . .150°C

Recommended Operating Conditions

Ambient Temperature (Extended Industrial) . . . . . . .-40°C to 125°C

Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

TYP

(NOTE 5) MAX UNIT

70 Ω

CC/RTOTAL

CC

24µA

(°C/W)

JA

(Note 14)

(Note 14)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

3

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

I

SB

I

SD

I

LkgDig

t

DCP

(Note 14)
t

ShdnRec

(Note 14)

Vpor Power-on Recall Voltage Minimum V

Ramp VCC Ramp Rate 0.2 V/ms

V

CC

t

EEPROM SPECIFICATION

t

WC

(Note 15)

SERIAL INTERFACE SPECS

V

V

VCC Supply Current (volatile
write/read)

V

Supply Current (volatile

CC

write/read, non-volatile read)
VCC Supply Current ( non-volatile

write/read)

Supply Current (non-volatile

V

CC

write/read)
VCC Current (standby) V

VCC Current (shutdown) V

Leakage Current, at Pins A0, A1,
SHDN

, SDA, and SCL

DCP Wiper Response Time SCL falling edge of last bit of DCP data byte

DCP Recall Time from Shutdown
Mode

Power-up Delay VCC above Vpor, to DCP Initial Value

D

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature °C 50 Years
Non-volatile Write Cycle Time 12 20 ms

A1, A0, SHDN, SDA, and SCL Input

IL

Buffer LOW Voltage
A1, A0, SHDN, SDA, and SCL Input

IH

Buffer HIGH Voltage

10k DCP, f
read and write states)

50k DCP, f
read and write states)

10k DCP, f
read and write states)

50k DCP, f
read and write states)

= +5.5V , 10k DCP, I2C interface in

CC

standby state

= +3.6V, 10k DCP, I2C interface in

V

CC

standby state

= +5.5V, 50k DCP, I2C interface in

V

CC

standby state
V

= +3.6V, 50k DCP, I2C interface in

CC

standby state

= +5.5V @ +85°C, I2C interface in

CC

standby state
V

= +5.5V @ +125°C, I2C interface in

CC

standby state

= +3.6V @ +85°C, I2C interface in

V

CC

standby state

= +3.6V @ +125°C, I2C interface in

V

CC

standby state
Voltage at pin from GND to V

to wiper new position
From rising edge of SHDN

stored position and RH connection
SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

Register recall completed, and I
in standby state

= 400kHz; (for I2C active,

SCL

= 400kHz; (for I2C active,

SCL

= 400kHz; (for I2C active,

SCL

= 400kHz; (for I2C active,

SCL

CC

signal to wiper

at which memory recall occurs 2.0 2.6 V

CC

2

C Interface

T55≤

-0.3 0.3*V

0.7*V

(NOTE 5) MAX UNIT

0.5 mA

3.2 mA

2.7 mA

850 µA

550 µA

160 µA

100 µA

-1 1 µA

1.5 µs

1.5 µs

1.5 µs

CC

VCC+0.3 V

1mA

3µA

5µA

2µA

4µA

3ms

CC

V

4

FN6310.0

July 3, 2006