intersil ISL22319 DATA SHEET

®

www.BDTIC.com/Intersil

Single Digitally Controlled Potentiometer (XDCP™)

ISL22319

Data Sheet July 3, 2006

Low Noise, Low Power, I2C® Bus,
128 T a ps, Wiper Only

The ISL22319 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the content of the
DCP’s IVR to the WR.

The DCP can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.

FN6310.0

Features

• 128 resistor taps

2

•I

C serial interface

- Two address pins, up to four devices/bus

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ 3.3V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

°C

- Register data retention: 50 years @

• 8 Ld MSOP

• Pb-free plus anneal product (RoHS compliant)

T55≤

Pinout

ISL22319

(8 LD MSOP)

TOP VIEW

VCCSCL

8

RW

7

6

SHDN

5

GND

SDA

A1

A0

1

2

3

4

Ordering Information

PART NUMBER PART MARKING

ISL22319UFU8Z
(Notes 1, 2)

ISL22319WFU8Z
(Notes 1, 2)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

319UZ 50 -40 to +125 8 Ld MSOP

319WZ 10 -40 to +125 8 Ld MSOP

RESISTANCE OPTION

(kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

M8.118

(Pb-Free)

M8.118

(Pb-Free)

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006. All Rights Reserved

Block Diagram

www.BDTIC.com/Intersil

ISL22319

V

CC

SCL

SDA

A0
A1

SHDN

I2C

INTERFACE

POWER-UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC

NON-VOLATILE
REGISTERS

GND

Pin Descriptions

MSOP PIN SYMBOL DESCRIPTION

2

1 SCL Open drain I
2 SDA Open drain serial data I/O for the I2C interface
3 A1 Device address input for the I
4 A0 Device address input for the I
5 GND Device ground pin
6SHDN
7 RW “Wiper” terminal of DCP
8V

CC

Shutdown active low input

Power supply pin

C interface clock input

2

C interface

2

C interface

WR

RW

2

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP Pin with

respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @+125°C

ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV

(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied .

NOTES:

3. θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

(Note 14)

C

(Note 14)

I

LkgRW

VOLTAGE DIVIDER MODE ( measured at R

INL

(Note 10)

DNL

(Note 9)
ZSerror

(Note 7)

FSerror
(Note 8)

TC

(Note 1 1, 14)

End-to-End Resistance W option 10 kΩ

End-to-End Resistance Tolerance -20 +20 %
End-to-End Temperature Coefficient W option ±50 ppm/°C

Wiper Resistance V

W

Wiper Capacitance 25 pF

W

Leakage on RW Pin Voltage at pin from GND to V

, unloaded)

W

Integral Non-linearity -1 1 LSB

Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

Zero-scale Error W option 0 1 5 LSB

Full-scale Error W option -5 -1 0 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

V

+0.3

CC

CC

U option 50 kΩ

U option ±80 ppm/°C

= 3.3V @ 25°C,

CC

wiper current = V

U option 0 0.5 2

U option -2 -1 0

Thermal Resistance (Typical, Note 3) θ

10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Maximum Junction Temperature (Plastic Package). . . . . . . . . .150°C

Recommended Operating Conditions

Ambient Temperature (Extended Industrial) . . . . . . .-40°C to 125°C

Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

TYP

(NOTE 5) MAX UNIT

70 Ω

CC/RTOTAL

CC

24µA

(°C/W)

JA

(Note 14)

(Note 14)

(Note 6)

(Note 6)

(Note 6)

(Note 6)

3

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

I

SB

I

SD

I

LkgDig

t

DCP

(Note 14)
t

ShdnRec

(Note 14)

Vpor Power-on Recall Voltage Minimum V

Ramp VCC Ramp Rate 0.2 V/ms

V

CC

t

EEPROM SPECIFICATION

t

WC

(Note 15)

SERIAL INTERFACE SPECS

V

V

VCC Supply Current (volatile
write/read)

V

Supply Current (volatile

CC

write/read, non-volatile read)
VCC Supply Current ( non-volatile

write/read)

Supply Current (non-volatile

V

CC

write/read)
VCC Current (standby) V

VCC Current (shutdown) V

Leakage Current, at Pins A0, A1,
SHDN

, SDA, and SCL

DCP Wiper Response Time SCL falling edge of last bit of DCP data byte

DCP Recall Time from Shutdown
Mode

Power-up Delay VCC above Vpor, to DCP Initial Value

D

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature °C 50 Years
Non-volatile Write Cycle Time 12 20 ms

A1, A0, SHDN, SDA, and SCL Input

IL

Buffer LOW Voltage
A1, A0, SHDN, SDA, and SCL Input

IH

Buffer HIGH Voltage

10k DCP, f
read and write states)

50k DCP, f
read and write states)

10k DCP, f
read and write states)

50k DCP, f
read and write states)

= +5.5V , 10k DCP, I2C interface in

CC

standby state

= +3.6V, 10k DCP, I2C interface in

V

CC

standby state

= +5.5V, 50k DCP, I2C interface in

V

CC

standby state
V

= +3.6V, 50k DCP, I2C interface in

CC

standby state

= +5.5V @ +85°C, I2C interface in

CC

standby state
V

= +5.5V @ +125°C, I2C interface in

CC

standby state

= +3.6V @ +85°C, I2C interface in

V

CC

standby state

= +3.6V @ +125°C, I2C interface in

V

CC

standby state
Voltage at pin from GND to V

to wiper new position
From rising edge of SHDN

stored position and RH connection
SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

Register recall completed, and I
in standby state

= 400kHz; (for I2C active,

SCL

= 400kHz; (for I2C active,

SCL

= 400kHz; (for I2C active,

SCL

= 400kHz; (for I2C active,

SCL

CC

signal to wiper

at which memory recall occurs 2.0 2.6 V

CC

2

C Interface

T55≤

-0.3 0.3*V

0.7*V

(NOTE 5) MAX UNIT

0.5 mA

3.2 mA

2.7 mA

850 µA

550 µA

160 µA

100 µA

-1 1 µA

1.5 µs

1.5 µs

1.5 µs

CC

VCC+0.3 V

1mA

3µA

5µA

2µA

4µA

3ms

CC

V

4

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

V

OL

Cpin

SDA and SCL Input Buffer Hysteresis 0.05*

SDA Output Buffer LOW Voltage,
Sinking 4mA

A1, A0, SHDN, SDA, and SCL Pin

V

CC

00.4V

Hysteresis

Capacitance

f

SCL

t

t

t

BUF

sp

AA

SCL Frequency 400 kHz
Pulse Width Suppression Time at SDA

and SCL Inputs
SCL Falling Edge to SDA Output Data

Valid

Time the Bus Must be Free before the

Start of a New Transmission

Any pulse narrower than the max spec is
suppressed

SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of V

window

CC

SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of V

CC

1300 ns

during the following START condition

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

t

DH

Clock LOW Time Measured at the 30% of VCC crossing 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing 600 ns
START Condition Setup Time SCL rising edge to SDA falling edge; both

crossing 70% of V

CC

STAR T Condition Hold Time From SDA falling edge crossing 30% of VCC

to SCL falling edge crossing 70% of V

CC

Input Data Setup Time From SDA exiting the 30% to 70% of VCC

600 ns

600 ns

100 ns
window, to SCL rising edge crossing 30% of
V

CC

Input Data Hold Time From SCL rising edge crossing 70% of VCC

to SDA entering the 30% to 70% of V
window

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC,

to SDA rising edge crossing 30% of V

STOP Condition Hold Time for Read,
or Volatile Only Write

Output Data Hold Time From SCL falling edge crossing 30% of VCC,

From SDA rising edge to SCL falling edge;
both crossing 70% of V

CC

until SDA enters the 30% to 70% of V

CC

CC

CC

0ns

600 ns

1300 ns

0ns

window

t

t

SDA and SCL Rise Time From 30% to 70% of V

R

SDA and SCL Fall Time From 70% to 30% of V

F

CC

CC

20 +

0.1 * Cb
20 +

0.1 * Cb

Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF

Rpu

SDA and SCL Bus Pull-up Resistor
Off-chip

Maximum is determined by tR and t
For Cb = 400pF, max is about 2~2.5kΩ

F

1kΩ

For Cb = 40pF, max is about 15~20kΩ

t

SU:A

t

HD:A

A1 and A0 Setup Time Before START condition 600 ns
A1 and A0 Hold Time After STOP condition 600 ns

TYP

(NOTE 5) MAX UNIT

10 pF

50 ns

900 ns

250 ns

250 ns

V

NOTES:

5. Typical values are for T

6. LSB: [V(R

– V(RW)0]/127. V(RW)

W)127

= 25°C and 3.3V supply voltage.

A

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively . LSB is the

127

incremental voltage when changing from one tap to an adjacent tap.

7. ZS error = V(RW)

/LSB.

0

5

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

8. FS error = [V(RW)

9. DNL = [V(RW)

10. INL = [V(RW)

11. for i = 16 to 127 decimal, T = -40°C to 125°C. Max( ) is the maximum value of the wiper

TC

12. MI =

Max V RW()

----------------------------------------------------------------------------------------------

V

Max V RW()

|RW

– RW

127

– VCC]/LSB.

127

– V(RW)

i

– (i • LSB) – V(RW)0]/LSB for i = 1 to 127

i

()Min V RW()

()Min V RW()

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

()–

i

()+[]2⁄

i

|/127. MI is a minimum increment. RW

0

i

i

---------------- -

×=

165°C

10

6

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

and RW0 are the measured resistances for the DCP register set to 7F hex and

127

00 hex respectively.

13. Roffset = RW
Roffset = RW

/MI, when measuring between RW and RL.

0

/MI, when measuring between RW and RH.

127

14. This parameter is not 100% tested.

is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-

15. t

WC

volatile write cycle.

SDA vs SCL Timing

t

sp

t

DH

t

BUF

t

HD:STO

t

SU:STO

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

t

SU:STA

t

HD:STA

t

F

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

R

t

AA

A0 and A1 Pin Timing

A0, A1

SCL

SDA

START

t

SU:A

CLK 1

t

HD:A

STOP

6

FN6310.0

July 3, 2006

Typical Performance Curves

www.BDTIC.com/Intersil

VCC

100

Vcc = 3.3V, T = 125ºC

90
80
70
60
50
40
30

Vcc = 3.3V, T = 20ºC

WIPER RESISITANCE (Ω)

20
10

0

0 20406080100120

TAP PO SITI ON ( D E C I MAL )

Vcc = 3.3V, T = -40º C

ISL22319

1.4

1.2

1

VCC

0.8

0.6

Isb (µA)

0.4

0.2

0

2.73.23.74.24.75.2

T = 1 25

T = 25

ºC

ºC

Vcc, V

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[ I(RW) = V

CC/RTOTAL

] FOR 10kΩ (W)

0.2
Vcc = 2.7V

T = 25ºC

0.1

0

DNL (LSB)

-0. 1

Vcc = 5.5V

-0. 2
0 20 40 60 80 100 120

TAP PO S ITI O N ( DE C I MAL )

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

1.30

MODE FOR 10kΩ (W)

10k

1.10

0.90

0.70

0.50

0.30

ZSerror (LSB)

Vcc = 5.5V

Vcc = 2.7V

0.10

-0.10

50k

-0.30

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (ºC)

FIGURE 2. STANDBY I

CC

vs V

CC

0.2
T = 25ºC

0.1

Vcc = 2.7V

0

INL (LSB)

-0.1
Vcc = 5.5V

-0.2

0 20406080100120

TAP PO SI TIO N ( D ECI MAL )

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

0.00

-0. 30
Vcc = 2.7V Vcc = 5.5V

50k

-0. 60

-0. 90

FSerror (LSB)

10k

-1. 20

-1. 50

-40-200 20406080100120

TEMPERATURE (ºC)

FIGURE 5. ZSerror vs TEMPERATURE

FIGURE 6. FSerror vs TEMPERATURE

7

FN6310.0

July 3, 2006

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL22319

1.00
Vcc = 2.7V

0.50

CHANGE (%)

0.00

TOTAL

-0.50

END TO END R

-1.00

-40 -20 0 20 40 60 80 100 120

FIGURE 7. END TO END R

Vcc = 5.5V

TEMPERATURE (º C)

TOTAL

TEMPERATURE

50k

10k

% CHANGE vs

105

90

10k

75
60
45

TCv (ppm/°C)

30

50k

15

0

16 36 56 76 96

TAP PO SI T IO N ( D ECIMAL)

FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm

FIGURE 9. MIDSCALE GLITCH, CODE 3Fh TO 40h

Pin Description

Potentiometers Pins

RW

RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.

SHDN

The active low SHDN pin forces the resistor to end-to-end
open circuit condition and shorts RWi to GND. When SHDN
is returned to logic high, the previous latch settings put RW
at the same resistance setting prior to shutdown. This pin is
logically OR’d with SHDN bit in ACR register. I
still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation.

8

2

C interface is

FIGURE 10. LARGE SIGNAL SETTLING TIME

RW

FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE

Bus Interface Pins

Serial Data Input/Output (SDA)

The SDA is a bidirectional serial data input/output pin for I2C
interface. It receives device address, operation code, wiper
address and data from an I

2

C external master device at the

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.

SDA requires an external pull-up resistor, since it is an open
drain input/output.

Serial Clock (SCL)

This is the serial clock input of the I2C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.

Device Address (A1, A0)

The address inputs are used to set the least significant 2 bits
of the 7-bit I
address serial data stream must match with the Address
input pins in order to initiate communication with the
ISL22319. A maximum of 4 ISL22319 devices may occupy
the I

2

C interface slave address. A match in the slave

2

C serial bus.

Principles of Operation

The ISL22319 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and an I
serial interface providing direct communication between a
host and the potentiometer and memory. The resistor array
is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.

When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.

DCP Description

The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer and internally connected to V
The RW pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the
DCP is controlled by an 7-bit volatile Wiper Register (WR).
When the WR of a DCP contains all zeroes (WR[6:0]= 00h),
its wiper terminal (RW) is closest to GND. When the WR
register of a DCP contains all ones (WR[6:0]= 7Fh), its wiper
terminal (RW) is closest to V
increases from all zeroes (0) to all ones (127 decimal), the
wiper moves monotonically from the position closest to GND
to the closest to V

While the ISL22319 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between V
becomes large enough for reliable non-volatile memory

CC

.

CC

and GND. After the power supply voltage

. As the value of the WR

CC

and GND.

CC

2

C

reading, the WR will be reload with the value stored in a non­volatile Initial Value Register (IVR).

The WR and IVR can be read or written to directly using the

2

I

C serial interface as described in the following sections.

Memory Description

The ISL22319 contains one non-volatile 8-bit register, known as
the Initial Value Register (IVR), and two volatile 8-bit registers,
Wiper Register (WR) and Access Control Register (ACR). The
memory map of ISL22319 is on Table 1. The non-volatile
register (IVR) at address 0, contains initial wiper position and
volatile register (WR) contains current wiper position.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

2— ACR
1Reserved
0IVR WR

The non-volatile IVR and volatile WR registers are
accessible with the same address.

The Access Control Register (ACR) contains information
and control bits described below in Table 2.

The VOL bit (ACR[7]) determines whether the access is to
wiper registers WR or initial value registers IVR.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

VOL SHDN WIP

If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.

The SHDN bit (ACR[6]) disables or enables Shutdown mode.
This bit is logically OR ‘d with SHDN
DCP is in Shutdown mode. Default value of SHDN bit is 1.

The WIP bit (ACR[5]) is read only bit. It indicates that
nonHvolatile write operation is in progress. It is impossible to
write to the WR or ACR while WIP bit is 1.

00000

pin. When this bit is 0,

I2C Serial Interface

The ISL22319 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22319
operates as a slave device in all applications.

All communication over the I
sending the MSB of each byte of data first.

2

C interface is conducted by

9

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

Protocol Conventions

Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 12). On power-up of the ISL22319 the SDA pin is in
the input mode.

2

All I

C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22319 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 12). A START condition is ignored during the
powerHup of the device.

2

All I

C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 12). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).

The ISL22319 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22319 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 01010 as the five MSBs, and
the following two bits matching the logic values present at pins
A1 and A0. The LSB is the Read/Write

bit. Its value is “1” for a

Read operation, and “0” for a Write operation (See T able 3).

TABLE 3. IDENTIFICATION BYTE FORMAT

Logic values at pins A1 and A0 respectively

01010A1A0R/W

(MSB) (LSB)

SCL

SDA

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

START DATA DATA STOP

FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS

HIGH IMPEDANCE

START ACK

FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER

STABLE CHANGE

DATA

STABLE

81 9

HIGH IMPEDANCE

10

FN6310.0

July 3, 2006

SIGNALS FROM

www.BDTIC.com/Intersil

THE MASTER

S
T
A

IDENTIFICATION

R
T

BYTE

ISL22319

WRITE

ADDRESS

BYTE

DATA
BYTE

S
T
O
P

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

00011

0

FIGURE 14. BYTE WRITE SEQUENCE

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

S
T

A

IDENTIFICATION

R

BYTE WITH

T

R/W

00011

ADDRESS

=0

A0A1 A0A1

0

A
C
K

BYTE

0000

A
C
K

FIGURE 15. READ SEQUENCE

Write Operation

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22319 responds with an ACK. At this time, the device
enters its standby state (See Figure 14).

A0A1

0000

A
C
K

S
T
A

IDENTIFICATION

R

BYTE WITH

T

R/W

0

A
C
K

=1

1

0010

1

A
C

FIRST READ

K

DATA BYTE

A
C
K

A
C
K

A
C
K

LAST READ
DATA BYTE

S
T

A

O

C

P

K

The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write.

Read Operation

A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 15). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W

bit set to “1”. After each of
the three bytes, the ISL22319 responds with an ACK. Then
the ISL22319 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a ACK

and STOP condition) following the

last bit of the last Data Byte (See Figure 15).
In order to read back the non-volatile IVR, it is recommended

that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.

bit

11

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

V

CC

ISL22319

Rpu

V

V

CC

CC

Rpu

SHDN

SCL
SDA

A0
A1

FIGURE 16. TYPICAL APPLICATION DIAGRAM FOR IMPLEMENTING ADJUSTABLE VOLTAGE REFERANCE

Applications Information

The typical application diagram is shown on Figure 16. For
proper operation adding 0.1µF decoupling ceramic capacitor
to V

is recommended. The capacitor value may vary

CC

based on expected noise frequency of the design.

0.1µF

RW

R1

R2

V

CC

0.1µF

V

OUT

12

FN6310.0

July 3, 2006

ISL22319

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

TOP VIEW

-H-

SIDE VIEW

12

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

05

α

o

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 2 01/03

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

13

FN6310.0

July 3, 2006