intersil ISL22316 DATA SHEET

®

www.BDTIC.com/Intersil

Single Digitally Controlled Potentiometer (XDCP™)

ISL22316

Data Sheet February 18, 2008

Low Noise, Low Power I2C® Bus, 128 Taps

The ISL22316 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up, the device recalls the contents of the
DCP’s IVR to the WR.

The DCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

FN6186.1

Features

• 128 resistor taps

2

•I

C serial interface

- Two address pins, up to four devices/bus

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ +55

• 10 Ld MSOP or 10 Ld TDFN package

• Pb-free (RoHS compliant)

CC

= 3.3V

°C

Pinouts

SCL

SDA

A1

A0

SHDN

ISL22316

(10 LD MSOP)

TOP VIEW

1

2

3

4

5

10

VCC

RH

9

RW

8

7

RL

GND

6

SCL

SDA

SHDN

(10 LD TDFN)

TOP VIEW

1

2

3

A1

A0

4

5

ISL22316

O

10

VCC

RH

9

8

RW

RL

7

GND

6

Ordering Information

PART NUMBER

(Note) PART MARKING

ISL22316UFU10Z* 316UZ 50 -40 to +125 10 Ld MSOP M10.118
ISL22316WFU10Z* 316WZ 10 -40 to +125 10 Ld MSOP M10.118
ISL22316UFRT10Z* 316U 50 -40 to +125 10 Ld 3x3 TDFN L10.3x3B
ISL22316WFRT10Z* 316W 10 -40 to +125 10 Ld 3x3 TDFN L10.3x3B
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

RESISTANCE OPTION

(kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved

Block Diagram

www.BDTIC.com/Intersil

ISL22316

V

CC

SCL

SDA

A0
A1

SHDN

I2C

INTERFACE

POWER-UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

NON-VOLATILE

REGISTERS

GND

Pin Descriptions

MSOP PIN

NUMBER

1 1 SCL Open drain I
2 2 SDA Open drain Serial data I/O for the I2C interface
3 3 A1 Device address input for the I
4 4 A0 Device address input for the I
5 5 SHDN Shutdown active low input
6 6 GND Device ground pin
7 7 RL “Low” terminal of DCP
8 8 RW “Wiper” terminal of DCP
9 9 RH “High” terminal of DCP

10 10 VCC Power supply pin

TDFN PIN

NUMBER PIN NAME DESCRIPTION

2

C interface clock input

WR

2

C interface

2

C interface

RH

RW

RL

2

FN6186.1

February 18, 2008

ISL22316

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP Pin with

Respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Latchup (Note 1) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

ESD Ratings

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV

Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.

2. For θ

3. θ

Analog Specifications Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

R

VRH, V

C

H/CL/CW

(Note 17)

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ R

(Note 9)

(Note 8)

ZSerror

(Note 6)

FSerror

(Note 7)

(Notes 10, 17)

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

is for the location in the center of the exposed metal pad on the package underside.

JC

TOTAL

R

W

INL

DNL

TC

RH to RL Resistance W option 10 kΩ

to RL Resistance Tolerance -20 +20 %

R

H

End-to-End Temperature Coefficient W option ±50 ppm/°C

Wiper Resistance VCC = 3.3V , wiper current = VCC/R

RLVRH

V

and VRL Terminal Voltages VRH and VRL to GND 0 V

Potentiometer Capacitance 10/10/25 pF

Leakage on DCP Pins Voltage at pin from GND to VCC 0.1 1 µA

; VCC @ RH; measured at RW, unloaded)

L

Integral Non-linearity Monotonic over all tap positions, W and U

Differential Non-linearity Monotonic over all tap positions, W and U

Zero-scale Error W option 0 1 5 LSB

Full-scale Error W option -5 -1 0 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex for W and U

+0.3

CC

CC

U option 50 kΩ

U option ±80 ppm/°C

option

option

U option 0 0.5 2

U option -2 -1 0

option

Thermal Resistance (Typical) θ

10 Lead MSOP (Note 2). . . . . . . . . . . . 120 N/A

10 Lead TDFN (Notes 2, 3) . . . . . . . . . 150 48.3

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

MIN

(Note 18)

TOTAL

-1 1 LSB

-0.5 0.5 LSB

TYP

(Note 4)

(°C/W) θJC (°C/W)

JA

MAX

(Note 18) UNIT

(Note 17)

(Note 17)

70 200 Ω

CC

±4 ppm/°C

V

(Note 5)

(Note 5)

(Note 5)

(Note 5)

3

FN6186.1

February 18, 2008

ISL22316

www.BDTIC.com/Intersil

Analog Specifications Over recommended operating conditions, unless otherwise stated. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

RINL

(Note 14)

RDNL

(Note 13)

Roffset

(Note 12)

Integral Non-linearity DCP register set between 10 hex and 7F

Differential Non-linearity W option -1 1 MI

Offset W option 0 1 5 MI

hex; monotonic over all tap positions;
W and U option

U option -0.5 0.5 MI

U option 0 0.5 2 MI

MIN

(Note 18)

-1 1 MI

Operating Specifications Over the recommended operating conditions, unless otherwise specified.

MIN

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

I

I

LkgDig

t

DCP

(Note 17)

t

ShdnRec

(Note 17)

Vpor Power-on Recall Voltage Minimum V

V

CC

VCC Supply Current (Volatile Write/Read) f

VCC Supply Current (Non-volatile Write/Read) f

VCC Current (Standby) V

SB

VCC Current (Shutdown) V

SD

Leakage Current, at Pins A0, A1, SHDN,
SDA and SCL

DCP Wiper Response Time SCL falling edge of last bit of DCP data byte

DCP Recall Time from Shutdown Mode From rising edge of SHDN

Ramp VCC Ramp Rate 0.2 V/ms

Power-up Delay VCC above Vpor, to DCP Initial Value

t

D

= 400kHz; SDA = Open; (for I2C,

SCL

active, read and write states)

= 400kHz; SDA = Open; (for I2C,

SCL

active, read and write states)

= +5.5V @ +85°C, I2C interface in

CC

standby state

= +5.5V @ +125°C, I2C interface in

V

CC

standby state

= +3.6V @ +85°C, I2C interface in

V

CC

standby state

= +3.6V @ +125°C, I2C interface in

V

CC

standby state

= +5.5V @ +85°C, I2C interface in

CC

standby state

= +5.5V @ +125°C, I2C interface in

V

CC

standby state

= +3.6V @ +85°C, I2C interface in

V

CC

standby state

= +3.6V @ +125°C, I2C interface in

V

CC

standby state
Voltage at pin from GND to V

SDA is inactive

to wiper new position

stored position and RH connection
SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

at which memory recall occurs 2.0 2.6 V

CC

Register recall completed and I
in standby state

CC,

signal to wiper

2

C Interface

(Note 18)

-1 1 µA

TYP

(Note 4)

TYP

(Note 4)

1.5 µs

1.5 µs

1.5 µs

MAX

(Note 18) UNIT

MAX

(Note 18) UNIT

0.5 mA

3mA

5µA

7µA

3µA

5µA

3µA

5µA

2µA

4µA

3ms

(Note 11)

(Note 11)

(Note 11)

(Note 11)

(Note 11)

4

FN6186.1

February 18, 2008

ISL22316

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

EEPROM SPECIFICATION

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T ≤

t

(Note 16)

SERIAL INTERFACE SPECIFICATIONS

V

V

Hysteresis

V

Cpin

(Note 17)

f

SCL

t

t

BUF

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

t

Non-volatile Write Cycle Time 12 20 ms

WC

A1, A0, SHDN, SDA, and SCL Input Buffer

IL

LOW Voltage
A1, A0, SHDN, SDA, and SCL Input Buffer

IH

HIGH Voltage
SDA and SCL Input Buffer Hysteresis 0.05*V
SDA Output Buffer LOW Voltage, Sinking

OL

4mA
A1, A0, SHDN

Capacitance
SCL Frequency 400 kHz

t

Pulse Width Suppression Time at SDA and

sp

SCL Inputs
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until

AA

Time the Bus Must be Free Before the Start

of a New Transmission

Clock LOW Time Measured at the 30% of VCC crossing 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing 600 ns
START Condition Setup Time SCL rising edge to SDA falling edge; both

STAR T Condition Hold Time From SDA falling edge crossing 30% of VCC

Input Data Setup Time From SDA exiting the 30% to 70% of VCC

Input Data Hold Time From SCL rising edge crossing 70% of VCC

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC,

STOP Condition Hold Time for Read, or
Volatile Only Write

Output Data Hold Time From SCL falling edge crossing 30% of

DH

SDA and SCL Rise Time From 30% to 70% of V

t

R

SDA and SCL Fall Time From 70% to 30% of V

t

F

Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF

, SDA, and SCL Pin

Any pulse narrower than the max spec is
suppressed

SDA exits the 30% to 70% of V
SDA crossing 70% of VCC during a STOP

condition, to SDA crossing 70% of V
during the following START condition

crossing 70% of V

to SCL falling edge crossing 70% of V

window, to SCL rising edge crossing 30% of
V

CC

to SDA entering the 30% to 70% of V
window

to SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge;

both crossing 70% of V

V

, until SDA enters the 30% to 70% of

CC

window

V

CC

+55°C 50 Years

window

CC

CC

CC

CC

CC

CC

CC

CC

CC

MIN

(Note 18)

-0.3 0.3*V

0.7*V

00.4V

1300 ns

600 ns

600 ns

100 ns

0ns

600 ns

1300 ns

0ns

20 +

0.1*Cb
20 +

0.1*Cb

CC

CC

TYP

(Note 4)

10 pF

MAX

(Note 18) UNIT

V

+ 0.3 V

CC

50 ns

900 ns

250 ns

250 ns

CC

V

V

5

FN6186.1

February 18, 2008