intersil ISL22316 DATA SHEET

®

www.BDTIC.com/Intersil

Single Digitally Controlled Potentiometer (XDCP™)

ISL22316

Data Sheet February 18, 2008

Low Noise, Low Power I2C® Bus, 128 Taps

The ISL22316 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up, the device recalls the contents of the
DCP’s IVR to the WR.

The DCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

FN6186.1

Features

• 128 resistor taps

2

•I

C serial interface

- Two address pins, up to four devices/bus

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ V

• Shutdown mode

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ +55

• 10 Ld MSOP or 10 Ld TDFN package

• Pb-free (RoHS compliant)

CC

= 3.3V

°C

Pinouts

SCL

SDA

A1

A0

SHDN

ISL22316

(10 LD MSOP)

TOP VIEW

1

2

3

4

5

10

VCC

RH

9

RW

8

7

RL

GND

6

SCL

SDA

SHDN

(10 LD TDFN)

TOP VIEW

1

2

3

A1

A0

4

5

ISL22316

O

10

VCC

RH

9

8

RW

RL

7

GND

6

Ordering Information

PART NUMBER

(Note) PART MARKING

ISL22316UFU10Z* 316UZ 50 -40 to +125 10 Ld MSOP M10.118
ISL22316WFU10Z* 316WZ 10 -40 to +125 10 Ld MSOP M10.118
ISL22316UFRT10Z* 316U 50 -40 to +125 10 Ld 3x3 TDFN L10.3x3B
ISL22316WFRT10Z* 316W 10 -40 to +125 10 Ld 3x3 TDFN L10.3x3B
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

RESISTANCE OPTION

(kΩ)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

1

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved

Block Diagram

www.BDTIC.com/Intersil

ISL22316

V

CC

SCL

SDA

A0
A1

SHDN

I2C

INTERFACE

POWER-UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

NON-VOLATILE

REGISTERS

GND

Pin Descriptions

MSOP PIN

NUMBER

1 1 SCL Open drain I
2 2 SDA Open drain Serial data I/O for the I2C interface
3 3 A1 Device address input for the I
4 4 A0 Device address input for the I
5 5 SHDN Shutdown active low input
6 6 GND Device ground pin
7 7 RL “Low” terminal of DCP
8 8 RW “Wiper” terminal of DCP
9 9 RH “High” terminal of DCP

10 10 VCC Power supply pin

TDFN PIN

NUMBER PIN NAME DESCRIPTION

2

C interface clock input

WR

2

C interface

2

C interface

RH

RW

RL

2

FN6186.1

February 18, 2008

ISL22316

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at any DCP Pin with

Respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Latchup (Note 1) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

ESD Ratings

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV

Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.

2. For θ

3. θ

Analog Specifications Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

R

VRH, V

C

H/CL/CW

(Note 17)

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ R

(Note 9)

(Note 8)

ZSerror

(Note 6)

FSerror

(Note 7)

(Notes 10, 17)

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

is for the location in the center of the exposed metal pad on the package underside.

JC

TOTAL

R

W

INL

DNL

TC

RH to RL Resistance W option 10 kΩ

to RL Resistance Tolerance -20 +20 %

R

H

End-to-End Temperature Coefficient W option ±50 ppm/°C

Wiper Resistance VCC = 3.3V , wiper current = VCC/R

RLVRH

V

and VRL Terminal Voltages VRH and VRL to GND 0 V

Potentiometer Capacitance 10/10/25 pF

Leakage on DCP Pins Voltage at pin from GND to VCC 0.1 1 µA

; VCC @ RH; measured at RW, unloaded)

L

Integral Non-linearity Monotonic over all tap positions, W and U

Differential Non-linearity Monotonic over all tap positions, W and U

Zero-scale Error W option 0 1 5 LSB

Full-scale Error W option -5 -1 0 LSB

Ratiometric Temperature Coefficient DCP register set to 40 hex for W and U

+0.3

CC

CC

U option 50 kΩ

U option ±80 ppm/°C

option

option

U option 0 0.5 2

U option -2 -1 0

option

Thermal Resistance (Typical) θ

10 Lead MSOP (Note 2). . . . . . . . . . . . 120 N/A

10 Lead TDFN (Notes 2, 3) . . . . . . . . . 150 48.3

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

MIN

(Note 18)

TOTAL

-1 1 LSB

-0.5 0.5 LSB

TYP

(Note 4)

(°C/W) θJC (°C/W)

JA

MAX

(Note 18) UNIT

(Note 17)

(Note 17)

70 200 Ω

CC

±4 ppm/°C

V

(Note 5)

(Note 5)

(Note 5)

(Note 5)

3

FN6186.1

February 18, 2008

ISL22316

www.BDTIC.com/Intersil

Analog Specifications Over recommended operating conditions, unless otherwise stated. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

RINL

(Note 14)

RDNL

(Note 13)

Roffset

(Note 12)

Integral Non-linearity DCP register set between 10 hex and 7F

Differential Non-linearity W option -1 1 MI

Offset W option 0 1 5 MI

hex; monotonic over all tap positions;
W and U option

U option -0.5 0.5 MI

U option 0 0.5 2 MI

MIN

(Note 18)

-1 1 MI

Operating Specifications Over the recommended operating conditions, unless otherwise specified.

MIN

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

I

I

LkgDig

t

DCP

(Note 17)

t

ShdnRec

(Note 17)

Vpor Power-on Recall Voltage Minimum V

V

CC

VCC Supply Current (Volatile Write/Read) f

VCC Supply Current (Non-volatile Write/Read) f

VCC Current (Standby) V

SB

VCC Current (Shutdown) V

SD

Leakage Current, at Pins A0, A1, SHDN,
SDA and SCL

DCP Wiper Response Time SCL falling edge of last bit of DCP data byte

DCP Recall Time from Shutdown Mode From rising edge of SHDN

Ramp VCC Ramp Rate 0.2 V/ms

Power-up Delay VCC above Vpor, to DCP Initial Value

t

D

= 400kHz; SDA = Open; (for I2C,

SCL

active, read and write states)

= 400kHz; SDA = Open; (for I2C,

SCL

active, read and write states)

= +5.5V @ +85°C, I2C interface in

CC

standby state

= +5.5V @ +125°C, I2C interface in

V

CC

standby state

= +3.6V @ +85°C, I2C interface in

V

CC

standby state

= +3.6V @ +125°C, I2C interface in

V

CC

standby state

= +5.5V @ +85°C, I2C interface in

CC

standby state

= +5.5V @ +125°C, I2C interface in

V

CC

standby state

= +3.6V @ +85°C, I2C interface in

V

CC

standby state

= +3.6V @ +125°C, I2C interface in

V

CC

standby state
Voltage at pin from GND to V

SDA is inactive

to wiper new position

stored position and RH connection
SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

at which memory recall occurs 2.0 2.6 V

CC

Register recall completed and I
in standby state

CC,

signal to wiper

2

C Interface

(Note 18)

-1 1 µA

TYP

(Note 4)

TYP

(Note 4)

1.5 µs

1.5 µs

1.5 µs

MAX

(Note 18) UNIT

MAX

(Note 18) UNIT

0.5 mA

3mA

5µA

7µA

3µA

5µA

3µA

5µA

2µA

4µA

3ms

(Note 11)

(Note 11)

(Note 11)

(Note 11)

(Note 11)

4

FN6186.1

February 18, 2008

ISL22316

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

EEPROM SPECIFICATION

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T ≤

t

(Note 16)

SERIAL INTERFACE SPECIFICATIONS

V

V

Hysteresis

V

Cpin

(Note 17)

f

SCL

t

t

BUF

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

t

Non-volatile Write Cycle Time 12 20 ms

WC

A1, A0, SHDN, SDA, and SCL Input Buffer

IL

LOW Voltage
A1, A0, SHDN, SDA, and SCL Input Buffer

IH

HIGH Voltage
SDA and SCL Input Buffer Hysteresis 0.05*V
SDA Output Buffer LOW Voltage, Sinking

OL

4mA
A1, A0, SHDN

Capacitance
SCL Frequency 400 kHz

t

Pulse Width Suppression Time at SDA and

sp

SCL Inputs
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until

AA

Time the Bus Must be Free Before the Start

of a New Transmission

Clock LOW Time Measured at the 30% of VCC crossing 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing 600 ns
START Condition Setup Time SCL rising edge to SDA falling edge; both

STAR T Condition Hold Time From SDA falling edge crossing 30% of VCC

Input Data Setup Time From SDA exiting the 30% to 70% of VCC

Input Data Hold Time From SCL rising edge crossing 70% of VCC

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC,

STOP Condition Hold Time for Read, or
Volatile Only Write

Output Data Hold Time From SCL falling edge crossing 30% of

DH

SDA and SCL Rise Time From 30% to 70% of V

t

R

SDA and SCL Fall Time From 70% to 30% of V

t

F

Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF

, SDA, and SCL Pin

Any pulse narrower than the max spec is
suppressed

SDA exits the 30% to 70% of V
SDA crossing 70% of VCC during a STOP

condition, to SDA crossing 70% of V
during the following START condition

crossing 70% of V

to SCL falling edge crossing 70% of V

window, to SCL rising edge crossing 30% of
V

CC

to SDA entering the 30% to 70% of V
window

to SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge;

both crossing 70% of V

V

, until SDA enters the 30% to 70% of

CC

window

V

CC

+55°C 50 Years

window

CC

CC

CC

CC

CC

CC

CC

CC

CC

MIN

(Note 18)

-0.3 0.3*V

0.7*V

00.4V

1300 ns

600 ns

600 ns

100 ns

0ns

600 ns

1300 ns

0ns

20 +

0.1*Cb
20 +

0.1*Cb

CC

CC

TYP

(Note 4)

10 pF

MAX

(Note 18) UNIT

V

+ 0.3 V

CC

50 ns

900 ns

250 ns

250 ns

CC

V

V

5

FN6186.1

February 18, 2008

ISL22316

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

Rpu

t

SU:A

t

HD:A

NOTES:

4. Typical values are for T

5. LSB: [V(R

6. ZS error = V(RW)

7. FS error = [V(RW)

8. DNL = [V(RW)

9. INL = [V(RW)

10. for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

11. MI =

12. Roffset = RW

13. RDNL = (RW

14. RINL = [RW

15. for i = 16 to 127, T = -40°C to 125°C. Max( ) is the maximum value of the resistance and Min ( ) is

16. t

17. Limits should be considered typical and are not production tested.

18. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.

SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and t

A1 and A0 Setup Time Before START condition 600 ns
A1 and A0 Hold Time After STOP condition 600 ns

= +25°C and 3.3V supply voltage.

A

– V(RW)0]/127. V(RW)

incremental voltage when changing from one tap to an adjacent tap.

TC

00 hex respectively.

Roffset = RW

TC

WC

write cycle.

W)127

/LSB.

0

– VCC]/LSB.

127

– V(RW)

i

– (i • LSB) – V(RW)0]/LSB for i = 1 to 127

i

Max V RW()

()Min V RW()

----------------------------------------------------------------------------------------------

V

Max V RW()

()Min V RW()

|RW

– RW

127

/MI, when measuring between RW and RL.

0

/MI, when measuring between RW and RH.

127

– RW

i

– (MI • i) – RW0]/MI, for i = 16 to 127.

i

Max Ri()Min Ri()–[]

--------------------------------------------------------------- -

R

Max Ri()Min Ri()+[]2⁄

is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

()–

i

()+[]2⁄

i

|/127. MI is a minimum increment. RW

0

)/MI -1, for i = 16 to 127.

i-1

×=

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively . LSB is the

127

i

×=

i

6

10

---------------- -

the minimum value of the resistance over the temperature range.

165°C

For Cb = 400pF, max is about 2kΩ~2.5kΩ
For Cb = 40pF, max is about 15kΩ~20kΩ

6

10

---------------- -

165°C

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

and RW0 are the measured resistances for the DCP register set to 7F hex and

127

F

MIN

(Note 18)

1kΩ

TYP

(Note 4)

MAX

(Note 18) UNIT

6

FN6186.1

February 18, 2008

SDA vs SCL Timing

www.BDTIC.com/Intersil

ISL22316

t

t

F

t

HIGH

t

LOW

t

R

sp

t

HD:STO

SCL

t

SU:STA

(INPUT TIMING)

(OUTPUT TIMING)

SDA

SDA

A0 and A1 Pin Timing

A0, A1

SCL

SDA

t

HD:STA

START

t

SU:A

t

SU:DAT

CLK 1

t

HD:DAT

t

SU:STO

t

t

DH

AA

STOP

t

HD:A

t

BUF

Typical Performance Curves

100

VCC = 3.3V, T = +125°C

90
80
70
60
50
40
30

VCC = 3.3V, T = +20°C

20

WIPER RESISITANCE (Ω)

10

0

020406080100120

TAP POSITI ON (DECIMAL)

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[ I(RW) = V

CC/RTOTAL

V

= 3.3V, T = -40°C

CC

] FOR 10kΩ (W)

1.4

1.2

1.0

0.8

(µA)

0.6

SB

I

0.4

0.2

0

2.7 3.2 3.7 4.2 4.7 5.2

T = +125°C

T = +25°C

V

CC

FIGURE 2. STANDBY I

(V)

CC

vs V

CC

7

FN6186.1

February 18, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

0.2
T = +25°C

VCC = 2.7V

0.1

ISL22316

0.2

0.1

T = +25°C

VCC = 2.7V

0

DNL (LSB)

-0.1

VCC = 5.5V

-0.2
0 20406080100120

TAP POSITION (DECIMAL)

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

1.3

1.1

0.9

0.7

(LSB)

0.5

ERROR

0.3

ZS

0.1

-0.1

-0.3

-40 -20 0 20 40 60 80 100 120

FIGURE 5. ZS

10k

VCC = 5.5V

VCC = 2.7V

50k

TEMPERATURE (°C)

vs TEMPERATURE FIGURE 6. FS

ERROR

0

INL (LSB)

-0.1

VCC = 5.5V

-0.2
0 20 40 60 80 100 120

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

0.0

-0.3

VCC = 2.7V

-0.6

(LSB)

-0.9

ERROR

ZS

-1.2

-1.5

-40 -20 0 20 40 60 80 100 120

ERROR

50k

10k

TEMPERATURE (ºC)

vs TEMPERATURE

VCC = 5.5V

0.4

0.2

0

-0.2

DNL (LSB)

-0.4
VCC = 2.7V

-0.6

16 36 56 76 96 116

VCC = 5.5V

TAP POSITION (DECIMAL)

T = +25°C

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

0.4

0.2

0

-0.2

INL (LSB)

-0.4

-0.6
16 36 56 76 96 116

FIGURE 8. INL vs TAP POSITION IN RHEOST AT MODE FOR

10kΩ (W)

8

10kΩ (W)

VCC = 5.5V

TAP POSITI ON (DECIMAL)

T = +25°C

VCC = 2.7V

February 18, 2008

FN6186.1

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

1.0

0.5

CHANGE (%)

0.0

VCC = 5.5V

TOTAL

-0.5

END TO END R

-1.0

-40 -20 0 20 40 60 80 100 120

FIGURE 9. END-TO-END R

TEMPERATURE

VCC = 2.7V

10k

TEMPERATURE (ºC)

% CHANGE vs

TOTAL

50k

ISL22316

105

90

75

60

45

TCv (ppm/°C)

50k

30

15

0

16 36 56 76 96

10k

TAP POSITION (DECIMAL)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

OUTPUT

300

250

200

150

TCr (ppm/°C)

100

50

0

16 36 56 76 96

50k

TAP POSITION (DECIMAL)

10k

INPUT

WIPER AT MID POINT (POSITION 40h)
R

= 9.5kΩ

TOTAL

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (2.6MHz)

SCL

SIGNAL AT WIPER
(WIPER UNLOADED)

WIPER MID POINT MOVEMENT
FROM 3Fh TO 40h

FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h FIGURE 14. LARGE SIGNAL SETTLING TIME

9

SIGNAL AT WIPER
(WIPER UNLOADED MOVEMENT
FROM 7Fh TO 00h)

February 18, 2008

FN6186.1

ISL22316

www.BDTIC.com/Intersil

Pin Description

Potentiometers Pins

RH AND RL

The high (RH) and low (RL) terminals of the ISL22316 are
equivalent to the fixed terminals of a mechanical
potentiometer. RH and RL are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WR set to 127 decimal, the wiper will be
closest to RH, and with the WR set to 0, the wiper is closest
to RL.

RW

RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.

SHDN

The SHDN pin forces the resistor to end-to-end open circuit
condition on RH and shorts RW to RL. When SHDN
returned to logic high, the previous latch settings put RWi at
the same resistance setting prior to shutdown. This pin is
logically OR’d with the SHDN bit in the ACR register. The I
interface is still available in shutdown mode and all registers
are accessible. This pin must remain HIGH for normal
operation.

RH

RW

RL

FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for I
interface. It receives device address, operation code, wiper
address and data from an I
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.

SDA requires an external pull-up resistor, since it is an open
drain input/output.

SERIAL CLOCK (SCL)

This input is the serial clock of the I
requires an external pull-up resistor, since it is an open drain
input.

DEVICE ADDRESS (A1, A0)

The address inputs are used to set the least significant 2 bits
of the 7-bit I

2

C interface slave address. A match in the slave

2

C external master device at the

2

C serial interface. SCL

is

2

C

2

C

address serial data stream must match with the Address input
pins in order to initiate communication with the ISL22316. A
maximum of four ISL22316 devices may occupy the I
bus.

2

C serial

Principles of Operation

The ISL22316 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and an I
serial interface providing direct communication between a
host and the potentiometer and memory. The resistor array
is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.

When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.

DCP Description

The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by a 7-bit
volatile Wiper Register (WR). When the WR of a DCP
contains all zeroes (WR<6:0>: 00h), its wiper terminal (RW)
is closest to its “Low” terminal (RL). When the WR register of
a DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal
(RW) is closest to its “High” terminal (RH). As the value of
the WR increases from all zeroes (0) to all ones (127
decimal), the wiper moves monotonically from the position
closest to RL to the closest to RH. At the same time, the
resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.

While the ISL22316 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reload with the value stored in a
non-volatile Initial Value Register (IVR).

The WR and IVR can be read or written to directly using the

2

I

C serial interface as described in the following sections.

Memory Description

The ISL22316 contains one non-volatile 8-bit register, known
as the Initial V alue Re giste r (IVR), and two vol atile 8 -bit
registers, Wiper Register (WR) and Access Control Register
(ACR). Table 1 shows the Memory map of the ISL22316. The

2

C

10

FN6186.1

February 18, 2008

non-volatile register (IVR) at address 0, contain initial wiper

www.BDTIC.com/Intersil

position and volatile registers (WR) contain current wiper
position.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

2— ACR
1 Reserved
0IVR WR

The non-volatile IVR and volatile WR registers are
accessible with the same address.

The Access Control Register (ACR) contains information
and control bits described in Table 2.

The VOL bit (ACR<7>) determines whether the access is to
wiper registers WR or initial value registers IVR.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

VOL SHDN WIP

If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.

The SHDN bit (ACR<6>) disables or enables Shutdown mode.
This bit is logically OR ‘d with SHDN
DCP is in Shutdown mode. Default value of SHDN bit is 1.

The WIP bit (ACR<5>) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WR or ACR while WIP bit is 1.

00000

pin. When this bit is 0,

I2C Serial Interface

The ISL22316 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22316
operates as a slave device in all applications.

All communication over the I
sending the MSB of each byte of data first.

2

C interface is conducted by

ISL22316

2

All I

C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22316 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 16). A START condition is ignored during the
power-up of the device.

2

All I

C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).

The ISL22316 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22316 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is the Read/Write
“1” for a Read operation, and “0” for a Write operation (see
Table 3).

Logic values at pins A1 and A0 respectively

01010A1A0R/W

(MSB) (LSB)

TABLE 3. IDENTIFICATION BYTE FORMAT

bit. Its value is

Protocol Conventions

Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 16). On power-up of the ISL22316, the SDA pin is in
the input mode.

11

FN6186.1

February 18, 2008

SCL

www.BDTIC.com/Intersil

SDA

ISL22316

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

SIGNALS FROM

START DATA DATA STOP

STABLE CHANGE

DATA

STABLE

FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS

81 9

HIGH IMPEDANCE

START ACK

FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

S

THE MASTER

T
A

IDENTIFICATION

R
T

BYTE

ADDRESS

BYTE

DATA
BYTE

HIGH IMPEDANCE

S
T

O

P

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

00011

0

A0A1

0000

A
C
K

0

FIGURE 18. BYTE WRITE SEQUENCE

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

S
T
A

IDENTIFICATION

R

BYTE WITH

T

R/W

00011

0

= 0

A
C
K

ADDRESS

BYTE

0000A0A1 A0A1

S

T

A

IDENTIFICATION

R

T

A
C
K

BYTE WITH

R/W

= 1

0010

1

1

A
C
K

FIGURE 19. READ SEQUENCE

12

A
C
K

FIRST READ

DATA BYTE

A
C
K

A
C
K

A
C
K

LAST READ
DATA BYTE

February 18, 2008

S
T

A

O

C

P

K

FN6186.1

ISL22316

www.BDTIC.com/Intersil

Write Operation

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22316 responds with an ACK. At this time, the device
enters its standby state (see Figure 18).

The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write.

Read Operation

A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 19). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W
the three bytes, the ISL22316 responds with an ACK. Then
the ISL22316 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a ACK
last bit of the last Data Byte (see Figure 19).

In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.

bit set to “1”. After each of

and STOP condition) following the

bit

13

FN6186.1

February 18, 2008

ISL22316

www.BDTIC.com/Intersil

Thin Dual Flat No-Lead Plastic Package (TDFN)

(DATUM B)

6

INDEX

AREA

(DATUM A)

NX (b)

5

SECTION "C-C"

A

6

INDEX
AREA

SEATING

PLANE

NX L

8

C

12

N

BOTTOM VIEW

D

TOP VIEW

SIDE VIEW

D2

N-1

e
(Nd-1)Xe

REF.

(A1)

2X

2X

E

A

A3

87

D2/2

NX k

E2

E2/2

NX b

5

M

0.10

C

L

e

CC

FOR ODD TERMINAL/SIDE

ABC0.15

CB

0.15

//

TERMINAL TIP

9

0.10

0.08

L

C

C

BAC

L10.3x3B

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A
A1
A3

b

D
D2

E
E2

e

k

L

0.70 0.75 0.80

- - 0.05

0.20 REF

0.18 0.25 0.30

3.00 BSC

2.23 2.38 2.48

3.00 BSC

1.49 1.64 1.74

0.50 BSC

0.20 - -

0.30 0.40 0.50

N102
Nd 5 3

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.

NOTESMIN NOMINAL MAX

-

-

-

5, 8

-

7, 8

-

7, 8

-

-

8

Rev. 0 2/06

14

FN6186.1

February 18, 2008

ISL22316

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.007 0.011 0.18 0.27 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

o

θ

α

5

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 0 12/02

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

15

FN6186.1

February 18, 2008