intersil ISL21400 DATA SHEET

®

ISL21400

Data Sheet April 24, 2007

Programmable Temperature Slope Voltage Reference

The ISL21400 features a precision voltage reference combined with a temperature sensor whose output voltage varies linearly with temperature. The precision 1.20V reference has a very low temperature coefficient (tempco), and its output voltage is scaled by an internal DAC (V

REF

) to produce a temperature stable output voltage that is programmable from 0V to 1.20V. The output voltage from the temperature sensor (V

) is summed with V

TS

to produce

REF

a temperature dependent output voltage. The slope of the V

portion of the output voltage can be

TS

programmed to be positive or negative in the range

-2.1mV/°C to +2.1mV/°C. A programmable gain amplifier (PGA) sums the V

and the V

TS

voltages and provides

REF

gains of 1x, 2x, and 4x to scale the output up to 4.8V and the slope to ±8.4mV/°C.

The V resolution via an I non-volatile registers. The PGA gain is also set via the I

REF

and V

terms are programmable with 8 bits of

TS

2

C bus and the values are stored in

2

C bus and the value is stored in a non-volatile register. Non-volatile memory storage assures the programmed settings are retained on power-down, eliminating the need for software initialization at device power-up.

Temperature Characteristics Curve

3.0

2.5

2.0 TS = 0

1.5

VREF (V)

1.0 TS = 0

0.5

0.0

-40 -15 10 35 60 85

AV = 2

TS = 127

= 1

A

V

TEMPERATURE (°C)

TS = 255

TS = 127

FN8091.1

Features

• Programmable reference voltage

• Programmable temperature slope

• Programmable Gain Amplifier

• Non-volatile storage of programming registers

•I2C serial interface

• 2% total accuracy over temperature and V

CC

range

• 200µA typical active supply current

• Operating temperature range = -40°C to +85°C

• 8 Ld MSOP package

• Pb-free plus anneal available (RoHS compliant)

Applications

• RF power amplifier bias compensation

• LCD bias compensation

• Laser diode bias compensation

• Sensor bias and linearization

• Data acquisition systems

• Variable DAC reference

• Amplifier biasing

Pinout

ISL21400

(8 LD MSOP)

TOP VIEW

A2

V

A1 A0

SS

1 2

3 4

V

CC

8

V

7

OUT

6

SDA SCL

5

Ordering Information

RANGE

V

DD

PART NUMBER (Note) PART MARKING

ISL21400IU8Z DEW 2.7 to 5.5 -40 to +85 8 Ld MSOP (3.0mm), green mtl M8.118 ISL21400IU8Z-TK DEW 2.7 to 5.5 -40 to +85 8 Ld MSOP (3.0mm), green mtl M8.118

NOTE: Intersil Pb-free products employ special Pb-free ma terial sets; molding compou nds/die att ach materials an d 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

1

(V)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

TEMP RANGE

(°C)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL21400

Pin Description

MSOP SYMBOL DESCRIPTION

1 A2 Hardwire slave address pin for I 2 A1 Hardwire slave address pin for I 3 A0 Hardwire slave address pin for I 4V

SS

Ground pin

2

C serial bus

2

C serial bus

2

C serial bus

5 SCL Serial bus clock input 6 SDA Serial bus data input/output 7 VOUT Output voltage 8V

CC

Device power supply

Block Diagram

VCC

TEMP SENSE

V

BIAS

n = 0 to 255

m = 0 to 255

REF

V

REF

(n)

TS

DAC

(m)

DAC

EEPROM 5 BYTES

VSS

S

COMMUNICATIONS

A

AND

REGISTERS

A0 A1 A2

GAIN SELECT AV = 1, 2, 4

V

OUT

SCL

SDA

2

FN8091.1

April 24, 2007

ISL21400

Absolute Maximum Ratings Thermal Information

Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to 6.5V

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on V

Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to V

OUT

CC

Voltage on All Other Pins . . . . . . . . . . . . . . . . . .-0.3V to VCC+0.3V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical) θ

(°C/ W)

JA

8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 130

Moisture Sensitivity for MSOP Package

(See Technical Brief TB363) . . . . . . . . . . . . . . . . . . . . . . . Level 2

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Analog Specifications V

= 5.5V, TA= +25°C to +85°C, Unless Otherwise Noted

CC

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

(Note 2) MAX UNITS

POWER SUPPLY

V

I

Q(NV)

Vpor Power-on Recall Voltage

V

Ramp

Supply Voltage Range 2.7 3.0 5.5 V

CC

I

Supply

Q

= 2.7V Standby, SDA = SCL = V

V

CC

V

= 5.5V Standby, SDA = SCL = V

CC

CC CC

200 400 µA 235 500 µA

Non-Volatile Supply

= 2.7V Nonvolatile write 500 750 µA

V

CC

V

= 5.5V Nonvolatile write 1.3 1.6 mA

CC

2.0 2.6 V

CC

t

D

Minimum V occurs

Ramp Rate 0.2 V/ms

V

CC

Power-Up Delay V

above Vpor, time delay to Register

CC

recall, and I

at which memory recall

CC

2

C Interface in standby state

3ms

OUTPUT VOLTAGE PERFORMANCE SPECIFICATIONS

G G

Gain Error AV = 2 (Notes 1, 3, 12) -1 +1 %

E1

Gain Error AV = 4 (Notes 1, 3, 12) -1 +1 %

E2

K Temperature Sensor Coefficient (Notes 1, 8) -2.2 -2.1 -2.0 mV/°C

Absolute Output Voltage (Swing) Range Unloaded, T

Absolute Output Voltage (Swing) Range Loaded, I TS1 Temperature Sensor Slope A TS2 Temperature Sensor Slope A TS3 Temperature Sensor Slope A TS4 Incremental Temperature Sensor Slope A

= 1, n = 255, m = 255 (Notes 1, 6) -2.1 mV/°C

V

= 2, n = 255, m = 255 (Notes 1, 6) -4.2 mV/°C

V

= 4, n = 255, m = 255 (Notes 1, 6) -8.4 mV/°C

V

= 1, n = 255, m = 0 to 255 (Notes 1,

V

= +25°C (Note 3) VCC - 0.100 GND + 0.100 V

A

= ±500µA (Note 3) VCC - 0.250 GND + 0.250 V

OUT

8.2 μV/°C

10)

TSNL Temperature Slope Non-Linearity n = 255, m = 0 to 255, T = -40°C to +85°C

±0.5 ±1.0 %

(Notes 1, 11)

DNL DAC Relative Linearity

(V

= 2.7 to 5.5V)

CC

and Temp Sense; AV = 1 (Note 13) -1.0 +1.0 LSB

V

REF

per

Code

3

FN8091.1

April 24, 2007

ISL21400

Analog Specifications V

= 5.5V, TA= +25°C to +85°C, Unless Otherwise Noted

CC

SYMBOL PARAMETER TEST CONDITIONS MIN

INL DAC Absolute Linearity (VCC = 2.7 to

V

and Temp Sense; AV = 1 (Note 13) -3.0 +3.0 LSB

REF

5.5V)

V

OUT(TE)

V

OUT1

OUT2

OUT3

OUT4

Total Error for V

Output Voltage V

OUT

, Gain = 1 AV = 1, n = 255, m = 128, TA=+25°C,

REF

, Gain = 2 AV = 2, n = 255, m = 128, TA=+25°C,

REF

, Gain = 4 AV = 4, n = 255, m = 128, TA=+25°C,

REF

+ TS AV = 1, n = 255, m = 0, TA = +85°C

REF

(Notes 1, 8, 9) ±1 ±2 %

V

=5.5V

CC

V

=5.5V

CC

V

=5.5V

CC

1.189 1.2 1.211 V

2.378 2.40 2.422 V

4.756 4.80 4.844 V

1.315 1.326 1.337 V

(Note 3)

V

OUT5

OUT6

OUT7

Output Voltage V

+ TS AV = 1, n = 255, m = 128, TA=+85°C

REF

+ TS AV = 1, n = 255, m = 255, TA=+85°C

REF

+ TS AV = 1, n = 255, m = 0, TA= -40°C,

REF

(Note 3)

1.188 1.199 1.210 V

1.063 1.074 1.085 V

1.052 1.063 1.074 V

(Note 3)

V

OUT8

OUT9

Output Voltage V

+ TS AV = 1, n = 255, m = 128, TA= -40°C,

REF

+ TS AV = 1, n = 255, m = 255, TA= -40°C,

REF

(Note 3)

1.189 1.200 1.211 V

1.336 1.325 1.347 V

(Note 3)

OUTPUT VOLTAGE DC SPECIFICATIONS

PSRR Power Supply Rejection Ratio A

R

Output Impedance (load regulation) Given by R

OUT

I

Short Circuit, Sourcing V

SC

Short Circuit, Sinking V

C

Load Capacitance Reference output stable for all CL up to

L

= 1, n = 255, m = 128, (Note 7) 50 60 dB

V

T

= +25°C, I

A

= 5.5V, V

CC

= 5.5V, V

CC

OUT

= (ΔV

OUT

OUT OUT

/ΔI

OUT

),

OUT

= ±500µA

= 0V 5 9 mA = 5.5V 6 9 mA

specifications

OUTPUT VOLTAGE AC SPECIFICATIONS

Output Voltage Noise 0.1Hz to 10Hz, AV =1 90 µV

V

N

10Hz to 10kHz, CL = 0, AV = 1 TBD mV Power On Response 1% Settling 500 µs Line Ripple Rejection V

= 5V ±100mV, f = 120Hz 60 dB

CC

TYP

(Note 2) MAX UNITS

25Ω

5nF

P-P

RMS

Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise)

SYMBOL PARAMETER TEST CONDITIONS MIN

I

LI

V

IL

V

IH

Hysteresis SDA and SCL Input Buffer

V

OL

C

Input Leakage VIN = GND to V

CC

Input LOW Voltage -0.3 0.3 x V Input HIGH Voltage 0.7 x V

0.05 x V

Hysteresis SDA Output Buffer LOW Voltage IOL = 3mA 0 0.4 V Pin Capacitance (Note 3) 10 pF

4

CC

TYP

(Note 2) MAX UNITS

1V

CC

V

+ 0.3 V

CC

V

FN8091.1

April 24, 2007

ISL21400

Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise) (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

f

SCL

t

sp

SCL Frequency (Note 3) 400 kHz Pulse Width Suppression Time at

SDA and SCL Inputs

Any pulse narrower than the max spec is suppressed (Note 3)

t

AA

SCL Falling Edge to SDA Output Data Valid

SCL falling edge crossing 30% of V the 30% to 70% of V

, until SDA exits

CC

window (Note 3)

t

BUF

Time the Bus Must be Free Before the Start of a New Transmission

SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of V during the following START

CC

1300 ns

condition (Note 3)

t

LOW

t

HIGH

Clock LOW Time Measured at the 30% of VCC

crossing (Note 3)

Clock HIGH Time Measured at the 70% of VCC

1300 ns

600 ns

crossing (Note 3)

t

SU:STA

t

HD:STA

t

SU:DAT

START Condition Setup Time SCL rising edge to SDA

falling edge; both crossing 70% of V

(Note 3)

CC

START Condition Hold Time From SDA falling edge

crossing 30% of V falling edge crossing 70% of V

(Note 3)

CC

to SCL

Input Data Setup Time From SDA exiting the 30% to

70% of V

window, to SCL

CC

600 ns

100 ns

rising edge crossing 30% of V

(Note 3)

CC

t

HD:DAT

t

SU:STO

t

HD:STO

t

DH

Input Data Hold Time From SCL rising edge

crossing 70% of V entering the 30% to 70% of V

window (Note 3)

CC

STOP Condition Setup Time From SCL rising edge

STOP Condition Hold Time for Read, or Volatile Only Write

crossing 70% of V rising edge crossing 30% of V

(Note 3)

CC

From SDA rising edge to SCL falling edge; both crossing 70% of V

(Note 3)

CC

, to SDA

CC

Output Data Hold Time From SCL falling edge

crossing 30% of V

CC

to SDA

, until

0ns

600 ns

1300 ns

0ns

SDA enters the 30% to 70% of V

window (Note 3)

CC

t

R

SDA and SCL Rise Time From 30% to 70% of VCC

20 + 0.1 x Cb 250 ns

(Note 3)

t

F

Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip

SDA and SCL Fall Time From 70% to 30% of VCC

(Note 3)

20 + 0.1 x Cb 250 ns

10 400 pF

(Note 4)

(Note 2) MAX UNITS

TYP

50 ns

900 ns

5

FN8091.1

April 24, 2007

ISL21400

Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise) (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

1kΩ

Rpu SDA and SCL Bus Pull-up Resistor

Off-chip

Maximum is determined by t and t

F

For Cb = 400pF , max is about

R

2~2.5kΩ For Cb = 40pF, max is about

15~20kΩ I V

V

LO

IL

IH

Output Leakage Current (SDA only) V A1, A0, SHDN, SDA, and SCL Input

Buffer LOW Voltage A1, A0, SHDN, SDA, and SCL Input

= GND to V

OUT

CC

-0.3 VCC x 0.3 V

VCC x 0.7 V

Buffer HIGH Voltage

V

OL

C

SDA Output Buffer LOW Voltage IOL = 100µA (Note 3), at 3mA

sink

Capacitive Loading of SDA or SCL Total on-chip and off-chip

L

(Note 3)

00.4V

10 400 pF

EEPROM Endurance 1,000,000 Cycles

t

WC

(Note 14)

EEPROM Retention Temperature T Non-Volatile Write Cycle Time 12 20 ms

≤ +55°C 50 Years

(Note 2) MAX UNITS

TYP

1µA

CC

V

Timing Diagrams

Bus Timing

t

F

SCL

(INPUT TIMING)

(OUTPUT TIMING)

SDA

t

SU:STA

t

HD:STA

t

SU:DAT

Write Cycle Timing

SCL

SDA

NOTES:

1. Equation 1 governs the output voltage and is stated as follows:

V

2. Typical values are for T

8th BIT OF LAST BYTE ACK

⎧⎫

• n = 0 to 255, m = 0 to 255, K = -2.1mV/C(typ), T0 = +25°C,=

OUTAVVREF

⎨⎬ ⎩⎭

= +25°C and VCC = 5.5V.

A

n

--------- -

• KT T

+

255

t

HIGH

2m•()255–

--------------------------------

–()

0

255

t

LOW

t

HD:DAT

STOP

CONDITION

t

DH

sp

START

CONDITION

t

BUF

t

HD:STO

t

SU:STO

t

R

t

AA

t

WC

6

FN8091.1

April 24, 2007