intersil ISL2111 DATA SHEET

®

www.BDTIC.com/Intersil

ISL2110, ISL2111

Data Sheet April 25, 2008 FN6295.3

100V, 3A/4A Peak, High Frequency
Half-Bridge Drivers

The ISL2110, ISL2111 are 100V, high frequency, half-bridge
N-Channel power MOSFET driver ICs. They are based on
the popular HIP2100, HIP2101 half-bridge drivers, but offer
several performance improvements. Peak output pull-up/
pull-down current has been increased to 3A/4A, which
significantly reduces switching power losses and eliminates
the need for external totem-pole buffers in many
applications. Also, the low end of the V
range has been extended to 8VDC. The ISL2110 has
additional input hysteresis for superior operation in noisy
environments and the inputs of the ISL2111, like those of the
ISL2110, can now safely swing to the V

operational supply

DD

supply rail.

DD

Ordering Information

PART

NUMBER

(Notes 1, 2)

ISL2110ABZ 2110 ABZ -40 to +125 8 Ld SOIC M8.15
ISL2110AR4Z 211 0AR4Z -40 to +125 12 Ld 4x4 DFN L12.4x4A
ISL2111ABZ 2111 ABZ -40 to +125 8 Ld SOIC M8.15
ISL2111AR4Z 211 1AR4Z -40 to +125 12 Ld 4x4 DFN L12.4x4A
ISL2111ARTZ 211 1ARTZ -40 to +125 10 Ld 4x4 TDFN L10.4x4

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb­free material sets; molding compounds/die attach materials and
100% matte tin plate PLUS ANNEAL - e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.

2. Add “-T” suffix for Tape and Reel p acking option. Please refer to
TB347 for details on reel specifications.

PART

MARKING

TEMP.

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

Features

• Drives N-Channel MOSFET Half-Bridge

• SOIC, DFN and TDFN Package Options

• SOIC, DFN and TDFN Packages Compliant with 100V
Conductor Spacing Guidelines per IPC-2221

• Pb-Free (RoHS Compliant)

• Bootstrap Supply Max Voltage to 114VDC

• On-Chip 1Ω Bootstrap Diode

• Fast Propagation Times for Multi-MHz Circuits

• Drives 1nF Load with Typical Rise/Fall Times of 9ns/7.5ns

• CMOS Compatible Input Thresholds (ISL2110)

• 3.3V/TTL Compatible Input Thresholds (ISL2111)

• Independent Inputs Provide Flexibility

• No Start-Up Problems

• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground or HS Slewing at High dv/dt

• Low Power Consumption

• Wide Supply Voltage Range (8V to 14V)

• Supply Undervoltage Protection

•1.6Ω/1Ω Typical Output Pull-Up/Pull-Down Resistance

Applications

• Telecom Half-Bridge DC/DC Converters

• Telecom Full-Bridge DC/DC Converters

• Two-S wi tch Forward Converters

• Active-Clamp Forward Converters

• Class-D Audio Amplifiers

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2006-2008. All Rights Reserved.

Pinouts

www.BDTIC.com/Intersil

ISL2111

(10 LD 4X4 TDFN)

TOP VIEW

ISL2110, ISL2111

ISL2110, ISL2111
(12 LD 4X4 DFN)

TOP VIEW

VDD

1

HB

2

HO

3
4

HS
NC

5

Application Block Diagram

LO

10

VSS

9

LI

8
7

HI
NC

6

V

1

DD

2

NC

3

NC
HB
HO
HS HI

EPAD*

4
5
6 7

*EPAD = Exposed PAD

12
11
10

9
8

LO
V
NC
NC
LI

SS

ISL2110, ISL2111

(8 LD SOIC)

TOP VIEW

+12V

1

V

DD

HB

2

HO

3

HS

4

8

LO
V

7

SS

LI

6

HI

5

+100V

PWM

CONTROLLER

V

DD

HB

HI

LI

DRIVE

DRIVE

CONTROL

ISL2110
ISL2111

V

SS

HI

LO

HO

HS

LO

REFERENCE

ISOLATION

SECONDARY

CIRCUIT

AND

2

FN6295.3

April 25, 2008

Functional Block Diagram

www.BDTIC.com/Intersil

V

DD

HI

LI

V

SS

*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For

best thermal performance connect the EPAD to the PCB power ground plane.

UNDER

VOLTAGE

ISL2111

ISL2111

ISL2110, ISL2111

LEVEL SHIFT

UNDER

VOLTAGE

HB

HO

DRIVER

HS

LO

DRIVER

EPAD (DFN Package Only)

+12V

+12V

+48V

PWM

ISL2110
ISL2111

FIGURE 1. TWO-SWITCH FORWARD CONVERTER

+48V

PWM

ISL2110
ISL2111

SECONDARY

CIRCUIT

ISOLATION

SECONDARY

CIRCUIT

FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP

3

ISOLATION

FN6295.3

April 25, 2008

ISL2110, ISL2111

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage, V

LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . .-0.3V to V

Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . .-0.3V to V

Voltage on HO (Note 4) . . . . . . . . . . . . . . V

Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V

Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118V

Average Current in V

DD, VHB

- VHS (Notes 3, 4) . . . . . . . .-0.3V to 18V

DD

- 0.3V to V

HS

to HB Diode . . . . . . . . . . . . . . . . . . 100mA

DD

DD
HB

+ 0.3V
+ 0.3V
+ 0.3V

Maximum Recommended Operating Conditions

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V

Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V

Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V

Voltage on HB . .V

HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

3. The ISL2110 and ISL21 11 are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating
curve for this mode of operation.

4. All voltages referenced to V

5. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

6. θ

JA

Tech Brief TB379.

7. For θ

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

and are not production tested.

+ 7V to VHS + 14V and VDD - 1V to V

HS

unless otherwise specified.

SS

DD

+ 100V

Thermal Resistance (Typical) θ

8 Ld SOIC (Note 5) . . . . . . . . . . . . . . . 95 N/A

10 Ld TDFN (Notes 6, 7) . . . . . . . . . . . 42 5.5

12 Ld DFN (Notes 6, 7) . . . . . . . . . . . . 40 5.5

Max Power Dissipation at +25°C in Free Air

8 Ld SOIC (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W

10 Ld TDFN (Notes 6, 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W

12 Ld DFN (Notes 6, 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W

Storage Temperature Range. . . . . . . . . . . . . . . . . . . -65°C to +150°C

Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

(°C/W) θJC (°C/W)

JA

Electrical Specifications V

PARAMETERS SYMBOL TEST CONDITIONS

SUPPLY CURRENTS

V

Quiescent Current I

DD

V

Quiescent Current I

DD

V

Operating Current I

DD

Operating Current I

V

DD

Total HB Quiescent Current I
Total HB Operating Current I
HB to V
HB to V

INPUT PINS

Low Level Input Voltage Threshold V
Low Level Input Voltage Threshold V
High Level Input Voltage Threshold V
High Level Input Voltage Threshold V
Input Voltage Hysteresis V
Input Pull-Down Resistance R

Current, Quiescent I

SS

Current, Operating I

SS

DD

= V

HB

DD

DD
DDO
DDO

HB
HBO
HBS

HBSO

IL

IL
IH
IH

IHYS

I

= 12V, V

= V

SS

ISL2110; LI = HI = 0V - 0.1 0.25 - 0.3 mA
ISL2111; LI = HI = 0V - 0.3 0.45 - 0.55 mA
ISL2110; f = 500kHz - 3.4 5.0 - 5.5 mA
ISL2111; f = 500kHz - 3.5 5.0 - 5.5 mA
LI = HI = 0V - 0.1 0.15 - 0.2 mA
f = 500kHz - 3.4 5.0 - 5.5 mA
LI = HI = 0V; VHB = VHS = 114V - 0.05 1.5 - 10 µA
f = 500kHz; VHB = VHS = 114V - 1.2 - - - mA

ISL2110 3.7 4.4 - 3.5 - V
ISL2111 1.4 1.8 - 1.2 - V
ISL2110 - 6.6 7.4 - 7.6 V
ISL2111 - 1.8 2.2 - 2.4 V
ISL2110 - 2.2 - - - V

= 0V, No Load on LO or HO, Unless Otherwise Specified.

HS

T

= +25°C TJ = -40°C to +125°C

J

(Note 8)

- 210 - 100 500 kΩ

MIN

MAX

(Note 8)

UNITSMIN TYP MAX

4

FN6295.3

April 25, 2008

ISL2110, ISL2111

www.BDTIC.com/Intersil

Electrical Specifications V

DD

PARAMETERS SYMBOL TEST CONDITIONS

UNDERVOLTAGE PROTECTION

Rising Threshold V

V

DD

V

Threshold Hysteresis V

DD

HB Rising Threshold V
HB Threshold Hysteresis V

BOOT STRAP DIODE

Low Current Forward Voltage V
High Current Forward Voltage V
Dynamic Resistance R

LO GATE DRIVER

Low Level Output Voltage V
High Level Output Voltage V
Peak Pull-Up Current I
Peak Pull-Down Current I

HO GATE DRIVER

Low Level Output Voltage V
High Level Output Voltage V
Peak Pull-Up Current I
Peak Pull-Down Current I

= V

HB

DDR
DDH

HBR
HBH

DL

DH

D

OLL
OHL

OHL

OLL

OLH

OHH
OHH
OLH

= 12V, V

SS

= V

= 0V, No Load on LO or HO, Unless Otherwise Specified. (Continued)

HS

TJ = +25°C TJ = -40°C to +125°C

MIN

(Note 8)

MAX

(Note 8)

6.1 6.6 7.1 5.8 7.4 V

-0.6- - - V

5.5 6.1 6.8 5.0 7.1 V

-0.6- - - V

I
I
I

= 100µA - 0.5 0.6 - 0.7 V

VDD-HB

= 100mA - 0.7 0.9 - 1 V

VDD-HB

= 100mA - 0.7 1 - 1.5 Ω

VDD-HB

ILO = 100mA - 0.1 0.18 - 0.25 V
ILO = -100mA, V

OHL

= V

DD

- V

LO

- 0.16 0.23 - 0.3 V
VLO = 0V - 3 - - - A
VLO = 12V - 4 - - - A

IHO = 100mA - 0.1 0.18 - 0.25 V
IHO = -100mA, V

OHH

= V

HB

- V

- 0.16 0.23 - 0.3 V

HO

VHO = 0V - 3 - - - A
VHO = 12V - 4 - - - A

UNITSMIN TYP MAX

Switching Specifications V

= VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified.

DD

PARAMETERS SYMBOL

Lower Turn-Off Propagation Delay (LI Falling to LO Falling) t
Upper Turn-Off Propagation Delay (HI Falling to HO Falling) t
Lower Turn-On Propagation Delay (LI Risin g to LO Risin g) t
Upper Turn-On Propagation Delay (HI Rising to HO Rising ) t
Delay Matching: Upper Turn-Off to Lower Turn-On t
Delay Matching: Lower Turn-Off to Upper Turn-On t
Either Output Rise Time (10% to 90%) t
Either Output Fall Time (90% to 10%) t
Either Output Rise Time (3V to 9V) t
Either Output Fall Time (9V to 3V) t
Minimum Input Pulse Width that Changes the Output t
Bootstrap Diode Turn-On or Turn-Off Time t

LPHL
HPHL
LPLH
HPLH

MON

MOFF

RC
FC

R

F
PW
BS

= -40°C

T

J

to +125°C

MIN

(Note 8)

MAX

(Note 8)

UNITSMIN TYP MAX

TEST

CONDITIONS

T

= +25°C

J

- 32 50 - 60 ns

- 32 50 - 60 ns

- 39 50 - 60 ns

- 38 50 - 60 ns
1 8 - - 16 ns
1 6 - - 16 ns

CL = 1nF - 9 - - - ns
CL = 1nF - 7.5 - - - ns
CL = 0.1µF - 0.3 0.4 - 0.5 µs
CL = 0.1µF - 0.19 0.3 - 0.4 µs

- - - - 50 ns

-10- - - ns

5

FN6295.3

April 25, 2008

ISL2110, ISL2111

www.BDTIC.com/Intersil

Pin Descriptions

SYMBOL DESCRIPTION

V

DD

Positive supply to lower gate driver. Bypass this pin to VSS.

HB High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.

Bootstrap diode is on-chip.
HO High-side output. Connect to gate of high-side power MOSFET.
HS High-side source connection. Connect to source of high-side power MOSFET . Connect negative side of bootstrap capacitor to this

pin.

HI High-side input.
LI Low-side input.

V

SS

Chip negative supply, which will generally be ground.
LO Low-side output. Connect to gate of low-side power MOSFET.
NC No Connect.

EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.

Timing Diagrams

HI, LI

t

,

HPLH

t

LPLH

HO, LO

FIGURE 3. PROPAGATION DELAYS

Typical Performance Curves

10.0

T = -40°C

(mA)

1.0

DDO

I

0.1
10k 100k 1

FIGURE 5. ISL2110 I

FREQUENCY

T = +25°C

T = +150°C

DD

T = +125°C

FREQUENCY (Hz)

OPERATING CURRENT vs

t

HPHL

t

LPHL

,

.103

LI

HI

LO

t

MOFF

HO

t

MON

FIGURE 4. DELAY MATCHING

10.0

T = -40°C

T = +25°C

(mA)

1.0

DDO

I

T = +125°C

T = +150°C

0.1

k

10k 100k 1.103k

FREQUENCY (Hz)

FIGURE 6. ISL2111 I

FREQUENCY

OPERATING CURRENT vs

DD

6

FN6295.3

April 25, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL2110, ISL2111

10.0

T = -40°C

(mA)

HBO

I

1.0

0.1

0.01

T = +25°C

T = +125°C

10k 100k 1

FREQUENCY (Hz)

T = +150°C

.103

k

FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY FIGURE 8. I

300

250

(mV)

200

OHH

, V

150

OHL

V

100

50

-50 0 50 100 150

VDD = VHB = 14V

VDD = VHB = 8V

VDD = VHB = 12V

TEMPERATURE (°C)

10.0

T = +150°C

1.0

(mA)

HBSO

I

(mV)

OLH

, V

OLL

V

T = +25°C

0.1

0.01

200

150

100

50

T = +125°C

10k 100k 1

OPERATING CURRENT vs FREQUENCY

HBS

-50 0 50 100 150

T = -40°C

FREQUENCY (Hz)

VDD = VHB = 14V

VDD = VHB = 8V

VDD = VHB = 12V

TEMPERATURE (°C)

FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs

TEMPERATURE

.103

k

6.7

6.5

6.3

(V)

6.1

HBR

5.9

, V

DDR

5.7

V

5.5

5.3

-50 0 50 100 150

V

HBR

TEMPERATURE (°C)

V

DDR

FIGURE 11. UNDERVOL T AGE LOCKOUT THRESHOLD vs

TEMPERATURE

7

0.70

0.65

V

0.60

(V)

HBH

0.55

, V

0.50

DDH

V

0.45

0.40

V

-50 0 50 100 150

HBH

DDH

TEMPERATURE (°C)

FIGURE 12. UNDERVOLT AGE LOCKOUT HYSTERESIS vs

TEMPERATURE

FN6295.3

April 25, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL2110, ISL2111

55

(ns)

50

HPHL

45

, t

HPLH

40

, t

35

LPHL

, t

30

LPLH

t

25

-50 0 50 100 150

t

HPLH

TEMPERATURE (°C)

t

HPHL

t

LPLH

t

LPHL

FIGURE 13. ISL2110 PROPAGA TION DELAYS vs

TEMPERATURE

8.0

7.5

7.0

(ns)

6.5

6.0

MOFF

, t

5.5

MON

t

5.0

4.5

4.0

-50 0 50 100 150

TEMPERATURE (°C)

t

MON

t

MOFF

55

(ns)

50

HPHL

45

, t

HPLH

40

, t

35

LPHL

, t

30

LPLH

t

25

-50 0 50 100 150

t

HPLH

TEMPERATURE (°C)

t

HPHL

t

LPLH

FIGURE 14. ISL2111 PROPAGATION DELAYS vs

TEMPERATURE

10.0

9.5

9.0

8.5

8.0

(ns)

7.5

7.0

MOFF

6.5

, t

6.0

MON

t

5.5

5.0

4.5

4.0

-50 0 50 100 150

TEMPERATURE (°C)

t

MON

t

t

MOFF

LPHL

FIGURE 15. ISL2110 DELAY MATCHING vs TEMPERATURE FIGURE 16. ISL2111 DELAY MATCHING vs TEMPERATURE

(A)

OHH

, I

OHL

I

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

2.5

(A)

2.0

OHH

, I

1.5

OHL

I

1.0

0.5

0

0481012

26 0481012

V

LO

, VHO (V)

FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT

8

26

V

LO

, VHO (V)

VOLTAGE

FN6295.3

April 25, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL2110, ISL2111

120
110
100

90
80
70

(µA)

60

HB

, I

50

DD

I

40
30
20
10

0

0 5 10 15 20

I

DD

I

HB

V

, VHB (V)

DD

320
300
280
260
240
220
200

(µA)

180
160

HB

, I

140
120

DD

I

100

80
60
40
20

0

0 5 10 15 20

I

DD

I

HB

, VHB (V)

V

DD

FIGURE 19. ISL2110 QUIESCENT CURRENT vs VOLTAGE FIGURE 20. ISL2111 QUIESCENT CURRENT vs VOLTAGE

1.00

0.10

0.01

.10-3

1

-4

1.10

-5

1.10

FORWARD CURRENT (A)

-6

1.10

0.3 0.4 0.5 0.6 0.7 0.8

FORWARD VOLTAGE (V)

FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS FIGURE 22. V

120

100

80

VOLTAGE (V)

60

SS

40

TO V

DD

20

V

0

12 13 14 15 16

V

TO VSS VOLTAGE (V)

HS

VOLTAGE vs VDD VOLTAGE

HS

9

FN6295.3

April 25, 2008

ISL2110, ISL2111

www.BDTIC.com/Intersil

Package Outline Drawing

L10.4x4

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/08

A

B

4.00

INDEX AREA

PIN #1 INDEX AREA

6

PIN 1

3.2 REF

BSC

6

8X 0.80

1

5

10X 0 . 40

( 3.80)

4.00

TOP VIEW

( 3.00 )

0.15

( 10 X 0.60 )

( 2.60)

(4X)

0 .75

2.60

10

3.00

BOTTOM VIEW

SIDE VIEW

0 . 2 REF

C

6

0.104CAMB

0.05 M

10 X 0.30

SEE DETAIL "X"

BASE PLANE

C

C

0.10

C

SEATING PLANE

0.08

C

( 8X 0 . 8 )

TYPICAL RECOMMENDED LAND PATTERN

( 10X 0 . 30 )

NOTES:

Dimensions are in millimeters.1.
Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

2.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05
Dimension b applies to the metallized terminal and is measured

4.
between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

The configuration of the pin #1 identifier is optional, but must be

6.
located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

10

0 . 00 MIN.
0 . 05 MAX.

DETAIL "X"

FN6295.3

April 25, 2008

ISL2110, ISL2111

www.BDTIC.com/Intersil

Dual Flat No-Lead Plastic Package (DFN)
Micro Lead Frame Plastic Package (MLFP)

2X

0.15

A

E1/2 E/2

A2

A1

A3

NX k

4X P

M

0.10 C A

L

C

E1 E

9

A

//

5

B

5

2X

B

0.10

0.08 C

0.15

C

SEATING
PLANE

NX b

7

2X

5

INDEX
AREA

2X

6

INDEX
AREA

6

0.15

8

N

1

2

TOP VIEW

SIDE VIEW

7 8

(Nd-1)Xe

1

N

N-1

e

D

D/2

D1

D1/2

3

D2

REF.

D2/2

32

NX b

A

C

B

AC0.15

0

4X

C

E2

E2/2

BOTTOM VIEW

C

L

A1

L12.4x4A

12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A - 0.85 0.90 ­A1 0.00 0.01 0.05 ­A2 - 0.65 0.70 ­A3 0.20 REF -

b 0.18 0.23 0.30 5, 8

B

C

D 4.00 BSC ­D1 3.75 BSC ­D2 2.65 2.80 2.95 7, 8

E 4.00 BSC ­E1 3.75 BSC ­E2 1.43 1.58 1.73 7, 8

e 0.50 BSC -

k 0.635 - - ­L 0.30 0.40 0.50 8
N122

Nd 6 3

P 0.24 0.42 0.60 ­θ --12-

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

2. N is the number of terminals.

3. Nd refer to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed p ads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for
the L dimension.

NOTESMIN NOMINAL MAX

Rev. 0 8/03

CC

TERMINAL TIP

e

FOR EVEN TERMINAL/SIDE

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FN6295.3

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Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

ISL2110, ISL2111

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12

FN6295.3

April 25, 2008