intersil ISL2101A DATA SHEET

®

www.BDTIC.com/Intersil

ISL2100A, ISL2101A

Data Sheet June 8, 2006 FN6294.0

100V, 2A Peak, High Frequency
Half-Bridge Drivers

The ISL2100A, ISL2101A are 100V, high frequency,
half-bridge N-channel power MOSFET driver ICs. They are
based on the popular HIP2100, HIP2101 half-bridge drivers,
but offer several performance improvements. The ISL2100A
has additional input hysteresis for superior operation in noisy
environments and the inputs of the ISL2101A, like those of
the ISL2100A, can now safely swing to the V

supply rail.

DD

Finally, both parts are available in a very compact 9 Ld DFN
package to minimize the required PCB footprint.

Ordering Information

PART

NUMBER

(Notes 1, 2)

ISL2100AAR3Z 00AZ -40 to 125 9 Ld 3x3 DFN L9.3x3
ISL2101AAR3Z 01AZ -40 to 125 9 Ld 3x3 DFN L9.3x3

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-T” suffix for Tape and Reel packing option.

PART

MARKING

TEMP.

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

Features

• Drives N-Channel MOSFET Half-Bridge

• Space-Saving DFN Package

• DFN Package Compliant with 100V Conductor Spacing
Guidelines per IPC-2221

• Pb-Free Plus Anneal Available (RoHS Compliant)

• Bootstrap Supply Max Voltage to 114VDC

• On-Chip 1Ω Bootstrap Diode

• Fast Propagation Times for Multi-MHz Circuits

• Drives 1nF Load with Typical Rise/Fall Times of 10ns

• CMOS Compatible Input Thresholds (ISL2100A)

• 3.3V/TTL Compatible Input Thresholds (ISL2101A)

• Independent Inputs Provide Flexibility

• No Start-Up Problems

• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground or HS Slewing at High dv/dt

• Low Power Consumption

• Wide Supply Voltage Range (9V to 14V)

• Supply Undervoltage Protection

•2.5Ω Typical Output Pull-Up/Pull-Down Resistance

Applications

Pinouts

ISL2100A, ISL2101A (DFN)

TOP VIEW

V

1

DD

HB

2
3

HO
HS

4

NOTE: EPAD = Exposed PAD.

EPAD

1

LO

9

V

8

SS

LI

7
6

HI
NC

5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

• Telecom Half-Bridge Converters

• Telecom Full-Bridge Converters

• Two-S wi tch Forward Converters

• Active-Clamp Forward Converters

• Class-D Audio Amplifiers

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2006. All Rights Reserved.

Application Block Diagram

www.BDTIC.com/Intersil

ISL2100A, ISL2101A

PWM

CONTROLLER

Functional Block Diagram

V

DD

HI

HI

LI

UNDER

VOLTAGE

+12V

V

DD

CONTROL

V

DRIVE

DRIVE

ISL2100A
ISL2101A

SS

HI

LO

LEVEL SHIFT

HB

HO

HS

LO

+100V

DRIVER

REFERENCE

AND

ISOLATION

SECONDARY

CIRCUIT

HB

HO

HS

ISL2101A

UNDER

ISL2101A

LI

V

SS

VOLTAGE

DRIVER

EPAD (DFN Package Only)

*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For

best thermal performance connect the EPAD to the PCB power ground plane.

LO

2

FN6294.0

June 8, 2006

+12V

www.BDTIC.com/Intersil

ISL2100A, ISL2101A

+48V

+12V

PWM

FIGURE 1. TWO-SWITCH FORWARD CONVERTER

PWM

ISL2100A
ISL2101A

ISL2100A
ISL2101A

+48V

SECONDARY

CIRCUIT

ISOLATION

SECONDARY

CIRCUIT

ISOLATION

FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP

3

FN6294.0

June 8, 2006

ISL2100A, ISL2101A

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Absolute Maximum Ratings Thermal Information

Supply Voltage, V

LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . -0.3V to V

DD, VHB

Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . -0.3V to V

Voltage on HO (Note 4) . . . . . . . . . . . . . . V

Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V

- VHS (Notes 3, 4) . . . . . . . -0.3V to 18V

+ 0.3V

DD

+ 0.3V

- 0.3V to V

HS

DD
HB

+ 0.3V

Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V

Average Current in V

to HB Diode . . . . . . . . . . . . . . . . . . 100mA

DD

Maximum Recommended Operating Conditions

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 14V

Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V

Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V

Voltage on HB . .V

HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.

+ 8V to VHS + 14V and VDD - 1V to V

HS

NOTES:

3. The ISL2100A-01A are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating curve
for this mode of operation.

4. All voltages referenced to V

5. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. For θ

JA

the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.

unless otherwise specified.

SS

DD

+ 100V

Thermal Resistance (Typical) θ

(°C/W) θJC (°C/W)

JA

DFN (Note 5) . . . . . . . . . . . . . . . . . . . . 55 7.5

Max Power Dissipation at 25°C in Free Air (DFN, Note 5). . . . 2.27W

Storage Temperature Range . . . . . . . . . . . . . . . . . . .-65°C to 150°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . .-55°C to 150°C

Lead Temperature (Soldering 10s - SOIC Lead Tips Only). . 300°C
For Recommended soldering conditions see Tech Brief TB389.

JC,

Electrical Specifications V

DD

= V

HB

PARAMETERS SYMBOL TEST CONDITIONS

SUPPLY CURRENTS

Quiescent Current I

V

DD

Quiescent Current I

V

DD

V

Operating Current I

DD

Operating Current I

V

DD

Total HB Quiescent Current I
Total HB Operating Current I
HB to V
HB to V

Current, Quiescent I

SS

Current, Operating I

SS

INPUT PINS

Low Level Input Voltage Threshold V
Low Level Input Voltage Threshold V
High Level Input Voltage Threshold V
High Level Input Voltage Threshold V
Input Voltage Hysteresis V
Input Pull-down Resistance R

UNDER VOLTAGE PROTECTION

Rising Threshold V

V

DD

V

Threshold Hysteresis V

DD

HB Rising Threshold V
HB Threshold Hysteresis V

= 12V, V

DD

DD
DDO
DDO

HB
HBO
HBS

HBSO

IL
IL
IH
IH

IHYS

I

DDR
DDH

HBR

HBH

= V

SS

= 0V, No Load on LO or HO, Unless Otherwise Specified

HS

T

= 25°C

J

T

= -40°C to

J

125°C

UNITSMIN TYP MAX MIN MAX

ISL2100A; LI = HI = 0V - 0.1 0.25 - 0.3 mA
ISL2101A; LI = HI = 0V - 0.3 0.45 - 0.55 mA
ISL2100A; f = 500kHz - 1.6 2.2 - 2.7 mA
ISL2101A; f = 500kHz - 1.9 2.5 - 3 mA
LI = HI = 0V - 0.1 0.15 - 0.2 mA
f = 500kHz - 2.0 2.5 - 3 mA
LI = HI = 0V; VHB = VHS = 114V - 0.05 1 - 10 µA
f = 500kHz; VHB = VHS = 114V - 0.9 - - - mA

ISL2100A 3.7 4.4 - 2.7 - V
ISL2101A 1.4 1.8 - 1.2 - V
ISL2100A - 6.6 7.4 - 8.4 V
ISL2101A - 1.8 2.2 - 2.4 V
ISL2100A - 2.2 - - - V

- 210 - 100 500 kΩ

6.8 7.3 7.8 6.5 8.1 V

-0.6---V

6.2 6.9 7.5 5.9 7.8 V

-0.6---V

4

FN6294.0

June 8, 2006

ISL2100A, ISL2101A

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Electrical Specifications V

PARAMETERS SYMBOL TEST CONDITIONS

BOOT STRAP DIODE

Low Current Forward Voltage V
High Current Forward Voltage V
Dynamic Resistance R

LO GATE DRIVER

Low Level Output Voltage V
High Level Output Voltage V
Peak Pull-Up Current I
Peak Pull-Down Current I

HO GATE DRIVER

Low Level Output Voltage V
High Level Output Voltage V
Peak Pull-Up Current I
Peak Pull-Down Current I

Switching Specifications V

PARAMETERS SYMBOL

Lower Turn-Off Propagation Delay (LI Falling to LO Falling) t
Upper Turn-Off Propagation Delay (HI Falling to HO Falling) t
Lower Turn-On Propagation Delay (LI Risin g to LO Risin g) t
Upper Turn-On Propagation Delay (HI Rising to HO Rising ) t
Delay Matching: Upper Turn-Off to Lower Turn-On t
Delay Matching: Lower Turn-Off to Upper Turn-On t
Either Output Rise/Fall Time (10% to 90%/90% to 10%) t
Either Output Rise/Fall Time (3V to 9V/9V to 3V) t
Minimum Input Pulse Width that Changes the Output t
Bootstrap Diode Turn-On or Turn-Off Time t

= V

DD

DD

= 12V, V

HB

DL

DH

D

OLL

OHL
OHL

OLL

OLH

OHH
OHH
OLH

= VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified

= V

SS

I

VDD-HB

I

VDD-HB

I

VDD-HB

ILO = 100mA - 0.25 0.3 - 0.4 V
ILO = -100mA, V
VLO = 0V -2--- A
VLO = 12V - 2 - - - A

IHO = 100mA - 0.25 0.3 - 0.4 V
IHO = -100mA, V
VHO = 0V -2--- A
VHO = 12V - 2 - - - A

= 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)

HS

= 100µA - 0.5 0.6 - 0.7 V
= 100mA - 0.7 0.9 - 1 V
= 100mA - 0.8 1 - 1.5 Ω

OHL

OHH

LPHL
HPHL
LPLH
HPLH
MON

MOFF

RC,tFC

R,tF

PW

BS

T

= -40°C to

T

= 25°C

J

= V

- V

DD

LO

= V

- V

HB

HO

TEST

CONDITIONS

CL = 1nF - 10 - - - ns
CL = 0.1µF - 0.5 0.6 - 0.8 us

- 0.25 0.3 - 0.4 V

- 0.25 0.3 - 0.4 V

T

= 25°C

J

- 34 50 - 60 ns

- 31 50 - 60 ns

- 39 50 - 60 ns

- 39 50 - 60 ns
1 8 - - 16 ns
1 6 - - 16 ns

----50ns

-10- - - ns

J

125°C

= -40°C

T

J

to 125°C

UNITSMIN TYP MAX MIN MAX

UNITSMIN TYP MAX MIN MAX

5

FN6294.0

June 8, 2006

ISL2100A, ISL2101A

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Pin Descriptions

SYMBOL DESCRIPTION

V

Positive supply to lower gate driver. Bypass this pin to VSS.

DD

HB High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap

diode is on-chip.
HO High-side output. Connect to gate of high-side power MOSFET.
HS High-side source connection. Connect to source of high-side power MOSFET . Connect negative side of bootstrap capacitor to this pin.

HI High-side input.
LI Low-side input.

V

Chip negative supply, which will generally be ground.

SS

LO Low-side output. Connect to gate of low-side power MOSFET.

EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.

Timing Diagrams

LI

HI,

LI

t

,

HPLH

t

LPLH

HO,

LO

FIGURE 3. PROPAGATION DELAYS

Typical Performance Curves

10

1

IDDO (mA)

0.1
10 100 1.10

FIGURE 5. ISL2100A IDD OPERATING CURRENT vs

FREQUENCY

FREQUENCY (kHz)

T = -40C
T = 25C
T = 125C
T = 150C

t

HPHL

t

LPHL

3

HI

,

LO

HO

t

MON

t

MOFF

FIGURE 4. DELAY MATCHING

10

1

IDDO (mA)

0.1
10 100 1.10

FREQUENCY (kHz)

3

T = -40C
T = 25C
T = 125C
T = 150C

FIGURE 6. ISL2101A IDD OPERATING CURRENT vs

FREQUENCY

6

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June 8, 2006

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Typical Performance Curves (Continued)

10

1

IHBO (mA)

0.1

0.01
10 100 1.10

FREQUENCY (kHz)

T = -40C
T= 25C
T = 125C
T = 150C

3

10

1

IHBSO (mA)

0.1

0.01
10 100 1.10

FREQUENCY (kHz)

T = -40C
T = 25C
T = 125C
T = 150C

3

FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY

500
450
400
350
300
250

VOHL, VOHH (mV)

200
150

50 0 50 100 150

TEMPERATURE (C)

VDD = VHB = 9V
VDD = VHB = 12V
VDD = VHB = 14V

450

400

350

300

250

VOLL, VOLH (mV)

200

150

50 0 50 100 150

TEMPERATURE (C)

VDD = VHB = 9V
VDD = VHB = 12V
VDD = VHB = 14V

FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs

TEMPERATURE

7.6

7.4

7.2

VDDR, VHBR (V)

7

6.8
50 0 50 100 150

TEMPERATURE (C)

VDDR
VHBR

FIGURE 11. UNDERVOL T AGE LOCKOUT THRESHOLD vs

TEMPERATURE

0.6

0.55

0.5

VDDH, VHBH (V)

0.45

0.4
50 0 50 100 150

TEMPERATURE (C)

VDDH
VHBH

FIGURE 12. UNDERVOLT AGE LOCKOUT HYSTERESIS vs

TEMPERATURE

7

FN6294.0

June 8, 2006

ISL2100A, ISL2101A

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Typical Performance Curves (Continued)

55
50
45
40
35
30
25

tLPLH, tLPHL, tHPLH, tHPHL (ns)

20

50 0 50 100 150

TEMPERATURE (C)

tLPLH
tLPHL
tHPLH
tHPHL

FIGURE 13. ISL2100A PROPAGATION DELAYS vs

TEMPERATURE

10

9
8
7
6
5

tMON, tMOFF (ns)

4
3

50 0 50 100 150

TEMPERATURE (C)

tMON
tMOFF

55
50
45
40
35
30
25

tLPLH, tLPHL, tHPLH, tHPHL (ns)

20

50 0 50 100 150

TEMPERATURE (C)

tLPLH
tLPHL
tHPLH
tHPHL

FIGURE 14. ISL2101A PROPAGA TION DELAYS vs

TEMPERATURE

10

9
8
7
6
5

tMON, tMOFF (ns)

4
3
2

50 0 50 100 150

TEMPERATURE (C)

tMON
tMOFF

FIGURE 15. ISL2100A DELAY MATCHING vs TEMPERATURE FIGURE 16. ISL2101A DELAY MATCHING vs TEMPERATURE

2.5

2

1.5

1

IOHL, IOHH (A)

0.5

0

024681012

VLO, VHO (V)

2.5

2

1.5

1

IOLL, IOLH (A)

0.5

0

024681012

VLO, VHO (V)

FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT

VOLTAGE

8

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Typical Performance Curves (Continued)

260
240
220
200
180
160
140
120
100

IDD, IHB (uA)

80
60
40
20

0

0 5 10 15 20

VDD, VHB (V)

IDD
IHB

340
320
300
280
260
240
220
200
180
160
140
120

IDD, IHB (uA)

100

80
60
40
20

0

0 5 10 15 20

VDD, VHB (V)

IDD
IHB

FIGURE 19. ISL2100A QUIESCENT CURRENT vs VOLTAGE FIGURE 20. ISL2101A QUIESCENT CURRENT vs VOLTAGE

1

0.1

0.01

3

1.10

4

1.10

5

1.10

FORWARD CURRENT (A)

6

1.10

0.3 0.4 0.5 0.6 0.7 0.8
FORWARD VOLTAGE (V)

120

100

80

60

40

20

VDD to VSS VOLTAGE (V)

0

12 13 14 15 16

VHS to VSS VOLTAGE (V)

FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE

9

FN6294.0

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ISL2100A, ISL2101A

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Dual Flat No-Lead Plastic Package (DFN)

(DAT UM B )

5

INDEX
AREA

(DATUM A)

5

INDEX
AREA

SEATING

PLANE

NX L

7

A

TOP

C

SIDE VIEW

12

N

N-1

BOTTOM VIEW

D

VIEW

D2

D2/2

e
(Nd-1)Xe

REF .

2X

A3

E2/2

NX b

4

76

0.10

E

A

NX k

E2

2X

L9.3x3

ABC0.15

CB

0.15

//

M

0.10

0.08

C

C

BAC

9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

NOTESMIN NOMINAL MAX

A 0.8 0 0.90 1.00 ­A1 - - 0.05 ­A3 0.20 REF -

b 0.20 0.25 0.30 4, 7

D 3.00 BSC -

D2 1.85 2.00 2.10 6, 7

E 3.00 BSC ­E2 0.80 0.95 1.05 6, 7

e 0.50 BSC -

k0.60 - - ­L 0.25 0.35 0.45 7
N92

Rev. 0 3/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. All dimensions are in millimeters. Angles are in degrees.

4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be
either a mold or mark feature.

6. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

7. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

8. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.

C

L

NX (b)

4

SECTION "C-C"

(A1)

8

e

CC

FOR ODD TERMINAL/SIDE

TERMINAL TIP

L

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

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10

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