intersil ISL1220 DATA SHEET

ISL1220

I2C® Real Time Clock/Calendar with Frequency Output

Data Sheet June 22, 2006

Low Power RTC with 8 Bytes of Battery Backed SRAM and Separate F

The ISL1220 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, battery-backed user SRAM and separate F and IRQ

The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.

outputs.

OUT

Ordering Information

PART

NUMBER

(Note)

ISL1220IUZ 1220Z 2.7V to 5.5V -40 to +85 10 Ld MSOP ISL1220IUZ-T 1220Z 2.7V to 5.5V -40 to +85 10 Ld MSOP

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and comp atible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

RANGE

TEMP.

RANGE

(°C)

PACKAGE

(Pb-Free)

Tape and Reel

Pinout

ISL1220

(10 LD MSOP)

TOP VIEW

BAT

GND

5 6

IRQ

SCL

SDA

OUT

FN6315.0

Features

• Real Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month, and Year

• Frequency Output pin

- 15 Selectable Output Frequencies

• Single Alarm with Separate Interrupt pin

- Settable to the Second, Minute, Hour, Day of the Week, Day, or Month

- Single Event or Pulse Interrupt Mode

• Automatic Backup to Battery or Super Cap

• Power Failure Detection

• On-Chip Oscillator Compensation

• 8 Bytes Battery-Backed User SRAM

C Interface

•I

- 400kHz Data Transfer Rate

• 400nA Battery Supply Current

• Small Package Option

- 10 Ld MSOP Package

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Utility Meters

• HVAC Equipment

• Audio/Video Components

• Set Top Box/Television

• Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers/PDA

• POS Equipment

• Test Meters/Fixtures

• Office Automation (C opiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial/Medical/ Automotive

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

ISL1220

SDA

SCL

BAT

GND

Pin Descriptions

TRIP

SDA

BUFFER

SCL

BUFFER

OSCILLATOR

CRYSTAL

POR

I2C

INTERFACE

SWITCH

INTERNAL

SUPPLY

RTC

DIVIDER

FREQUENCY

OUT

CONTROL

LOGIC

ALARM

SECONDS

MINUTES

HOURS

DA Y OF WEEK

DATE

MONTH

YEAR

CONTROL

REGISTERS

USER

SRAM

IRQ

OUT

NUMBER SYMBOL DESCRIPTION

1 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz

quartz crystal. X1 ca n al s o b e d ri v e n d i r e ct l y f r o m a 32 . 7 6 8 k H z so u r c e .

2 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz

quartz crystal.

BAT

This input provides a backup supply voltage to the device. V V

supply fails. This pin should be tied to ground if not used.

supplies power to the device in the event that the

BAT

4 GND Ground. 5 NC No Connection 6F

OUT

Frequency Output (F

). Open drain output, Programmable to be active/disabled in battery back up mode.

OUT

7 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain

output and may be wire OR’ed with other open drain or open collector outputs. 8 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. 9IRQ

10 V

Interrupt Output. Open drain output, active low.

Power supply.

FN6315.0

June 22, 2006

ISL1220

Absolute Maximum Ratings Thermal Information

Voltage on VDD, V

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

, SCL, SDA, and IRQ, F

BAT

OUT

Pins

Voltage on X1 and X2 Pins

(respect to ground). . . . . . . . . . . .-0.5V to V

-0.5V to V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

+ 0.5 (VDD Mode)

+ 0.5 (V

BAT

Mode)

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

ESD Rating (Human Body Model). . . . . . . . . . . . . . . . . . . . . . .>2kV

ESD Rating (Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . .>175V

Output Current Sink (F

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

, IRQ . . . . . . . . . . . . . . . . . . . . . . . . 3mA

OUT

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

DC Operating Characteristics – RTC Temperature = -40°C to +85°C, unless otherwise stated.

SYMBOL PARAMETER CONDITIONS MIN

Main Power Supply 2.7 5.5 V Battery Supply Voltage 1.8 5.5 V Supply Current VDD = 5V 2 6 µA 2, 3

= 3V 1.2 4 µA

Supply Current with I2C Active VDD = 5V 40 120 µA 2, 3 Supply Current (Low Power Mode) VDD = 5V, LPMODE = 1 1.4 5 µA 2, 7 Battery Supply Current V

= 3V 400 950 nA 2

BAT

Battery Input Leakage VDD = 5.5V, V Input Leakage Current on SCL 100 nA I/O Leakage Current on SDA 100 nA V

Mode Threshold 1.6 2.2 2.64 V

BAT

Hysteresis 10 35 60 mV

TRIP

Hysteresis 10 50 100 mV

BAT

Output Low Voltage VDD = 5V, IOL = 3mA 0.4 V

= 2.7V, IOL = 1mA 0.4 V

Output Leakage Current VDD = 5.5V

= 5.5V

OUT

IRQ, F

BAT

DD1

DD2

DD3

BAT

BATLKG

TRIP

TRIPHYS

BATHYS

OUT

Thermal Resistance (Typical, Note 1)

10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . 120

Moisture Sensitivity (see Technical Brief TB363). . . . . . . . . . Level 2

Maximum Junction Temperature (Plastic Package). . . . . . . . .150°C

Recommended Operating Conditions

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V

BAT

TYP

(Note 5) MAX UNITS NOTES

= 1.8V 100 nA

BAT

100 400 nA

(°C/W)

Power-Down Timing Temperature = -40°C to +85°C, unless otherwise stated.

TYP

SYMBOL PARAMETER CONDITIONS MIN

DD SR-

VDD Negative Slewrate 10 V/ms 4

(Note 5) MAX UNITS NOTES

Serial Interface Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

SERIAL INTERFACE SPECS

SDA and SCL Input Buffer LOW

Voltage

(Note 5) MAX UNITS NOTES

-0.3 0.3 x

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June 22, 2006

ISL1220

Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

Hysteresis SDA and SCL Input Buffer

SDA and SCL Input Buffer HIGH

Voltage

0.7 x

0.05 x

Hysteresis

Cpin SDA and SCL Pin Capacitance T

SCL

BUF

SDA Output Buffer LOW Voltage,

Sinking 3mA

= 25°C, f = 1MHz, VDD = 5V, VIN=0V,

= 0V

OUT

SCL Frequency 400 kHz Pulse Width Suppression Time at

SDA and SCL Inputs SCL Falling Edge to SDA Output

Data Valid Time the Bus Must be Free before

the Start of a New Transmission

Any pulse narrower than the max spec is suppressed.

SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of V

window.

SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of V

1300 ns

during the following START condition.

LOW

HIGH

SU:STA

HD:STA

SU:DAT

HD:DAT

Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns START Condition Setup Time SCL rising edge to SDA falling edge. Both

crossing 70% of V

STAR T Condition Hold Time From SDA falling edge crossing 30% of VDD

to SCL falling edge crossing 70% of V

Input Data Setup Time From SDA exiting the 30% to 70% of VDD

window, to SCL rising edge crossing 30% of V

Input Data Hold Time From SCL falling edge crossing 30% of VDD

to SDA entering the 30% to 70% of V

window.

SU:STO

HD:STO

STOP Condition Setup Time From SCL rising edge crossing 70% of VDD,

to SDA rising edge crossing 30% of V

STOP condItion Hold Time From SDA rising edge to SCL falling edge.

Both crossing 70% of V

Output Data Hold T ime From SCL falling edge crossing 30% of VDD,

until SDA enters the 30% to 70% of V window.

SDA and SCL Rise Time From 30% to 70% of V

0.1 x Cb

SDA and SCL Fall Time From 70% to 30% of V

0.1 x Cb

Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 6

Rpu SDA and SCL Bus Pull-up Resistor

Off-chip

Maximum is determined by t For Cb = 400pF, max is about 2~2.5kΩ.

and tF.

For Cb = 40pF, max is about 15~20kΩ

NOTES:

2. IRQ

and F

OUT

Inactive.

3. LPMODE = 0 (default).

4. In order to ensure proper timekeeping, the V

specification must be followed.

DD SR-

5. Typical values are for T = 25°C and 3.3V supply voltage.

6. These are I

7. A write to register 08h should only be done if V

C specific parameters and are not directly tested, however they are used during device testing to validate device specification.

> V

, otherwise the device will be unable to communicate using I2C.

BAT

(Note 5) MAX UNITS NOTES

0.3

VDD +

00.4V

10 pF

50 ns

900 ns

600 ns

100 ns

0 900 ns

600 ns

0ns

20 +

300 ns 6

1kΩ 6

FN6315.0

June 22, 2006

SDA vs SCL Timing

ISL1220

SCL

(INPUT TIMING)

(OUTPUT TIMING)

SDA

SU:STA

HD:STA

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be steady Will be steady

May change from LOW to HIGH

May change from HIGH to LOW

Will change from LOW to HIGH

Will change from HIGH to LOW

SU:DAT

HIGH

LOW

HD:DAT

SU:STO

BUF

Don’t Care: Changes Allowed

N/A Center Line is

Changing: State Not Known

High Impedance

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June 22, 2006

ISL1220

Typical Performance Curves Temperature is +25°C unless otherwise specified

900E-9 800E-9 700E-9 600E-9 500E-9

BAT (A)

400E-9 300E-9 200E-9 100E-9

000E+0

2.4E-06

2.2E-06

2.0E-06

1.8E-06

(A)

1.6E-06

DD1

1.4E-06

1.2E-06

1.0E-06

1E-6

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 (V)

BAT

FIGURE 1. I

-40-200 20406080 TEMPERATURE (°C)

FIGURE 3. I

DD1

vs V

BAT

VCC= 5V

VCC= 3.3V

BAT

vs TEMPERATURE FIGURE 4. I

1E-6

800E-9

600E-9

BAT (A)

400E-9

200E-9

000E+0

FIGURE 2. I

2.4E-6

2.2E-6

2.0E-6

1.8E-6

1.6E-6

(A)

1.4E-6

DD1

1.2E-6

1.0E-6

800.0E-9

600.0E-9

400.0E-9

-40-200 20406080 TEMPERATURE (°C)

vs TEMPERATURE AT V

BAT

LPMODE = 0

LPMODE = 1

2.53.03.54.04.55.05.5 V

CC (V)

vs VCC WITH LPMODE ON AND OFF

DD1

BAT

= 3V

(A)

DD1

2.1E-6

2.0E-6

1.9E-6

1.8E-6

1.7E-6

1.6E-6

1.5E-6

1.4E-6

1.3E-6

1.2E-6 1/32

1/16

FIGURE 5. I

3.0E-6

2.9E-6

2.8E-6

2.7E-6

2.6E-6

2.5E-6

(A)

2.4E-6

DD1

2.3E-6

2.2E-6

2.1E-6

2.0E-6

1.9E-6

1/2

1/4

1/8

OUT (Hz)

DD1

vs F

OUT

AT V

= 3.3V FIGURE 6. I

1024

4096

32768

1.8E-6 1

1/16

DD1

OUT (Hz)

vs F

OUT

1/2

1/4

1/8

1/32

AT VDD = 5V

4096

1024

June 22, 2006

32768

FN6315.0

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