intersil ISL1219 DATA SHEET

ISL1219

Real Time Clock/Calendar with Event Detection

Data Sheet August 14, 2006

Low Power RTC with Battery Backed SRAM and Event Detection

The ISL1219 device is a low power real time clock with Event Detect and Time Stamp function, timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching and 2 Bytes of battery-backed user SRAM.

The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.

Ordering Information

PART

NUMBER

(See Note)

ISL1219IUZ 1219Z 2.7V to 5.5V -40 to +85 10 Ld MSOP ISL1219IUZ-T 1219Z 2.7V to 5.5V -40 to +85 10 Ld MSOP

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

RANGE

TEMP

RANGE

(°C)

PACKAGE

(Pb-Free)

Tape and Reel

Pinout

ISL1219

(10 LD MSOP)

TOP VIEW

BAT

GND

EVIN

5 6

IRQ/F

SCL

SDA

EVDET

OUT

FN6314.1

Features

• Real Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month, and Year

• Security and Event Functions

- Tamper detection with Time Stamp in Normal and Battery Backed modes

- Event Detection During Battery Backed or Normal Modes

- Selectable Event Input Sampling Rates Allows Low Power Operation

- Selectable Glitch Filter on Event Input Monitor

• 15 Selectable Frequency Outputs

• Single Alarm

- Settable to the Second, Minute, Hour, Day of the Week, Day, or Month

- Single Event or Pulse Interrupt Mode

• Automatic Backup to Battery or Super Cap

• Power Failure Detection

• On-Chip Oscillator Compensation

• 2 Bytes Battery-Backed User SRAM

C Interface

•I

- 400kHz Data Transfer Rate

• 400nA Battery Supply Current

• Small Package

-10 Ld MSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Utility Meters

• Set Top Box/Modem

• POS Equipment

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Test Meters/Fixtures

• Vending Machine Management

• Security and Anti Tampering Applications

- Panel/Enclosure Status

- Warranty Reporting

- Time Stamping Applications

- Patrol/Security Check (Fire or Light Equipment)

- Automotive Applications

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

ISL1219

SDA

SCL

BAT

EVIN

GND

TRIP

SDA

BUFFER

SCL

BUFFER

CRYSTAL

OSCILLATOR

POR

I2C

INTERFACE

SWITCH

INTERNAL

SUPPLY

RTC

DIVIDER

FREQUENCY

OUT

CONTROL

LOGIC

ALARM

SECONDS

MINUTES

HOURS

DA Y OF WEEK

DATE

MONTH

YEAR

CONTROL

REGISTERS

USER

SRAM

IRQ/

OUT

EVDET

Pin Descriptions

NUMBER SYMBOL DESCRIPTION

1X1X1. The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external

32.768kHz quartz crystal. X1 can a l s o be d r i v e n di r e c t l y from a 32 . 7 6 8 k H z so u r c e .

2X2X2. The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external

32.768kHz quartz crystal. X2 should be left open when X1 is driven from external source.

BAT

4GNDGround. 5EVINEvent Input (EVIN). The EVIN is an input pin that is used to detect an externally monitored event. When a high signal

6 EVDET 7SDASerial Data (SDA). SDA is a bidirectional pin used to transfer serial data into and out of the device. It has an open

8SCLSerial Clock (SCL). The SCL input is used to clock all serial data into and out of the device. 9IRQ

10 V

This input provides a backup supply voltage to the device. V

BAT.

the V

supply fails. This pin should be tied to ground if not used.

BAT

is present at the EVIN pin an “event” is detected. Event Detect Output, active when EVIN is triggered. Open drain output.

drain output and may be wire OR’ed with other open drain or open collector outputs.

Interrupt Output IRQ, /Frequency Output F

OUT

output pin. The function is set via the configuration register.

Power supply.

DD.

Multi-functional pin that can be used as interrupt or frequency

OUT.

supplies power to the device in the event that

FN6314.1

August 14, 2006

ISL1219

Absolute Maximum Ratings Thermal Information

Voltage on VDD, V

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

, SCL, SDA, and IRQ/F

BAT

OUT

Pins

Voltage on X1 and X2 Pins

(respect to ground). . . . . . . . . . . .-0.5V to V

-0.5V to V

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

+ 0.5 (VDD Mode)

+ 0.5 (V

BAT

Mode)

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

ESD Rating (Human Body Model). . . . . . . . . . . . . . . . . . . . . . .>2kV

ESD Rating (Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . .>175V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

Thermal Resistance (Typical, Note 1)

(°C/W)

10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . 120

Moisture Sensitivity (see Technical Brief TB363). . . . . . . . . . Level 2

DC Operating Characteristics – RTC Test Conditions: V

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.

SYMBOL PARAMETER CONDITIONS MIN

BAT

DD1

DD2

DD3

BAT

BATLKG

TRIP

TRIPHYS

BATHYS

Main Power Supply 2.7 5.5 V Battery Supply Voltage 1.8 5.5 V Supply Current VDD = 5V 2 6 µA 2, 3

= 3V 1.2 4 µA

Supply Current With I2C Active VDD = 5V 40 120 µA 2, 3 Supply Current (Low Power Mode) VDD = 5V, LPMODE = 1 1.4 5 µA 2, 8 Battery Supply Current V Battery Input Leakage VDD = 5.5V, V

= 3V 400 950 nA 2

BAT

= 1.8V 100 nA

BAT

Input Leakage Current on SCL 100 nA I/O Leakage Current on SDA 100 nA V

Mode Threshold 1.6 2.2 2.64 V

BAT

Hysteresis 10 35 60 mV

TRIP

Hysteresis 10 50 100 mV

BAT

EVIN

-0.3 0.3 x

0.7 x V

Hysteresis 0.05 x

EVPU

IRQ

OUT

EVIN Pull-up Current V

= 3V 1.5 µA 6

SUP

and EVDET

Output Low Voltage VDD = 5V, IOL = 3mA 0.4 V

= 2.7V, IOL = 1mA 0.4 V

Output Leakage Current VDD = 5.5V

= 5.5V

OUT

TYP

(Note 5) MAX UNITS NOTES

VDD +

0.3 V

100 400 nA

FN6314.1

August 14, 2006

ISL1219

Power-Down Timing Test Conditions: V

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.

SYMBOL PARAMETER CONDITIONS MIN

DD SR-

I2C Interface Specifications Test Conditions: V

VDD Negative Slew Rate 10 V/ms 4

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

SDA and SCL Input Buffer LOW Voltage

SDA and SCL Input Buffer HIGH Voltage

-0.3 0.3 x

0.7 x V

Hysteresis SDA and SCL Input Buffer Hysteresis 0.05 x

Cpin SDA and SCL Pin Capacitance T

SCL

SDA Output Buffer LOW Voltage,

VDD = 5V, IOL = 3mA 0.4 V

Sinking 3mA

= 25°C, f = 1MHz, VDD=5V,

=0V, V

OUT

=0V SCL Frequency 400 kHz Pulse Width Suppression Time at

SDA and SCL Inputs SCL Falling Edge to SDA Output Data

Valid

Any pulse narrower than the max spec is suppressed.

SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of V

window.

BUF

LOW

HIGH

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

HD:STO

Time the Bus Must be Free before the Start of a New Transmission

SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of V

during the following START

condition. Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns START Condition Setup Time SCL rising edge to SDA falling edge.

Both crossing 70% of V

START Condition Hold Time From SDA falling edge crossing 30%

of V

to SCL falling edge crossing

70% of V

Input Data Setup Time From SDA exiting the 30% to 70% of

window, to SCL rising edge

crossing 30% of V

DD.

Input Data Hold Time From SCL falling edge crossing 30%

of V

to SDA entering the 30% to

70% of V

window.

STOP Condition Setup Time From SCL rising edge crossing 70% of

, to SDA rising edge crossing 30%

of V

STOP Condition Hold Time From SDA rising edge to SCL falling

edge. Both crossing 70% of V

Output Data Hold Time From SCL falling edge crossing 30%

of V

, until SDA enters the 30% to

70% of V SDA and SCL Rise Time From 30% to 70% of V

window.

DD.

1300 ns

600 ns

100 ns

0 900 ns

600 ns

0ns

20 +

0.1 x Cb

TYP

(Note 5) MAX UNITS NOTES

TYP

(Note 4) MAX UNITS NOTES

VDD +

0.3 V

10 pF

50 ns

900 ns

300 ns 7

FN6314.1

August 14, 2006

ISL1219

I2C Interface Specifications Test Conditions: V

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

SDA and SCL Fall Time From 70% to 30% of V

DD.

20 +

(Note 4) MAX UNITS NOTES

300 ns 7

0.1 x Cb Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 7 Rpu SDA and SCL Bus Pull-up Resistor

Off-chip

Maximum is determined by t For Cb = 400pF, max is about

and tF.

1kΩ 7

2~2.5kΩ. For Cb = 40pF, max is about 15~20kΩ

NOTES:

2. IRQ

and F

and EVDET Inactive.

OUT

3. LPMODE = 0 (default).

4. In order to ensure proper timekeeping, the V

specification must be followed.

DD SR-

5. Typical values are for T = 25°C and 3.3V supply voltage.

6. V

7. These are I

= VDD if in V

SUP

C specific parameters and are not directly tested, however they are used during device testing to validate device specification.

8. A write to register 08h should only be done if V

Mode, V

SUP

= V

BAT

if in V

Mode.

BAT

> V

, otherwise the device will be unable to communicate using I2C.

BAT

SDA vs. SCL Timing

HIGH

LOW

SCL

(INPUT TIMING)

(OUTPUT TIMING)

SDA

SU:STA

HD:STA

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be steady Will be steady

May change from LOW to HIGH

May change from HIGH to LOW

Don’t Care: Changes Allowed

N/A Center Line is

SU:DAT

Will change from LOW to HIGH

Will change from HIGH to LOW

Changing: State Not Known

High Impedance

HD:DAT

SU:STO

BUF

FN6314.1

August 14, 2006

ISL1219

VDD

Typical Performance Curves Temperature is +25°C unless otherwise specified

900E-9 800E-9 700E-9 600E-9

(A)

500E-9

BAT

400E-9 300E-9 200E-9 100E-9

000E+0

2.4E-06

2.2E-06

2.0E-06

1.8E-06

(A)

1.6E-06

DD1

1.4E-06

1.2E-06

1.0E-06

1E-6

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 (V)

BAT

FIGURE 1. I

-40-200 20406080 TEMPERATURE (°C)

FIGURE 3. I

DD1

vs V

BAT

VDD= 5V

VDD= 3.3V

BAT

vs TEMPERATURE FIGURE 4. I

1E-6

800E-9

600E-9

(A)

BAT

400E-9

200E-9

000E+0

FIGURE 2. I

2.4E-6

2.2E-6

2.0E-6

1.8E-6

1.6E-6

(A)

1.4E-6

DD1

1.2E-6

1.0E-6

800.0E-9

600.0E-9

400.0E-9

-40-200 20406080 TEMPERATURE (°C)

vs TEMPERATURE AT V

BAT

LPMODE = 0

LPMODE = 1

2.53.03.54.04.55.05.5 V

(V)

vs VDD WITH LPMODE ON AND OFF

DD1

BAT

= 3V

(A)

DD1

2.1E-6

2.0E-6

1.9E-6

1.8E-6

1.7E-6

1.6E-6

1.5E-6

1.4E-6

1.3E-6

1.2E-6 1/8

1/32

1/16

FIGURE 5. I

1/4

DD1

1/2

OUT (Hz)

vs F

OUT

AT V

3.0E-6

2.9E-6

2.8E-6

2.7E-6

2.6E-6

2.5E-6

(A)

2.4E-6

DD1

2.3E-6

2.2E-6

2.1E-6

2.0E-6

1.9E-6

4096

1024

32768

= 3.3V FIGURE 6. I

1.8E-6 1

1/16

DD1

OUT (Hz)

vs F

OUT

1/2

1/4

1/8

1/32

AT VDD = 5V

4096

1024

32768

FN6314.1

August 14, 2006

ISL1219

Typical Performance Curves Temperature is +25°C unless otherwise specified (Continued)

8.00E-06

7.00E-06

6.00E-06

5.00E-06

4.00E-06

PULLUP

3.00E-06

2.00E-06

1.00E-06

0.00E+00

2.533.544.555.56

FIGURE 7. EVIN I

EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V

SDA

AND

/FOUT

IRQ

FIGURE 9. STANDARD OUTPUT LOAD FOR TESTING THE

DEVICE WITH V

5.0V

PULL-UP

1533Ω

100pF

= 5.0V

-40°C

vs V

FOR VOL= 0.4V AND I

+25°C

+85°C

= 3mA

= 5V

5.0E-07

4.0E-07

3.0E-07

PULLUP

2.0E-07

1.0E-07

-40 -25 -10 5 20 35 50 65 80

Temperature

FIGURE 8. I

PULL-UP

vs TEMPERATURE AT V

BAT

= 1.8V

hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.

The ISL1219's alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc.

General Description

The ISL1219 device is a low power Real Time Clock with Security and Event function, Time Stamp in both normal and battery modes, timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, and battery-backed user SRAM.

The Event Detection function can be used for tamper detection, security or other chassis or generic system monitoring. Upon a valid event detection, the ISL1219 sets the Event Detection bit (EVT bit) in the status register, stores time stamp information on on board memory, and, can optionally: 1) Issue an Event Output signal (EVDET pin), 2) At the time the event occurred, stop the RTC registers from advancing. The event monitor and time stamp functions in both main V monitor can also be configured for various input detection rates to optimize power consumption for the application. In addition, the Event Monitor pin (EVIN) has a selectable glitch filter to avoid switch de-bouncing.

The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for

and battery back up modes. The event

The device also offers a backup power input pin. This V

BAT

pin allows the device to be backed up by battery or SuperCap with automatic switchover from V entire ISL1219 device is fully operational from V

to V

. The

BAT

=2.7V to

5.5V and the clock/calendar portion of the device remains fully operational in battery backup mode down to 1.8V (Standby Mode).

Pin Description

X1, X2

The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL1219 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from

-40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. The device can also be driven directly from a

32.768kHz source at pin X1.

FN6314.1

August 14, 2006

X1 X2

FIGURE 10. RECOMMENDED CRYSTAL CONNECTION

BAT

This input provides a backup supply voltage to the device. V

supplies power to the device in the event that the VDD

BAT

supply fails. This pin can be connected to a battery, a Super Cap or tied to ground if not used.

EVIN (Event Input)

The EVIN pin is an input that is used to detect an externally monitored event. When a high signal is present at the EVIN pin, an “event” is detected. This input may be used for various monitoring functions, such as the opening of a detection switch on a chassis or door. The event detection circuit can be user enabled or disabled (see EVEN bit) and provides the option to be operational in battery backup modes (see EVBATB bit). When the event detection is disabled the EVIN pin is gated OFF. See functional Description for more details.

EVDET (Event Detect Output)

The EVDET is an open drain output which will go low when an event is detected at the EVIN pin. If the event detection function is enabled, the EVDET

output will go low and stay

low until the EVT bit is cleared (see EVIN pin description).

IRQ/F

(Interrupt Output/Frequency Output)

OUT

This dual function pin can be used as an interrupt or frequency output pin. The IRQ

mode is selected via

OUT

the frequency out control bits of the control/status register.

• Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output.

• Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I

C bus. It is

an open drain active low output.

Serial Clock (SCL)

The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the V

pin is activated to minimize power consumption.

BAT

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode.

ISL1219

An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I when the backup power supply on the V

C interface speeds. It is disabled

pin is activated.

BAT

VDD, GND

Chip power supply and ground pins. The device will operate with a power supply from V capacitor is recommended on the V

= 2.7V to 5.5VDC. A 0.1µF

pin to ground.

Functional Description

Power Control Operation

The power control circuit accepts a VDD and a V Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL1219 for up to 10 years. Another option is to use a Super Cap for applications where V

is interrupted for up

to a month. See the Applications Section for more information.

Normal Mode (VDD) to Battery Backup Mode (V

)

BAT

To transition from the VDD to V following conditions must be met:

Condition 1:

< V

where V

- V

BAT

BATHYS

≈ 50mV

Condition 2:

VDD < V where V

TRIP

≈ 2.2V

Battery Backup Mode (V (V

)

The ISL1219 device will switch from the V when one

Condition 1:

Condition 2:

of the following conditions occurs:

> V

where V

VDD > V where V

+ V

BAT

BATHYS

+ V

TRIP

TRIPHYS

BATHYS

≈ 50mV

TRIPHYS

≈ 30mV

mode, both of the

BAT

) to Normal Mode

BAT

input.

BAT

to VDD mode

FN6314.1

August 14, 2006

+ 17 hidden pages