intersil ISL1218 DATA SHEET

ISL1218

I2C® Real Time Clock/Calendar

Data Sheet June 22, 2006

Low Power RTC with Battery Backed SRAM

The ISL1218 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching and battery-backed user SRAM.

The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.

Ordering Information

PART

NUMBER

(Note)

ISL1218IBZ 1218IBZ 2.7V to

ISL1218IBZ-T 1218IBZ 2.7V to

ISL1218IUZ 1218Z 2.7V to

ISL1218IUZ-T 1218Z 2.7V to

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

RANGE

5.5V

TEMP.

RANGE

(°C)

-40 to +85 8 Ld SOIC

-40 to +85 8 Ld MSOP

PACKAGE

Tape and Reel

(Pb-Free)

Pinout

ISL1218

(8 LD MSOP, SOIC)

TOP VIEW

IRQ/F

OUT

SCL

SDA

BAT

GND

X1 X2

1 2

3 4

FN6313.0

Features

• Real Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month, and Year

• 15 Selectable Frequency Outputs

• Single Alarm

- Settable to the Second, Minute, Hour, Day of the Week, Day, or Month

- Single Event or Pulse Interrupt Mode

• Automatic Backup to Battery or Super Cap

• Power Failure Detection

• On-Chip Oscillator Compensation

• 8 Bytes Battery-Backed User SRAM

C Interface

•I

- 400kHz Data Transfer Rate

• 400nA Battery Supply Current

• Same Pin Out as ST M41Txx and Maxim DS13xx Devices

• Small Package Options

- 8 Ld MSOP and SOIC Packages

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Utility Meters

• HVAC Equipment

• Audio/Video Components

• Set Top Box/Television

• Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers/PDA

• POS Equipment

• Test Meters/Fixtures

• Office Automation (Copiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial/Medical/ Automotive

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

ISL1218

TRIP

SDA

BUFFER

SCL

BUFFER

CRYSTAL

OSCILLATOR

POR

I2C

INTERFACE

SWITCH

INTERNAL

SUPPLY

RTC

DIVIDER

FREQUENCY

OUT

RTC

CONTROL

LOGIC

ALARM

SECONDS

MINUTES

HOURS

DA Y OF WEEK

DATE

MONTH

YEAR

CONTROL

REGISTERS

USER

SRAM

IRQ/

OUT

SDA

SCL

BAT

Pin Descriptions

NUMBER SYMBOL DESCRIPTION

1 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz

quartz crystal. X1 ca n al s o b e d ri v e n d i r e ct l y f r o m a 32 . 7 6 8 k H z so u r c e .

2 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz

quartz crystal.

BAT

4 GND Ground. 5 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain

6 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. 7IRQ

This input provides a backup supply voltage to the device. V V

supply fails. This pin should be tied to ground if not used.

supplies power to the device in the event that the

BAT

output and may be wire OR’ed with other open drain or open collector outputs.

Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The

OUT

function is set via the configuration register. Power supply.

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June 22, 2006

ISL1218

Absolute Maximum Ratings Thermal Information

Voltage on VDD, V

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

, SCL, SDA, and IRQ/F

BAT

OUT

Pins

Voltage on X1 and X2 Pins

(respect to ground). . . . . . . . . . . .-0.5V to V

-0.5V to V

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

+ 0.5 (VDD Mode)

+ 0.5 (V

BAT

Mode)

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

ESD Rating (Human Body Model). . . . . . . . . . . . . . . . . . . . . . .>2kV

ESD Rating (Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . .>175V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

DC Operating Characteristics – RTC Temperature = -40°C to +85°C, unless otherwise stated.

SYMBOL PARAMETER CONDITIONS MIN

BAT

DD1

DD2

DD3

BAT

BATLKG

TRIP

TRIPHYS

BATHYS

IRQ

OUT

Main Power Supply 2.7 5.5 V Battery Supply Voltage 1.8 5.5 V Supply Current VDD = 5V 2 6 µA 2, 3

= 3V 1.2 4 µA

Supply Current With I2C Active VDD = 5V 40 120 µA 2, 3 Supply Current (Low Power Mode) VDD = 5V, LPMODE = 1 1.4 5 µA 2, 7 Battery Supply Current V

= 3V 400 950 nA 2

BAT

Battery Input Leakage VDD = 5.5V, V Input Leakage Current on SCL 100 nA I/O Leakage Current on SDA 100 nA V

Mode Threshold 1.6 2.2 2.64 V

BAT

Hysteresis 10 35 60 mV

TRIP

Hysteresis 10 50 100 mV

BAT

Output Low Voltage VDD = 5V, IOL = 3mA 0.4 V

= 2.7V, IOL = 1mA 0.4 V

Output Leakage Current VDD = 5.5V

= 5.5V

OUT

Thermal Resistance (Typical, Note 1)

8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 130

8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 110

Moisture Sensitivity for MSOP Package

(see Technical Brief TB363). . . . . . . . . . . . . . . . . . . . . . . . Level 2

Moisture Sensitivity for SOIC Package

(see Technical Brief TB363). . . . . . . . . . . . . . . . . . . . . . . . Level 1

Maximum Junction Temperature (Plastic Package). . . . . . . . . 150°C

TYP

(Note 5) MAX UNITS NOTES

= 1.8V 100 nA

BAT

100 400 nA

(°C/W)

Power-Down Timing Temperature = -40°C to +85°C, unless otherwise stated.

TYP

SYMBOL PARAMETER CONDITIONS MIN

DD SR-

VDD Negative Slewrate 10 V/ms 4

(Note 5) MAX UNITS NOTES

Serial Interface Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

SERIAL INTERFACE SPECS

SDA and SCL Input Buffer LOW Voltage

SDA and SCL Input Buffer HIGH Voltage

0.7 x V

(Note 5) MAX UNITS NOTES

-0.3 0.3 x

VDD +

0.3

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June 22, 2006

ISL1218

Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

Hysteresis SDA and SCL Input Buffer Hysteresis 0.05 x

SDA Output Buffer LOW Voltage, Sinking 3mA

Cpin SDA and SCL Pin Capacitance T

SCL

SCL Frequency 400 kHz Pulse Width Suppression Time at SDA

and SCL Inputs SCL Falling Edge to SDA Output Data

Valid

= 25°C, f = 1MHz, VDD = 5V,

=0V, V

OUT

= 0V

Any pulse narrower than the max spec is suppressed.

SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of V

window.

BUF

LOW

HIGH

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

HD:STO

Time the Bus Must be Free before the Start of a New Transmission

SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of V

during the following START

condition. Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns START Condition Setup Time SCL rising edge to SDA falling edge.

Both crossing 70% of V

STAR T Condition Hold Time From SDA falling edge crossing 30% of

to SCL falling edge crossing 70%

of V

Input daTa Setup Time From SDA exiting the 30% to 70% of

window, to SCL rising edge

crossing 30% of V

Input Data Hold Time From SCL falling edge crossing 30% of

to SDA entering the 30% to 70%

of V

window.

STOP Condition Setup Time From SCL rising edge crossing 70% of

, to SDA rising edge crossing 30%

of V

STOP Condition Hold Time From SDA rising edge to SCL falling

edge. Both crossing 70% of V

Output Data Hold Time From SCL falling edge crossing 30% of

, until SDA enters the 30% to 70%

of V

window.

SDA and SCL Rise Time From 30% to 70% of V

SDA and SCL Fall Time From 70% to 30% of V

1300 ns

20 +

0.1 x Cb 20 +

0.1 x Cb

Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 6 Rpu SDA and SCL Bus Pull-up Resistor

Off-chip

Maximum is determined by t For Cb = 400pF , max is about 2~2.5kΩ.

and tF.

For Cb = 40pF, max is about 15~20kΩ

NOTES:

2. IRQ

and F

OUT

Inactive.

3. LPMODE = 0 (default).

4. In order to ensure proper timekeeping, the V

specification must be followed.

DD SR-

5. Typical values are for T = 25°C and 3.3V supply voltage.

6. These are I

7. A write to register 08h should only be done if V

C specific parameters and are not directly tested, however they are used during device testing to validate device specification.

> V

, otherwise the device will be unable to communicate using I2C.

BAT

(Note 5) MAX UNITS NOTES

00.4V

10 pF

50 ns

900 ns

600 ns

100 ns

0 900 ns

600 ns

0ns

300 ns 6

1kΩ 6

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June 22, 2006

SDA vs SCL Timing

ISL1218

SCL

(INPUT TIMING)

(OUTPUT TIMING)

SDA

SU:STA

HD:STA

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be steady Will be steady

May change from LOW to HIGH

May change from HIGH to LOW

Will change from LOW to HIGH

Will change from HIGH to LOW

SU:DAT

HIGH

LOW

HD:DAT

SU:STO

BUF

Don’t Care: Changes Allowed

N/A Center Line is

Changing: State Not Known

High Impedance

FN6313.0

June 22, 2006

ISL1218

Typical Performance Curves Temperature is +25°C unless otherwise specified

900E-9 800E-9 700E-9 600E-9

(A)

500E-9

BAT

400E-9 300E-9 200E-9 100E-9

000E+0

2.4E-06

2.2E-06

2.0E-06

1.8E-06

(A)

1.6E-06

DD1

1.4E-06

1.2E-06

1.0E-06

1E-6

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 (V)

BAT

FIGURE 1. I

-40-200 20406080 TEMPERATURE (°C)

FIGURE 3. I

DD1

vs V

BAT

VCC= 5V

VCC= 3.3V

BAT

vs TEMPERATURE FIGURE 4. I

1E-6

800E-9

600E-9

(A)

BAT

400E-9

200E-9

000E+0

FIGURE 2. I

2.4E-6

2.2E-6

2.0E-6

1.8E-6

1.6E-6

(A)

1.4E-6

DD1

1.2E-6

1.0E-6

800.0E-9

600.0E-9

400.0E-9

-40-200 20406080 TEMPERATURE (°C)

vs TEMPERATURE AT V

BAT

LPMODE = 0

LPMODE = 1

2.53.03.54.04.55.05.5 V

CC (V)

vs VCC WITH LPMODE ON AND OFF

DD1

BAT

= 3V

(A)

DD1

2.1E-6

2.0E-6

1.9E-6

1.8E-6

1.7E-6

1.6E-6

1.5E-6

1.4E-6

1.3E-6

1.2E-6 1/8

1/32

1/16

FIGURE 5. I

1/4

DD1

1/2

OUT (Hz)

vs F

OUT

AT V

3.0E-6

2.9E-6

2.8E-6

2.7E-6

2.6E-6

2.5E-6

(A)

2.4E-6

DD1

2.3E-6

2.2E-6

2.1E-6

2.0E-6

1.9E-6

4096

1024

32768

= 3.3V FIGURE 6. I

1.8E-6 1

1/16

DD1

OUT (Hz)

vs F

OUT

1/2

1/4

1/8

1/32

AT VDD = 5V

4096

1024

June 22, 2006

32768

FN6313.0

ISL1218

EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V

5.0V

1533Ω

SDA AND

IRQ

/FOUT

FIGURE 7. STANDARD OUTPUT LOAD FOR TESTING THE

DEVICE WITH V

100pF

= 5.0V

FOR VOL= 0.4V AND I

= 5V

= 3mA

General Description

The ISL1218's powerful alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc.

The device also offers a backup power input pin. This V

BAT

pin allows the device to be backed up by battery or SuperCap with automatic switchover from V

to V

BAT

. The entire ISL1218 device is fully operational from 2.0V to 5.5V and the clock/calendar portion of the device remains fully operational down to 1.8V (Standby Mode).

Pin Description

X1, X2

The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL1218 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from

-40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. The device can also be driven directly from a

32.768kHz source at pin X1.

X1 X2

FIGURE 8. RECOMMENDED CRYSTAL CONNECTION

BAT

This input provides a backup supply voltage to the device. V

supplies power to the device in the event that the VDD

BAT

supply fails. This pin can be connected to a battery, a Super Cap or tied to ground if not used.

IRQ/F

(Interrupt Output/Frequency Output)

OUT

This dual function pin can be used as an interrupt or frequency output pin. The IRQ

mode is selected via

OUT

the frequency out control bits of the control/status register.

• Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output.

• Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I

C bus. It is

an open drain active low output.

Serial Clock (SCL)

The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the V

pin is activated to minimize power consumption.

BAT

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode.

An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I when the backup power supply on the V

C interface speeds. It is disabled

pin is activated.

BAT

VDD, GND

Chip power supply and ground pins. The device will operate with a power supply from 2.0V to 5.5VDC. A 0.1µF capacitor is recommended on the V

pin to ground.

Functional Description

Power Control Operation

The power control circuit accepts a VDD and a V Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power

BAT

input.

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June 22, 2006

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