intersil ISL1209 DATA SHEET

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ISL1209

Real Time Clock/Calendar with Event Detection

Data Sheet September 27, 2005

Low Power RTC with Battery Backed SRAM and Event Detection

The ISL1209 device is a low power real time clock with Event Detect function, timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching and battery-backed user SRAM.

NOTE: The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.

Ordering Information

PART

PAR T N U MBER

ISL1209IU10* AGT 2.7 to 5.5 -40 to 85 10 Ld MSOP

ISL1209IU10Z* (See Note)

*Add “-TK” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

ANV 2.7 to 5.5 -40 to 85 10 Ld MSOP

RANGE

(V)

TEMP

RANGE

(°C) PACKAGE

(Pb-free)

Pinout

ISL1209

(10 LD MSOP)

TOP VIEW

IRQ/F

OUT

SCL

SDA

EVDET

BAT

GND

EVIN

FN6109.1

Features

• Real Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month, and Year

• Security and Event Functions

- Tamper detection with Time Stamp

- Event Detection During Battery Packed or Normal Modes

- Selectable Event Input Sampling Rates Allows Low Power Operation

- Selectable Glitch Filter on Event Input Monitor

• 15 Selectable Frequency Outputs

• Single Alarm

- Settable to the Second, Minute, Hour, Day of the Week, Day, or Month

- Single Event or Pulse Interrupt Mode

• Automatic Backup to Battery or Super Cap

• Power Failure Detection

• On-Chip Oscillator Compensation

• 2 Bytes Battery-Backed User SRAM

C Interface

•I

- 400kHz Data Transfer Rate

• 400nA Battery Supply Current

• Small Package

-10 Ld MSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Utility Meters

• Set Top Box/Modem

• POS Equipment

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Test Meters/Fixtures

• Vending Machine Management

• Security and Anti Tampering Applications

- Panel/Enclosure Status

- Warranty Reporting

- Time Stamping Applications

- Patrol/Security Check (Fire or Light Equipment)

- Automotive Applications

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

ISL1209

SDA

SCL

BAT

EVIN

GND

Pin Descriptions

TRIP

SDA

BUFFER

SCL

BUFFER

CRYSTAL

OSCILLATOR

POR

I2C

INTERFACE

SWITCH

INTERNAL

SUPPLY

RTC

DIVIDER

FREQUENCY

OUT

CONTROL

LOGIC

ALARM

Seconds

Minutes

Hours

Day of Week

Date

Month

Yea r

CONTROL

REGISTERS

USER SRAM

IRQ/

OUT

EVDET

NUMBER SYMBOL DESCRIPTION

1X1X1. The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external

32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.

2X2X2. The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external

32.768kHz quartz crystal. X2 should be left open when X1 is driven from external source.

BAT

This input provides a backup supply voltage to the device. V

BAT.

the V

supply fails. This pin should be tied to ground if not used.

supplies power to the device in the event that

BAT

4GNDGround.

5EVINEvent Input ( EVIN). The EVIN is an input pin that is used to detect an externally monitored event. When a high signal

is present at the EVIN pin an “event” is detected.

6 EVDET

Event Detect Output, active when EVIN is triggered. Open drain output.

7SDASerial Data (SDA). SDA is a bidirectional pin used to transfer serial data into and out of the device. It has an open

drain output and may be wire OR’ed with other open drain or open collector outputs.

8SCLSerial Clock (SCL). The SCL input is used to clock all serial data into and out of the device.

9IRQ

10 V

Interrupt Output IRQ, /Frequency Output F

OUT

output pin. The function is set via the configuration register.

Power supply.

DD.

Multi-functional pin that can be used as interrupt or frequency

OUT.

FN6109.1

September 27, 2005

ISL1209

Absolute Maximum Ratings

Voltage on VDD, V

(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

Voltage on X1 and X2 pins

(respect to ground) . . . . . . . . . . . . -0.5V to V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

, SCL, SDA, and IRQ pins

BAT

-0.5V to V

+ 0.5 (VDD Mode)

+ 0.5 (V

BAT

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . >±2kV

Mode)

DC Operating Characteristics – RTC Test Conditions:V

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.

SYMBOL PARAMETER CONDITIONS MIN

DD1

BAT

Main Power Supply 2.7 5.5 V

Battery Supply Voltage 1.8 5.5 V

Supply Current VDD = 5V 2 6 µA 1, 2

VDD = 3V 1.2 4 µA

DD2

DD3

BAT

TRIP

TRIPHYS

BATHYS

Supply Current With I2C Active VDD = 5V 40 120 µA 1, 2

Supply Current (Low Power Mode) VDD = 5V, LPMODE = 1 1.4 5 µA 1

Battery Supply Current V

= 3V 400 950 nA 1

BAT

Input Leakage Current on SCL 100 nA

I/O Leakage Current on SDA 100 nA

Mode Threshold 1.6 2.2 2.6 V

BAT

Hysteresis 10 30 50 mV

TRIP

Hysteresis 15 50 100 mV

BAT

EVIN

-0.3 0.3 x

0.7 x V

Hysteresis 0.05 x

EVPU

IRQ

OUT

EVIN Pullup Current V

= 3V 1.5 µA 5

SUP

and EVDET

Output Low Voltage VDD = 5V, IOL = 3mA 0.4 V

VDD = 2.7V, IOL = 1mA 0.4 V

TYP

(Note 4) MAX UNITS NOTES

VDD +

0.3

Power-Down Timing Test Conditions:V

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.

SYMBOL PARAMETER CONDITIONS MIN

DD SR-

VDD Negative Slew rate 10 V/ms 3

TYP

(Note 4) MAX UNITS NOTES

FN6109.1

September 27, 2005

ISL1209

I2C Interface Specifications Test Conditions:V

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

SDA and SCL input buffer LOW voltage

SDA and SCL input buffer HIGH voltage

-0.3 0.3 x

0.7 x V

(Note 4) MAX UNITS

VDD +

0.3

Hysteresis SDA and SCL input buffer hysteresis 0.05 x

Cpin SDA and SCL pin capacitance T

SCL

BUF

LOW

HIGH

SU:STA

HD:STA

SU:DAT

SDA output buffer LOW voltage,

VDD = 5V, IOL = 3mA 0.4 V

sinking 3mA

= 25°C, f = 1MHz, VDD=5V, VIN=0V,

=0V

OUT

10 pF

SCL frequency 400 kHz

Pulse width suppression time at SDA and SCL inputs

SCL falling edge to SDA output data valid

Time the bus must be free before the start of a new transmission

Any pulse narrower than the max spec is suppressed.

SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of V

window.

SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of V the following START condition.

during

50 ns

900 ns

1300 ns

Clock LOW time Measured at the 30% of VDD crossing. 1300 ns

Clock HIGH time Measured at the 70% of VDD crossing. 600 ns

START condition setup time SCL rising edge to SDA falling edge. Both

crossing 70% of V

START condition hold time From SDA falling edge crossing 30% of VDD to

SCL falling edge crossing 70% of V

Input data setup time From SDA exiting the 30% to 70% of VDD

600 ns

100 ns window, to SCL rising edge crossing 30% of V

DD.

HD:DAT

SU:STO

HD:STO

Input data hold time From SCL falling edge crossing 30% of VDD to

SDA entering the 30% to 70% of V

window.

STOP condition setup time From SCL rising edge crossing 70% of VDD, to

SDA rising edge crossing 30% of V

STOP condition hold time From SDA rising edge to SCL falling edge. Both

crossing 70% of V

Output data hold time From SCL falling edge crossing 30% of VDD,

until SDA enters the 30% to 70% of V

SDA and SCL rise time From 30% to 70% of V

DD.

window.

0 900 ns

600 ns

0ns

20 +

300 ns

0.1 x Cb

SDA and SCL fall time From 70% to 30% of V

DD.

20 +

0.1 x Cb

300 ns

Cb Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF

Rpu SDA and SCL bus pull-up resistor off-

chip

Maximum is determined by t For Cb = 400pF, max is about 2~2.5kΩ.

and tF.

1kΩ

For Cb = 40pF, max is about 15~20kΩ

NOTES:

1. IRQ

& F

and EVDET Inactive.

OUT

2. LPMODE = 0 (default).

3. In order to ensure proper timekeeping, the V

specification must be followed.

DD SR-

4. Typical values are for T = 25°C and 3.3V supply voltage.

5. V

SUP=VDD

if in V

Mode, V

SUP=VBAT

if in V

BAT

Mode.

FN6109.1

September 27, 2005

SDA vs. SCL Timing

ISL1209

HIGH

LOW

SCL

SU:STA

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

HD:STA

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be steady Will be steady

May change from LOW to HIGH

May change from HIGH to LOW

Don’t Care: Changes Allowed

N/A Center Line is

SU:DAT

Will change from LOW to HIGH

Will change from HIGH to LOW

Changing: State Not Known

High Impedance

HD:DAT

SU:STO

BUF

FN6109.1

September 27, 2005

ISL1209

VDD

Typical Performance Curves Temperature is 25°C unless otherwise specified

900E-9

800E-9

700E-9

600E-9

(A)

500E-9

BAT

400E-9

300E-9

200E-9

100E-9

000E+0

2.4E-06

2.2E-06

2.0E-06

1.8E-06

(A)

1.6E-06

DD1

1.4E-06

1.2E-06

1.0E-06

1E-6

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

BAT

FIGURE 1. I

-40-200 20406080

TEMPERATURE (°C)

FIGURE 3. I

DD1

vs V

BAT

VDD= 5V

VDD= 3.3V

BAT

vs TEMPERATURE FIGURE 4. I

1E-6

800E-9

600E-9

(A)

BAT

400E-9

200E-9

000E+0

FIGURE 2. I

2.4E-6

2.2E-6

2.0E-6

1.8E-6

1.6E-6

(A)

1.4E-6

DD1

1.2E-6

1.0E-6

800.0E-9

600.0E-9

400.0E-9

-40-200 20406080 TEMPERATURE (°C)

vs TEMPERATURE AT V

BAT

LPMODE = 0

LPMODE = 1

2.53.03.54.04.55.05.5

(V)

vs VDD WITH LPMODE ON & OFF

DD1

BAT

= 3V

(A)

DD1

2.1E-6

2.0E-6

1.9E-6

1.8E-6

1.7E-6

1.6E-6

1.5E-6

1.4E-6

1.3E-6

1.2E-6

1/32

1/16

FIGURE 5. I

3.0E-6

2.9E-6

2.8E-6

2.7E-6

2.6E-6

2.5E-6

(A)

2.4E-6

DD1

2.3E-6

2.2E-6

2.1E-6

2.0E-6

1.9E-6

1/2

1/4

1/8

OUT (Hz)

DD1

vs F

OUT

AT V

= 3.3V FIGURE 6. I

1024

4096

32768

1.8E-6 1

1/16

DD1

OUT (Hz)

vs F

OUT

1/2

1/4

1/8

1/32

AT VDD = 5V

4096

1024

32768

FN6109.1

September 27, 2005

ISL1209

EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V

5.0V

1533Ω

SDA AND

IRQ

/FOUT

FIGURE 7. STANDARD OUTPUT LOAD FOR TESTING THE

DEVICE WITH V

100pF

= 5.0V

FOR VOL= 0.4V

AND I

= 5V

= 3mA

General Description

The ISL1209 device is a low power Real Time Clock with Security and Event function timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, and battery-backed user SRAM.

The Event Detection function can be used for tamper detection, security or other chassis or generic system monitoring. Upon a valid event detection, the ISL1209 sets the Event Detection bit (EVT bit) in the status register and, can optionally: 1) Issue an Event Output signal (EVDET

2) At the time the event occurred, stop the RTC registers from advancing. The event monitor can function in both main V

and battery back up modes. The event monitor can also

be configured for various input detection rates to optimize power consumption for the application. In addition, the Event Monitor pin (EVIN) has a selectable glitch filter to avoid switch de-bouncing.

The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.

The ISL1209's powerful alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc.

The device also offers a backup power input pin. This V pin allows the device to be backed up by battery or SuperCap with automatic switchover from V

to V

entire ISL1209 device is fully operational from V

5.5V and the clock/calendar portion of the device remains fully operational in battery backup mode down to 1.8V (Standby Mode).

BAT

=2.7V to

pin),

BAT

. The

Pin Description

X1, X2

The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL1209 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from

-40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. The device can also be driven directly from a

32.768kHz source at pin X1.

FIGURE 8. RECOMMENDED CRYSTAL CONNECTION

BAT

This input provides a backup supply voltage to the device. V

supplies power to the device in the event that the VDD

BAT

supply fails. This pin can be connected to a battery, a Super Cap or tied to ground if not used.

EVIN (Event Input)

The EVIN pin is an input that is used to detect an externally monitored event. When a high signal is present at the EVIN pin, an “event” is detected. This input may be used for various monitoring functions, such as the opening of a detection switch on a chassis or door. The event detection circuit can be user enabled or disabled (see EVEN bit) and provides the option to be operational in battery backup modes (see EVBATB bit). When the event detection is disabled the EVIN pin is gated OFF. See functional Description for more details.

EVDET (Event Detect Output)

The EVDET is an open drain output which will go low when an event is detected at the EVIN pin. If the event detection function is enabled, the EVDET low until the EVT bit is cleared (see EVIN pin description).

IRQ/F

This dual function pin can be used as an interrupt or

(Interrupt Output/Frequency Output)

OUT

frequency output pin. The IRQ the frequency out control bits of the control/status register.

• Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm

output will go low and stay

mode is selected via

OUT

FN6109.1

September 27, 2005

ISL1209

has occurred and requests action. It is an open drain active low output.

• Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I

C bus. It is

an open drain active low output.

Serial Clock (SCL)

The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the V

pin is activated to minimize power consumption.

BAT

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode.

An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I when the backup power supply on the V

C interface speeds. It is disabled

pin is activated.

BAT

VDD, GND

Chip power supply and ground pins. The device will operate with a power supply from V capacitor is recommended on the V

=2.7V to 5.5VDC. A 0.1µF

pin to ground.

Functional Description

Power Control Operation

The power control circuit accepts a VDD and a V Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL1209 for up to 10 years. Another option is to use a Super Cap for applications where V

is interrupted for up

to a month. See the Applications Section for more information.

Normal Mode (VDD) to Battery Backup Mode (V

)

BAT

To transition from the VDD to V following conditions must be met:

Condition 1:

< V

where V

- V

BAT

BATHYS

≈ 50mV

Condition 2:

< V

where V

TRIP

≈ 2.2V

Battery Backup Mode (V (V

)

The ISL1209 device will switch from the V when one

of the following conditions occurs:

mode, both of the

BAT

) to Normal Mode

BAT

input.

BAT

to VDD mode

Condition 1:

> V

where V

+ V

BAT

BATHYS

≈ 50mV

Condition 2:

VDD > V where V

+ V

TRIP

TRIPHYS

≈ 30mV

These power control situations are illustrated in Figures 9 and 10.

BATTERY BACKUP

TRIP

BAT

- V

BAT

BATHYS

FIGURE 9. BATTERY SWITCHOVER WHEN V

∆

BAT

TRIP

FIGURE 10. BATTERY SWITCHOVER WHEN V

The I

C bus is deactivated in battery backup mode to provide

MODE

BATTERY BACKUP

MODE

BAT

TRIP

+ V

BAT

+ V

BAT

lower power. Aside from this, all RTC functions are operational during battery backup mode. Except for SCL and SDA, all the inputs and outputs of the ISL1209 are active during battery backup mode unless disabled via the control register. The User SRAM is operational in battery backup mode down to 1.8V.

Power Failure Detection

The ISL1209 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both V

and V

BAT

Low Power Mode

The normal power switching of the ISL1209 is designed to switch into battery backup mode only if the V lost. This will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. Another mode, called Low

power is

2.2V

1.8V

BATHYS

< V

TRIP

3.0V

2.2V

TRIPHYS

> V

TRIP

FN6109.1

September 27, 2005

+ 16 hidden pages

intersil ISL1209 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual