intersil ISL12027 DATA SHEET

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ISL12027

New Features

Data Sheet FN8232.1

Real Time Clock/Calendar with EEPROM

The ISL12027 device is a low power real time clock with timing and crystal compensation, clock/calender, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, CPU Supervisor and integrated 512 x 8 bit EEPROM, in 16 Byte per page format.

The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.

Pinouts

ISL12027 (8 LD TSSOP)

TOP VIEW

BAT

SCL

SDA

GND

RESET

ISL12027 (8 LD SOIC)

TOP VIEW

RESET

GND

BAT

SCL

SDA

Ordering Information

TEMP.

PAR T N UMBER

(Note)

ISL12027IB27Z 12027IB27Z 2.63V -40 to +85 8 Ld SOIC

ISL12027IB27AZ* 2.92V -40 to +85 8 Ld SOIC

ISL12027IB30AZ* 3.09V -40 to +85 8 Ld SOIC

ISL12027IBZ 12027IBZ 4.38V -40 to +85 8 Ld SOIC

ISL12027IBAZ* 4.64V -40 to +85 8 Ld SOIC

ISL12027IV27Z 2027IV27Z 2.63V -40 to +85 8 Ld TSSOP

ISL12027IV27AZ* 2.92V -40 to +85 8 Ld TSSOP

ISL12027IV30AZ* 3.09V -40 to +85 8 Ld TSSOP

ISL12027IVZ 2027IVZ 4.38V -40 to +85 8 Ld TSSOP

ISL12027IVAZ* 4.64V -40 to +85 8 Ld TSSOP

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/ JEDEC J STD-020.

Add “-T” suffix for tape and reel.

* Contact Factory for availability.

PAR T

MARKING

RESET

VOLTAGE

RANGE

(°C)

PACKAGE

(Pb-Free)

December 19, 2005

Features

• Real Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month, and Year

• Two Non-Volatile Alarms

- Settable on the Second, Minute, Hour, Day of the Week, Day, or Month

- Repeat Mode (periodic interrupts)

• Automatic Backup to Battery or SuperCap

• On-Chip Oscillator Compensation

- Internal Feedback Resistor and Compensation Capacitors

- 64 Position Digitally Controlled Trim Capacitor

- 6 Digital Frequency Adjustment Settings to ±30ppm

• 512 x 8 Bits of EEPROM

- 16-Byte Page Write Mode (32 total pages)

- 8 Modes of Block Lock™

Protection

- Single Byte Write Capability

• High Reliability

- Data Retention: 50 years

- Endurance: 500,000 Cycles Per Byte

C* Interface

•I

- 400kHz Data Transfer Rate

• 800nA Battery Supply Current

• Package Options

- 8 Ld SOIC and TSSOP Packages

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Utility Meters

• HVAC Equipment

• Audio/Video Components

• Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers/PDA

• POS Equipment

• Test Meters/Fixtures

• Office Automation (Copiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial/Medical/Automotive

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

32.768kHz

ISL12027

OSC Compensation

Oscillator

Frequency

Divider

1Hz

Timer

Calendar

Logic

Time

Keeping

Registers

(SRAM)

Battery

Switch

Circuitry

BAT

Timer

Status

Registers

(SRAM)

Low Voltage

Reset

Alarm

Compare

Alarm Regs

(EEPROM)

Mask

EEPROM

ARRAY

SCL

SDA

Serial Interface Decoder

RESET

Control Decode

Logic

Control/

Registers

(EEPROM)

Watchdog

Pin Descriptions

PIN NUMBER

SYMBOL BRIEF DESCRIPTIONSOIC TSSOP

1 3 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external

32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.

2 4 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external

3 5 RESET

4 6 GND Ground.

5 7 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an

6 8 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on

71V

82V

BAT

32.768kHz quartz crystal.

RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period has expired or that the voltage has dropped below a fixed V output. Recommended value for the pull-up resistor is 5kΩ, If unused, connect to ground.

threshold. It is an open drain active LOW

TRIP

open drain output and may be wire OR’ed with other open drain or open collector outputs.

this pin is always active (not gated).

This input provides a backup supply voltage to the device. V that the V

supply fails. This pin should be tied to ground if not used.

supplies power to the device in the event

BAT

Power Supply.

FN8232.1

December 19, 2005

ISL12027

Absolute Maximum Ratings Thermal Information

Voltage on VDD, V

(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

, SCL, SDA, and RESET pins

BAT

Voltage on X1 and X2 pins

(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V

ESD Rating (MIL-STD-883, Method 3014) . . . . . . . . . . . . . . .>±2kV

ESD Rating (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . .>175V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Thermal Resistance (Note) θ

(°C/W)

8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 120

8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . 140

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

DC Electrical Specifications Unless otherwise noted, V

= 3.3V

= +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are at TA = 25°C and

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT NOTES

Main Power Supply 2.7 5.5 V

Backup Power Supply 1.8 5.5 V

BAT

Electrical Specifications

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT NOTES

DD1

DD2

DD3

BAT

BATLKG

TRIP

TRIPHYSVTRIP

BATHYSVBAT

DD SR-VDD

RESET

Supply Current with I2C Active VDD = 2.7V 500 µA 1, 2, 3

= 5.5V 800 µA

Supply Current for Non-Volatile Programming

Supply Current for Main Timekeeping (Low Power Mode)

Battery Supply Current V

Battery Input Leakage VDD = 5.5V, V

Mode Threshold 1.8 2.2 2.6 V 5

BAT

VDD = 2.7V 2.5 mA 1, 2, 3

VDD = 5.5V 3.5 mA

VDD = V

BAT

SDA

= 1.8V,

= V

SDA

= 3.0V,

= V

SDA

= V

= 2.7V 10 µA 3

SCL

= V

= 5.5V 20 µA

SCL

800 1000 nA 1, 4, 5

= V

SCL

= V

RESET

=0V

850 1200 nA

= V

SCL

= 1.8V -100 100 nA

BAT

RESET

=0V

Hysteresis 30 mV 5, 8

Hysteresis 50 mV 5, 8

Negative Slew rate 10 V/ms 6

OUTPUT

Output Low Voltage VDD = 5.5V

Output Leakage Current VDD = 5.5V

V I

OUT

= 3mA

= 2.7V

= 1mA

100 400 nA

= 5.5V

0.4 V

, 3

FN8232.1

December 19, 2005

ISL12027

Watchdog Timer/Low Voltage Reset Parameters

SYMBOL PARAMETER CONDITIONS MIN

RPD

PURST

RVALID

RESET

WDO

RST

RSP

EEPROM SPECIFICATIONS

VDD Detect to RESET LOW 500 ns 7

Power-up Reset Time-Out Delay 100 250 400 ms

Minimum VDD for Valid RESET Output

ISL12027-4.5A Reset Voltage Level 4.59 4.64 4.69 V

ISL12027 Reset Voltage Level 4.33 4.38 4.43 V

ISL12027-3 Reset Voltage Level 3.04 3.09 3.14 V

ISL12027-2.7A Reset Voltage Level 2.87 2.92 2.97 V

ISL12027-2.7 Reset Voltage Level 2.58 2.63 2.68 V

Watchdog Timer Period 32.768kHz crystal between X1

and X2

Watchdog Timer Reset Time-Out Delay

32.768kHz crystal between X1 and X2

I2C Interface Minimum Restart Time 1.2 µs

EEPROM Endurance 500,000 Cycles

EEPROM Retention Temperature ≤75°C 50 Years

TYP

(Note 5) MAX UNITS NOTES

1.0 V

1.70 1.75 1.801 s

725 750 775 ms

225 250 275 ms

Serial Interface (I2C) Specifications

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES

SDA, and SCL Input Buffer LOW

Voltage

SDA, and SCL Input Buffer HIGH

Voltage

Hysteresis SDA and SCL Input Buffer

Hysteresis

SDA Output Buffer LOW Voltage I

Input Leakage Current on SCL V

I/O Leakage Current on SDA V

TIMING CHARACTERISTICS

SCL Frequency 400 kHz

SCL

Pulse Width Suppression Time at

SDA and SCL Inputs

SCL Falling Edge to SDA Output

Data Valid

Time the Bus Must be Free Before

BUF

the Start of a New Transmission

HIGH

Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns

LOW

Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns

SBIB = 1 (Under VDD mode) -0.3 0.3 x V

SBIB = 1 (Under VDD mode) 0.7 x V

SBIB = 1 (Under V

= 4mA 0 0.4 V

= 5.5V 0.1 10 µA

mode) 0.05 x V

Any pulse narrower than the max spec

VDD + 0.3 V

50 ns

is suppressed.

SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of V window.

SDA crossing 70% of VDD during a

1300 ns

900 ns

STOP condition, to SDA crossing 70% of V

during the following START

condition.

FN8232.1

December 19, 2005

ISL12027

Serial Interface (I2C) Specifications (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

HD:STO

Cpin SDA, and SCL Pin Capacitance 10 pF

NOTES:

1. RESET

2. V

3. V

4. Bit BSW = 0 (Standard Mode), V

5. Specified at 25°C.

6. In order to ensure proper timekeeping, the V

7. Parameter is not 100% tested.

8. t

START Condition Setup Time SCL rising edge to SDA falling edge.

Both crossing 70% of V

START Condition Hold Time From SDA falling edge crossing 30%

of V

to SCL falling edge crossing

70% of V

Input Data Setup Time From SDA exiting the 30% to 70% of

window, to SCL rising edge

crossing 30% of V

Input Data Hold Time From SCL falling edge crossing 70% of

to SDA entering the 30% to 70%

of V

window.

STOP Condition Setup Time From SCL rising edge crossing 70% of

, to SDA rising edge crossing 30%

of V

STOP Condition Hold Time for Read, or Volatile Only Write

Output Data Hold Time From SCL falling edge crossing 30% of

SDA and SCL Rise Time From 30% to 70% of V

SDA and SCL Fall Time From 70% to 30% of V

From SDA rising edge to SCL falling edge. Both crossing 70% of V

, until SDA enters the 30% to 70%

of V

window.

600 ns

100 ns

0ns

600 ns

0ns

20 +

250 ns

0.1 x Cb

20 +

250 ns

0.1 x Cb

Cb Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF

Non-Volatile Write Cycle Time 12 20 ms 8

Inactive (no reset).

= VDD x 0.1, V

= 2.63V (VDD must be greater than V

RESET

is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write

sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.

= VDD x 0.9, f

SCL

BAT

= 400kHz.

≥ 1.8V.

), V

RESET

specification must be followed.

DD SR-

BAT

= 0V.

FN8232.1

December 19, 2005

Timing Diagrams

ISL12027

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

SCL

SDA

SU:DAT

SU:STA

HD:STA

8TH BIT OF LAST BYTE ACK

HIGH

LOW

HD:DAT

FIGURE 1. BUS TIMING

STOP

CONDITION

FIGURE 2. WRITE CYCLE TIMING

START

CONDITION

BUF

SU:STO

HD:STO

SCL

SDA

RESET

RSP

RSP<tWDO

START STOP START

Note: All inputs are ignored during the active reset period (t

RESET

PURST

RSP>tWDO

FIGURE 3. WATCHDOG TIMING

RPD

PURST

RST

RSP>tWDO

RST

RVALID

FIGURE 4. RESET TIMING

FN8232.1

December 19, 2005

ISL12027

Typical Performance Curves Temperature is 25°C unless otherwise specified

0.90

4.00

3.50

3.00

2.50

2.00

Ibat (uA)

1.50

1.00

0.50

0.00

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

FIGURE 5. I

BSW = 0 or 1

SCL,SDA pullups = 0 V

SCL,SDA pul lups = Vbat

BSW = 0 or 1

Vbat (V)

BAT

vs V

SBIB = 0 FIGURE 6. I

BAT,

0.80

0.70

0.60

0.50

Ibat

0.40

0.30

0.20

0.10

0.00

1.80 2.30 2.80 3.30 3.80 4.30 4.80 5.30

SCL,SDA pullups = 0V

BSW = 0 or 1

Vbat(V)

vs V

BAT

BAT,

SBIB = 1

5.00

4.50

4.00

3.50

3.00

2.50

Idd (uA)

2.00

1.50

1.00

0.50

0.00

-45-35-25-15-5 5 1525354555657585

Vdd=5.5V

Vdd=3.3V

Temperature

FIGURE 7. I

4.50

4.00

3.50

3.00

2.50

2.00

Idd (uA)

1.50

1.00

0.50

0.00

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

vs TEMPERATURE FIGURE 8. I

DD3

Vdd (V)

FIGURE 9. I

DD3

vs V

1.40

1.20

Vbat = 3.0V

1.00

0.80

0.60

Ibat (uA)

0.40

0.20

0.00

-45-35-25-15-5 5 1525354555657585

Temperature

vs TEMPERATURE

BAT

PPM change from ATR=0

-20

-40

-32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 28

ATR set ti ng

FIGURE 10. ∆F

vs ATR SETTING

OUT

FN8232.1

December 19, 2005

ISL12027

Description

The ISL12027 device is a Real Time Clock with clock/ calendar, two polled alarms with integrated 512x8 EEPROM configured in 16 Byte per page format, oscillator compensation, CPU Supervisor (Power on Reset, Low Voltage Sensing and Watchdog Timer) and battery backup switch.

The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost.

The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, Seconds. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction.

The Dual Alarms can be set to any Clock/Calendar value for a match. For instance, every minute, every Tuesday, or 5:23 AM on March 21. The alarms can be polled in the Status Register. There is a repeat mode for the alarms allowing a periodic interrupt.

The ISL12027 device integrates CPU Supervisory functions (POR, WDT) and Battery Switch. There is Power-On-Reset (RESET assert RESET threshold. The V VTS0 registers to five (5) preselected levels. There is WatchDog Timer (WDT) with 3 selectable time-out periods (0.25s, 0.75s and 1.75s) and disabled setting. The WatchDog Timer activates the RESET

The device offers a backup power input pin. This V allows the device to be backed up by battery or SuperCap. The entire ISL12027 device is fully operational from 2.7 to

5.5V and the clock/calendar portion of the ISL12027 device remains fully operational down to 1.8V (Standby Mode).

The ISL12027 device provides 4k bits of EEPROM with 8 modes of BlockLock™ control. The BlockLock allows a safe, secure memory for critical user and configuration data, while allowing a large user storage area.

) output with 250ms delay from power on. It will also

when V

trip

goes below the specified

threshold is selectable via VTS2/VTS1/

pin when it expires.

BAT

This open drain output requires the use of a pull-up resistor. The pull-up resistor on this pin must use the same voltage source as V

. The output circuitry controls the fall time of

the output signal with the use of a slope controlled pulldown. The circuit is designed for 400kHz I

C interface

speed.

BAT

This input provides a backup supply voltage to the device. V

supplies power to the device in the event the VDD

BAT

supply fails. This pin can be connected to a battery, a SuperCap or tied to ground if not used.

RESET

The RESET signal output can be used to notify a host processor that the watchdog timer has expired or the V voltage supply has dipped below the V

threshold. It is

RESET

an open drain, active LOW output. Recommended value for the pull-up resistor is 10kΩ. If unused it can be tied to ground.

X1, X2

The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12027 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from

-40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. X2 is intended to drive a crystal only, and should not drive any external circuit (Figure 11).

NO EXTERNAL COMPENSATION RESISTORS OR CAPACITORS ARE NEEDED OR ARE RECOMMENDED TO BE CONNECTED TO THE X1 AND X2 PINS.

X1 X2

FIGURE 11. RECOMMENDED CRYSTAL CONNECTION

Pin Descriptions

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). The pull-up resistor on this pin must use the same voltage source as V

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated).

Real Time Clock Operation

The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of the second, minute, hour, day, date, month, and year. The RTC has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the ISL12027 powers up after the loss of both V operate until at least one byte is written to the clock register.

and V

, the clock will not

BAT

FN8232.1

December 19, 2005

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