intersil ISL12025 DATA SHEET

ISL12025

New Features

Data Sheet FN6371.1

Real-Time Clock/Calendar with EEPROM

The ISL12025 device is a low power real-time clock with timing and crystal compensation, clock/calender, 64-bit unique ID, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, CPU Supervisor and integrated 512 x 8-bit EEPROM, in a 16 Bytes per page format.

The oscillator uses an external, low-cost 32.768kHz crystal. The real-time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.

Ordering Information

PART

NUMBER

(Note)

ISL12025IBZ 12025IBZ 2.63V -40 to +85 8 Ld SOIC M8.15 ISL12025IVZ 2025IVZ 2.63V -40 to +85 8 Ld TSSOP M8.173

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Add “-T” suffix for tape and reel.

PART

MARKING

RESET

VOLTAGE

TEMP.

RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG.

Pinouts

ISL12025

(8 LD SOIC)

TOP VIEW

October 18, 2006

Features

• Real-Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month, and Year

• 64-bit Unique ID

• Two Non-Volatile Alarms

- Settable on the Second, Minute, Hour, Day of the Week, Day, or Month

- Repeat Mode (periodic interrupts)

• Automatic Backup to Battery or SuperCap

• On-Chip Oscillator Compensation

- Internal Feedback Resistor and Compensation Capacitors

- 64 Position Digitally Controlled Trim Capacitor

- 6 Digital Frequency Adjustment Settings to ±30ppm

• 512 x 8 Bits of EEPROM

- 16-Bytes Page Write Mode (32 total pages)

- 8 Modes of Block Lock™

- Single Byte Write Capability

• High Reliability

- Data Retention: 50 years

- Endurance: 2,000,000 Cycles Per Byte

C* Interface

•I

- 400kHz Data Transfer Rate

• 800nA Battery Supply Current

• Package Options

- 8 Ld SOIC and 8 Ld TSSOP Packages

• Pb-Free Plus Anneal Available (RoHS Compliant)

Protection

RESET

GND

X1 X2

BAT

X1 X2

1 2

3 4

ISL12025

(8 LD TSSOP)

TOP VIEW

1 2

3 4

8 7 6 5

BAT

SCL SDA

Applications

• Utility Meters

• Audio/Video Components

• Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

SCL SDA GND RESET

• Pagers/PDA

• POS Equipment

• Test Meters/Fixtures

• Office Automation (C opiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial/Medical/A utomotive

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

32.768kHz

X1 X2

OSC Compensation

Oscillator

Frequency

Divider

ISL12025

1Hz

Timer

Calendar

Logic

Time

Keeping

Registers

(SRAM)

Battery

Switch

Circuitry

BAT

Timer

Status

Registers

(SRAM)

Low Voltage

Reset

Alarm

Compare

Alarm Regs

(EEPROM)

Mask

EEPROM

ARRAY

SCL SDA

Serial

Interface

Decoder

RESET

Control Decode

Logic

Control/ Registers (EEPROM)

Watchdog

Pin Descriptions

PIN NUMBER

SYMBOL BRIEF DESCRIPTIONSOIC TSSOP

1 3 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external

2 4 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external

3 5 RESET

4 6 GND Ground. 5 7 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an

6 8 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on

71V

82V

BAT

32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.

32.768kHz quartz crystal. RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period

has expired or that the voltage has dropped below a fixed V

threshold. It is an open drain active LOW

TRIP

output. Recommended value for the pull-up resistor is 5kΩ, If unused, connect to ground.

open drain output and may be wire OR’ed with other open drain or open collector outputs.

this pin is always active (not gated). This input provides a backup supply voltage to the device. V

that the V

supply fails. This pin should be tied to ground if not used.

supplies power to the device in the event

BAT

Power Supply.

FN6371.1

October 18, 2006

ISL12025

Absolute Maximum Ratings Thermal Information

Voltage on VDD, V

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

, SCL, SDA, and RESET pins

BAT

Voltage on X1 and X2 pins

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V

Latchup (Note 1) . . . . . . . . . . . . . . . . . . .Class II, Level B @ +85°C

ESD Rating (MIL-STD-883, Method 3014) . . . . . . . . . . . . . . .>±2kV

ESD Rating (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . .>175V

*CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θJ

Thermal Resistance (Note 2) θ

(°C/W)

8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 120

8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . 140

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C

DC Electrical Specifications Unless otherwise noted, V

and V

= 3.3V

= +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are at TA = +25°C

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

BAT

Main Power Supply 2.7 5.5 V Backup Power Supply 1.8 5.5 V

Electrical Specifications

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT NOTES

BATLKG

TRIPHYSVTRIP

BATHYSVBAT

DD SR-VDD

RESET

Supply Current with I2C Active VDD = 2.7V 500 µA 3, 4, 5

DD1

VDD = 5.5V 800 µA

Supply Current for Non-Volatile

DD2

Programming

Supply Current for Main

DD3

Timekeeping (Low Power Mode)

Battery Supply Current V

BAT

Battery Input Leakage VDD = 5.5V, V

TRIPVBAT

Mode Threshold 1.8 2.2 2.6 V 7

VDD = 2.7V 2.5 mA 3, 4, 5 VDD = 5.5V 3.5 mA VDD = V V

DD BAT

BAT

SDA

= V

SDA

= 1.8V,

= V

SDA

= 3.0V,

= V

SDA

= V

= 2.7V 10 µA 5

SCL

= V

= 5.5V 20 µA

SCL

800 1000 nA 3, 6, 7

= V

= 0V

SCL

850 1200 nA

= V

= 0V

SCL

= 1.8V -100 100 nA

BAT

Hysteresis 30 mV 7, 10

Hysteresis 50 mV 7, 10

Negative Slew rate 10 V/ms 8

OUTPUT

Output Low Voltage VDD = 5.5V

Output Leakage Current VDD = 5.5V

V I

OUT

= 3mA

= 2.7V

= 1mA

100 400 nA

= 5.5V

0.4 V

, 3

FN6371.1

October 18, 2006

ISL12025

Watchdog T imer/Low Voltage Reset Parameters

SYMBOL PARAMETER CONDITIONS MIN

RPD

PURST

RVALID

RESET

WDO

RST

RSP

EEPROM SPECIFICATIONS

VDD Detect to RESET LOW 500 ns 9 Power-up Reset Time-Out Delay 100 250 400 ms Minimum VDD for Valid RESET

Output ISL12025-4.5A Reset Voltage

Level ISL12025 Reset Voltage Level 4.33 4.38 4.43 V ISL12025-3 Reset Voltage Level 3.04 3.09 3.14 V ISL12025-2.7A Reset Voltage

Level ISL12025-2.7 Reset Voltage Level 2.58 2.63 2.68 V Watchdog Timer Period 32.768kHz crystal between X1 and X21.70 1.75 1.801 s

Watchdog Timer Reset Time-Out

32.768kHz crystal between X1 and X2225 250 275 ms

Delay I2C Interface Minimum Restart

Time

EEPROM Endurance 2,000,000 Cycles EEPROM Retention Temperature ≤75°C 50 Years

TYP

(Note 5) MAX UNITS NOTES

1.0 V

4.59 4.64 4.69 V

2.87 2.92 2.97 V

725 750 775 ms 225 250 275 ms

1.2 μs

Serial Interface (I2C) Specifications

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES

SDA, and SCL Input Buffer LOW

Voltage

SDA, and SCL Input Buffer HIGH

Voltage

Hysteresis SDA and SCL Input Buffer

Hysteresis

SDA Output Buffer LOW Voltage I

Input Leakage Current on SCL V

I/O Leakage Current on SDA V

TIMING CHARACTERISTICS

SCL Frequency 400 kHz

SCL

Pulse Width Suppression Time at

SDA and SCL Inputs

SCL Falling Edge to SDA Output

Data Valid

Time the Bus Must Be Free before

BUF

the Start of a New Transmission

SBIB = 1 (Under VDD mode) -0.3 0.3 x V

SBIB = 1 (Under VDD mode) 0.7 x V

SBIB = 1 (Under V

= 4mA 0 0.4 V

= 5.5V 0.1 10 μA

mode) 0.05 x V

Any pulse narrower than the max

VDD + 0.3 V

50 ns

spec is suppressed. SCL falling edge crossing 30% of

, until SDA exits the 30% to

70% of V

window.

SDA crossing 70% of VDD during a

1300 ns

900 ns

STOP condition, to SDA crossing 70% of V START condition.

during the following

FN6371.1

October 18, 2006

ISL12025

Serial Interface (I2C) Specifications (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES

LOW

HIGH

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

HD:STO

Cpin SDA, and SCL Pin Capacitance 10 pF t

NOTES:

3. RESET

4. V

5. V

6. Bit BSW = 0 (Standard Mode), V

7. Specified at +25°C.

8. In order to ensure proper timekeeping, the V

9. Parameter is not 100% tested.

10. t

Clock LOW Time Measured at the 30% of VDD

1300 ns

crossing.

Clock HIGH Time Measured at the 70% of VDD

600 ns

crossing.

START Condition Setup Time SCL rising edge to SDA falling

edge. Both crossing 70% of V

START Condition Hold Time From SDA falling edge crossing

30% of V

to SCL falling edge

crossing 70% of V

Input Data Setup Time From SDA exiting the 30% to 70%

of V

window, to SCL rising edge

crossing 30% of V

Input Data Hold Time From SCL falling edge crossing

70% of V

to SDA entering the

30% to 70% of V

STOP Condition Setup Time From SCL rising edge crossing

70% of V

, to SDA rising edge

crossing 30% of V

STOP Condition Hold Time for Read, or Volatile Only Write

Output Data Hold Time From SCL falling edge crossing

SDA and SCL Rise Time From 30% to 70% of V

SDA and SCL Fall Time From 70% to 30% of V

From SDA rising edge to SCL falling edge. Both crossing 70% of V

30% of V 30% to 70% of V

, until SDA enters the

window.

600 ns

100 ns

0ns

600 ns

0ns

20 +

250 ns

0.1 x Cb 20 +

250 ns

0.1 x Cb

Cb Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF

Non-Volatile Write Cycle Time 12 20 ms 10

Inactive (no reset).

= VDD x 0.1, V

= 2.63V (VDD must be greater than V

RESET

is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write

sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.

= VDD x 0.9, f

BAT

= 400kHz.

SCL

≥1.8V.

), V

RESET

specification must be followed.

DD SR-

BAT

= 0V.

FN6371.1

October 18, 2006

Timing Diagrams

ISL12025

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

SCL

SDA

SU:DAT

SU:STA

HD:STA

8TH BIT OF LAST BYTE ACK

HIGH

LOW

HD:DAT

FIGURE 1. BUS TIMING

STOP

CONDITION

FIGURE 2. WRITE CYCLE TIMING

START

CONDITION

BUF

SU:STO

HD:STO

SCL

SDA

RESET

RSP

RSP<tWDO

START STOP START

NOTE: ALL INPUTS ARE IGNORED DURING THE ACTIVE RESET PERIOD (t

RESET

PURST

RSP>tWDO

FIGURE 3. WATCHDOG TIMING

RPD

PURST

RST

RSP>tWDO

RST

RVALID

FIGURE 4. RESET TIMING

FN6371.1

October 18, 2006

ISL12025

Typical Performance Curves Temperature is +25°C unless otherwise specified

0.90

4.00

3.50

3.00

2.50

2.00

Ibat (uA)

1.50

1.00

0.50

0.00

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

FIGURE 5. I

BSW = 0 or 1

SCL,SDA pullups = 0V

SCL,SDA pullups = Vbat

BSW = 0 or 1

Vbat (V)

vs V

BAT

BAT,

SBIB = 0 FIGURE 6. I

0.80

0.70

0.60

0.50

Ibat

0.40

0.30

0.20

0.10

0.00

1.80 2.30 2.80 3.30 3.80 4.30 4. 80 5.30

SCL,SDA pullups = 0V

BSW = 0 or 1

Vbat(V)

vs V

BAT

BAT,

SBIB = 1

5.00

4.50

4.00

3.50

3.00

2.50

Idd (uA)

2.00

1.50

1.00

0.50

0.00

-45-35-25-15-5 5 1525354555657585

Vdd=5.5V

Vdd=3.3V

Temperature

FIGURE 7. I

4.50

4.00

3.50

3.00

2.50

2.00

Idd (uA)

1.50

1.00

0.50

0.00

1.8 2.3 2.8 3.3 3.8 4.3 4 .8 5.3

vs TEMPERATURE FIGURE 8. I

DD3

Vdd (V)

FIGURE 9. I

DD3

vs V

1.40

1.20

Vbat = 3.0V

1.00

0.80

0.60

Ibat (uA)

0.40

0.20

0.00

-45-35-25-15-5 5 1525354555657585

Temperature

vs TEMPERATURE

BAT

PPM change from ATR=0

-20

-40

-32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 28

ATR setting

FIGURE 10. ΔF

vs ATR SETTING

OUT

FN6371.1

October 18, 2006

ISL12025

Description

The ISL12025 device is a Real-Time Clock with clock/calendar, two polled alarms with integrated 512x8 EEPROM configured in 16 Bytes per page format, oscillator compensation, CPU Supervisor (Power-on Reset, Low Voltage Sensing and Watchdog Timer) and battery backup switch.

The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost.

The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, Seconds. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction.

The 64-bit unique ID is a random numbers programmed, verified and Locked at the factory and it is only accessible for reading and cannot be altered by the customer.

The Dual Alarms can be set to any Clock/Calendar value for a match. For instance, every minute, every Tuesday, or 5:23 AM on March 21. The alarms can be polled in the Status Register. There is a repeat mode for the alarms allowing a periodic interrupt.

The ISL12025 device integrates CPU Supervisory functions (POR, WDT) and Battery Switch. There is Power-On-Reset (RESET assert RESET threshold. The V VTS2/VTS1/VTS0 registers to five (5) preselected levels. There is WatchDog Timer (WDT) with 3 selectable time-out periods (0.25s, 0.75s and 1.75s) and disabled setting. The WatchDog Timer activates the RESET

The device offers a backup power input pin. This V allows the device to be backed up by battery or SuperCap. The entire ISL12025 device is fully operational from 2.7 to

5.5V and the clock/calendar portion of the ISL12025 device remains fully operational down to 1.8V (Standby Power Mode).

) output with 250ms delay from power-on. It will also

when V

trip

goes below the specified

threshold is selectable via

pin when it expires.

BAT

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated).

This open drain output requires the use of a pull-up resistor. The pull-up resistor on this pin must use the same voltage source as V

. The output circuitry controls the fall time of

the output signal with the use of a slope-controlled pulldown. The circuit is designed for 400kHz I

C interface

speed.

BAT

This input provides a backup supply voltage to the device. V

supplies power to the device in the event the VDD

BAT

supply fails. This pin can be connected to a battery, a SuperCap or tied to ground if not used.

RESET

The RESET signal output can be used to notify a host processor that the watchdog timer has expired or the V voltage supply has dipped below the V

RESET

threshold. It is

an open drain, active LOW output. Recommended value for the pull-up resistor is 10kΩ. If unused it can be tied to ground.

X1, X2

The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12025 to supply a timebase for the real-time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from

-40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. X2 is intended to drive a crystal only, and should not drive any external circuit (Figure 11).

NO EXTERNAL COMPENSATION RESISTORS OR CAPACITORS ARE NEEDED OR ARE RECOMMENDED TO BE CONNECTED TO THE X1 AND X2 PINS.

The ISL12025 device provides 4k bits of EEPROM with eight modes of BlockLock™ control. The BlockLock allows a safe, secure memory for critical user and configuration data, while allowing a large user storage area.

Pin Descriptions

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). The pull-up resistor on this pin must use the same voltage source as V

X1 X2

FIGURE 11. RECOMMENDED CRYSTAL CONNECTION

Real-Time Clock Operation

The Real-Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of the second, minute, hour, day, date, month, and year. The RTC has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls

FN6371.1

October 18, 2006

ISL12025

24 hour or AM/PM format. When the ISL12025 powers up after the loss of both V operate until at least one byte is written to the clock register.

and V

, the clock will not

BAT

Reading the Real-Time Clock

The RTC is read by initiating a Read command and specifying the address corresponding to the register of the Real-Time Clock. The RTC Registers can then be read in a Sequential Read Mode. Since the clock runs continuously and read takes a finite amount of time, there is a possibility that the clock could change during the course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation.

Writing to the Real-Time Clock

The time and date may be set by writing to the RTC registers. RTC Register should be written ONLY with Page Write. To avoid changing the current time by an uncompleted write operation, write to the all 8 bytes in one write operation. When writing the RTC registers, the new time value is loaded into a separate buffer at the falling edge of the clock during the Acknowledge. This new RTC value is loaded into the RTC Register by a stop bit at the end of a valid write sequence. An invalid write operation aborts the time update procedure and the contents of the buffer are discarded. After a valid write operation, the RTC will reflect the newly loaded data beginning with the next “one second” clock cycle after the stop bit is written. The RTC continues to update the time while an RTC register write is in progress and the RTC continues to run during any non-volatile write sequences.

Accuracy of the Real-Time Clock

The accuracy of the Real-Time Clock depends on the accuracy of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information see the “Application Section” on page 21.

Clock/Control Registers (CCR)

The Control/Clock Registers are located in an area separate from the EEPROM array and are only accessible following a slave byte of “1101111x” and reads or writes to addresses [0000h:003Fh]. The clock/control memory map has memory

addresses from 0000h to 003Fh. The defined addresses are described in the Table 2. Writing to and reading from the undefined addresses are not recommended.

CCR Access

The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a three step process (see “Writing to the Clock/Control Registers” on page 13.)

The CCR is divided into 6 sections. These are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (5 bytes; non-volatile)

4. Unique ID (8 bytes, non-volatile)

5. Real-Time Clock (8 bytes; volatile)

6. Status (1 byte; volatile)

Each register is read and written through buffers. The nonvolatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one section of the CCR per operation. Access to another section requires a new operation. A read or write can begin at any address in the CCR.

It is not necessary to set the RWEL bit prior to writing the status register. Section 5 (status register) supports a singl e byte read or write only. Continued reads or writes from this section terminates the operation.

The state of the CCR can be read by performing a random read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read of the CCR will not result in the output of data from the memory array. At the end of a read , the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and continue reading the next Register.

Real-Time Clock Registers (Volatile)

SC, MN, HR, DT, MO, YR: Clock/Calendar Registers

These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.

FN6371.1

October 18, 2006

+ 18 hidden pages