intersil ISL12025 DATA SHEET

ISL12025

New Features

Data Sheet FN6371.1

Real-Time Clock/Calendar with EEPROM

The ISL12025 device is a low power real-time clock with timing and crystal compensation, clock/calender, 64-bit unique ID, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, CPU Supervisor and integrated 512 x 8-bit EEPROM, in a 16 Bytes per page format.

The oscillator uses an external, low-cost 32.768kHz crystal. The real-time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.

Ordering Information

PART

NUMBER

(Note)

ISL12025IBZ 12025IBZ 2.63V -40 to +85 8 Ld SOIC M8.15 ISL12025IVZ 2025IVZ 2.63V -40 to +85 8 Ld TSSOP M8.173

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Add “-T” suffix for tape and reel.

PART

MARKING

RESET

VOLTAGE

TEMP.

RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG.

Pinouts

ISL12025

(8 LD SOIC)

TOP VIEW

October 18, 2006

Features

• Real-Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month, and Year

• 64-bit Unique ID

• Two Non-Volatile Alarms

- Settable on the Second, Minute, Hour, Day of the Week, Day, or Month

- Repeat Mode (periodic interrupts)

• Automatic Backup to Battery or SuperCap

• On-Chip Oscillator Compensation

- Internal Feedback Resistor and Compensation Capacitors

- 64 Position Digitally Controlled Trim Capacitor

- 6 Digital Frequency Adjustment Settings to ±30ppm

• 512 x 8 Bits of EEPROM

- 16-Bytes Page Write Mode (32 total pages)

- 8 Modes of Block Lock™

- Single Byte Write Capability

• High Reliability

- Data Retention: 50 years

- Endurance: 2,000,000 Cycles Per Byte

C* Interface

•I

- 400kHz Data Transfer Rate

• 800nA Battery Supply Current

• Package Options

- 8 Ld SOIC and 8 Ld TSSOP Packages

• Pb-Free Plus Anneal Available (RoHS Compliant)

Protection

RESET

GND

X1 X2

BAT

X1 X2

1 2

3 4

ISL12025

(8 LD TSSOP)

TOP VIEW

1 2

3 4

8 7 6 5

BAT

SCL SDA

Applications

• Utility Meters

• Audio/Video Components

• Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

SCL SDA GND RESET

• Pagers/PDA

• POS Equipment

• Test Meters/Fixtures

• Office Automation (C opiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial/Medical/A utomotive

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

32.768kHz

X1 X2

OSC Compensation

Oscillator

Frequency

Divider

ISL12025

1Hz

Timer

Calendar

Logic

Time

Keeping

Registers

(SRAM)

Battery

Switch

Circuitry

BAT

Timer

Status

Registers

(SRAM)

Low Voltage

Reset

Alarm

Compare

Alarm Regs

(EEPROM)

Mask

EEPROM

ARRAY

SCL SDA

Serial

Interface

Decoder

RESET

Control Decode

Logic

Control/ Registers (EEPROM)

Watchdog

Pin Descriptions

PIN NUMBER

SYMBOL BRIEF DESCRIPTIONSOIC TSSOP

1 3 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external

2 4 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external

3 5 RESET

4 6 GND Ground. 5 7 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an

6 8 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on

71V

82V

BAT

32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.

32.768kHz quartz crystal. RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period

has expired or that the voltage has dropped below a fixed V

threshold. It is an open drain active LOW

TRIP

output. Recommended value for the pull-up resistor is 5kΩ, If unused, connect to ground.

open drain output and may be wire OR’ed with other open drain or open collector outputs.

this pin is always active (not gated). This input provides a backup supply voltage to the device. V

that the V

supply fails. This pin should be tied to ground if not used.

supplies power to the device in the event

BAT

Power Supply.

FN6371.1

October 18, 2006

ISL12025

Absolute Maximum Ratings Thermal Information

Voltage on VDD, V

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

, SCL, SDA, and RESET pins

BAT

Voltage on X1 and X2 pins

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V

Latchup (Note 1) . . . . . . . . . . . . . . . . . . .Class II, Level B @ +85°C

ESD Rating (MIL-STD-883, Method 3014) . . . . . . . . . . . . . . .>±2kV

ESD Rating (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . .>175V

*CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θJ

Thermal Resistance (Note 2) θ

(°C/W)

8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 120

8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . 140

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C

DC Electrical Specifications Unless otherwise noted, V

and V

= 3.3V

= +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are at TA = +25°C

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

BAT

Main Power Supply 2.7 5.5 V Backup Power Supply 1.8 5.5 V

Electrical Specifications

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT NOTES

BATLKG

TRIPHYSVTRIP

BATHYSVBAT

DD SR-VDD

RESET

Supply Current with I2C Active VDD = 2.7V 500 µA 3, 4, 5

DD1

VDD = 5.5V 800 µA

Supply Current for Non-Volatile

DD2

Programming

Supply Current for Main

DD3

Timekeeping (Low Power Mode)

Battery Supply Current V

BAT

Battery Input Leakage VDD = 5.5V, V

TRIPVBAT

Mode Threshold 1.8 2.2 2.6 V 7

VDD = 2.7V 2.5 mA 3, 4, 5 VDD = 5.5V 3.5 mA VDD = V V

DD BAT

BAT

SDA

= V

SDA

= 1.8V,

= V

SDA

= 3.0V,

= V

SDA

= V

= 2.7V 10 µA 5

SCL

= V

= 5.5V 20 µA

SCL

800 1000 nA 3, 6, 7

= V

= 0V

SCL

850 1200 nA

= V

= 0V

SCL

= 1.8V -100 100 nA

BAT

Hysteresis 30 mV 7, 10

Hysteresis 50 mV 7, 10

Negative Slew rate 10 V/ms 8

OUTPUT

Output Low Voltage VDD = 5.5V

Output Leakage Current VDD = 5.5V

V I

OUT

= 3mA

= 2.7V

= 1mA

100 400 nA

= 5.5V

0.4 V

, 3

FN6371.1

October 18, 2006

ISL12025

Watchdog T imer/Low Voltage Reset Parameters

SYMBOL PARAMETER CONDITIONS MIN

RPD

PURST

RVALID

RESET

WDO

RST

RSP

EEPROM SPECIFICATIONS

VDD Detect to RESET LOW 500 ns 9 Power-up Reset Time-Out Delay 100 250 400 ms Minimum VDD for Valid RESET

Output ISL12025-4.5A Reset Voltage

Level ISL12025 Reset Voltage Level 4.33 4.38 4.43 V ISL12025-3 Reset Voltage Level 3.04 3.09 3.14 V ISL12025-2.7A Reset Voltage

Level ISL12025-2.7 Reset Voltage Level 2.58 2.63 2.68 V Watchdog Timer Period 32.768kHz crystal between X1 and X21.70 1.75 1.801 s

Watchdog Timer Reset Time-Out

32.768kHz crystal between X1 and X2225 250 275 ms

Delay I2C Interface Minimum Restart

Time

EEPROM Endurance 2,000,000 Cycles EEPROM Retention Temperature ≤75°C 50 Years

TYP

(Note 5) MAX UNITS NOTES

1.0 V

4.59 4.64 4.69 V

2.87 2.92 2.97 V

725 750 775 ms 225 250 275 ms

1.2 μs

Serial Interface (I2C) Specifications

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES

SDA, and SCL Input Buffer LOW

Voltage

SDA, and SCL Input Buffer HIGH

Voltage

Hysteresis SDA and SCL Input Buffer

Hysteresis

SDA Output Buffer LOW Voltage I

Input Leakage Current on SCL V

I/O Leakage Current on SDA V

TIMING CHARACTERISTICS

SCL Frequency 400 kHz

SCL

Pulse Width Suppression Time at

SDA and SCL Inputs

SCL Falling Edge to SDA Output

Data Valid

Time the Bus Must Be Free before

BUF

the Start of a New Transmission

SBIB = 1 (Under VDD mode) -0.3 0.3 x V

SBIB = 1 (Under VDD mode) 0.7 x V

SBIB = 1 (Under V

= 4mA 0 0.4 V

= 5.5V 0.1 10 μA

mode) 0.05 x V

Any pulse narrower than the max

VDD + 0.3 V

50 ns

spec is suppressed. SCL falling edge crossing 30% of

, until SDA exits the 30% to

70% of V

window.

SDA crossing 70% of VDD during a

1300 ns

900 ns

STOP condition, to SDA crossing 70% of V START condition.

during the following

FN6371.1

October 18, 2006

ISL12025

Serial Interface (I2C) Specifications (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES

LOW

HIGH

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

HD:STO

Cpin SDA, and SCL Pin Capacitance 10 pF t

NOTES:

3. RESET

4. V

5. V

6. Bit BSW = 0 (Standard Mode), V

7. Specified at +25°C.

8. In order to ensure proper timekeeping, the V

9. Parameter is not 100% tested.

10. t

Clock LOW Time Measured at the 30% of VDD

1300 ns

crossing.

Clock HIGH Time Measured at the 70% of VDD

600 ns

crossing.

START Condition Setup Time SCL rising edge to SDA falling

edge. Both crossing 70% of V

START Condition Hold Time From SDA falling edge crossing

30% of V

to SCL falling edge

crossing 70% of V

Input Data Setup Time From SDA exiting the 30% to 70%

of V

window, to SCL rising edge

crossing 30% of V

Input Data Hold Time From SCL falling edge crossing

70% of V

to SDA entering the

30% to 70% of V

STOP Condition Setup Time From SCL rising edge crossing

70% of V

, to SDA rising edge

crossing 30% of V

STOP Condition Hold Time for Read, or Volatile Only Write

Output Data Hold Time From SCL falling edge crossing

SDA and SCL Rise Time From 30% to 70% of V

SDA and SCL Fall Time From 70% to 30% of V

From SDA rising edge to SCL falling edge. Both crossing 70% of V

30% of V 30% to 70% of V

, until SDA enters the

window.

600 ns

100 ns

0ns

600 ns

0ns

20 +

250 ns

0.1 x Cb 20 +

250 ns

0.1 x Cb

Cb Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF

Non-Volatile Write Cycle Time 12 20 ms 10

Inactive (no reset).

= VDD x 0.1, V

= 2.63V (VDD must be greater than V

RESET

is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write

sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.

= VDD x 0.9, f

BAT

= 400kHz.

SCL

≥1.8V.

), V

RESET

specification must be followed.

DD SR-

BAT

= 0V.

FN6371.1

October 18, 2006

Timing Diagrams

ISL12025

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

SCL

SDA

SU:DAT

SU:STA

HD:STA

8TH BIT OF LAST BYTE ACK

HIGH

LOW

HD:DAT

FIGURE 1. BUS TIMING

STOP

CONDITION

FIGURE 2. WRITE CYCLE TIMING

START

CONDITION

BUF

SU:STO

HD:STO

SCL

SDA

RESET

RSP

RSP<tWDO

START STOP START

NOTE: ALL INPUTS ARE IGNORED DURING THE ACTIVE RESET PERIOD (t

RESET

PURST

RSP>tWDO

FIGURE 3. WATCHDOG TIMING

RPD

PURST

RST

RSP>tWDO

RST

RVALID

FIGURE 4. RESET TIMING

FN6371.1

October 18, 2006

ISL12025

Typical Performance Curves Temperature is +25°C unless otherwise specified

0.90

4.00

3.50

3.00

2.50

2.00

Ibat (uA)

1.50

1.00

0.50

0.00

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

FIGURE 5. I

BSW = 0 or 1

SCL,SDA pullups = 0V

SCL,SDA pullups = Vbat

BSW = 0 or 1

Vbat (V)

vs V

BAT

BAT,

SBIB = 0 FIGURE 6. I

0.80

0.70

0.60

0.50

Ibat

0.40

0.30

0.20

0.10

0.00

1.80 2.30 2.80 3.30 3.80 4.30 4. 80 5.30

SCL,SDA pullups = 0V

BSW = 0 or 1

Vbat(V)

vs V

BAT

BAT,

SBIB = 1

5.00

4.50

4.00

3.50

3.00

2.50

Idd (uA)

2.00

1.50

1.00

0.50

0.00

-45-35-25-15-5 5 1525354555657585

Vdd=5.5V

Vdd=3.3V

Temperature

FIGURE 7. I

4.50

4.00

3.50

3.00

2.50

2.00

Idd (uA)

1.50

1.00

0.50

0.00

1.8 2.3 2.8 3.3 3.8 4.3 4 .8 5.3

vs TEMPERATURE FIGURE 8. I

DD3

Vdd (V)

FIGURE 9. I

DD3

vs V

1.40

1.20

Vbat = 3.0V

1.00

0.80

0.60

Ibat (uA)

0.40

0.20

0.00

-45-35-25-15-5 5 1525354555657585

Temperature

vs TEMPERATURE

BAT

PPM change from ATR=0

-20

-40

-32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 28

ATR setting

FIGURE 10. ΔF

vs ATR SETTING

OUT

FN6371.1

October 18, 2006

ISL12025

Description

The ISL12025 device is a Real-Time Clock with clock/calendar, two polled alarms with integrated 512x8 EEPROM configured in 16 Bytes per page format, oscillator compensation, CPU Supervisor (Power-on Reset, Low Voltage Sensing and Watchdog Timer) and battery backup switch.

The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost.

The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, Seconds. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction.

The 64-bit unique ID is a random numbers programmed, verified and Locked at the factory and it is only accessible for reading and cannot be altered by the customer.

The Dual Alarms can be set to any Clock/Calendar value for a match. For instance, every minute, every Tuesday, or 5:23 AM on March 21. The alarms can be polled in the Status Register. There is a repeat mode for the alarms allowing a periodic interrupt.

The ISL12025 device integrates CPU Supervisory functions (POR, WDT) and Battery Switch. There is Power-On-Reset (RESET assert RESET threshold. The V VTS2/VTS1/VTS0 registers to five (5) preselected levels. There is WatchDog Timer (WDT) with 3 selectable time-out periods (0.25s, 0.75s and 1.75s) and disabled setting. The WatchDog Timer activates the RESET

The device offers a backup power input pin. This V allows the device to be backed up by battery or SuperCap. The entire ISL12025 device is fully operational from 2.7 to

5.5V and the clock/calendar portion of the ISL12025 device remains fully operational down to 1.8V (Standby Power Mode).

) output with 250ms delay from power-on. It will also

when V

trip

goes below the specified

threshold is selectable via

pin when it expires.

BAT

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated).

This open drain output requires the use of a pull-up resistor. The pull-up resistor on this pin must use the same voltage source as V

. The output circuitry controls the fall time of

the output signal with the use of a slope-controlled pulldown. The circuit is designed for 400kHz I

C interface

speed.

BAT

This input provides a backup supply voltage to the device. V

supplies power to the device in the event the VDD

BAT

supply fails. This pin can be connected to a battery, a SuperCap or tied to ground if not used.

RESET

The RESET signal output can be used to notify a host processor that the watchdog timer has expired or the V voltage supply has dipped below the V

RESET

threshold. It is

an open drain, active LOW output. Recommended value for the pull-up resistor is 10kΩ. If unused it can be tied to ground.

X1, X2

The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12025 to supply a timebase for the real-time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from

-40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. X2 is intended to drive a crystal only, and should not drive any external circuit (Figure 11).

NO EXTERNAL COMPENSATION RESISTORS OR CAPACITORS ARE NEEDED OR ARE RECOMMENDED TO BE CONNECTED TO THE X1 AND X2 PINS.

The ISL12025 device provides 4k bits of EEPROM with eight modes of BlockLock™ control. The BlockLock allows a safe, secure memory for critical user and configuration data, while allowing a large user storage area.

Pin Descriptions

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). The pull-up resistor on this pin must use the same voltage source as V

X1 X2

FIGURE 11. RECOMMENDED CRYSTAL CONNECTION

Real-Time Clock Operation

The Real-Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of the second, minute, hour, day, date, month, and year. The RTC has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls

FN6371.1

October 18, 2006

ISL12025

24 hour or AM/PM format. When the ISL12025 powers up after the loss of both V operate until at least one byte is written to the clock register.

and V

, the clock will not

BAT

Reading the Real-Time Clock

The RTC is read by initiating a Read command and specifying the address corresponding to the register of the Real-Time Clock. The RTC Registers can then be read in a Sequential Read Mode. Since the clock runs continuously and read takes a finite amount of time, there is a possibility that the clock could change during the course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation.

Writing to the Real-Time Clock

The time and date may be set by writing to the RTC registers. RTC Register should be written ONLY with Page Write. To avoid changing the current time by an uncompleted write operation, write to the all 8 bytes in one write operation. When writing the RTC registers, the new time value is loaded into a separate buffer at the falling edge of the clock during the Acknowledge. This new RTC value is loaded into the RTC Register by a stop bit at the end of a valid write sequence. An invalid write operation aborts the time update procedure and the contents of the buffer are discarded. After a valid write operation, the RTC will reflect the newly loaded data beginning with the next “one second” clock cycle after the stop bit is written. The RTC continues to update the time while an RTC register write is in progress and the RTC continues to run during any non-volatile write sequences.

Accuracy of the Real-Time Clock

The accuracy of the Real-Time Clock depends on the accuracy of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information see the “Application Section” on page 21.

Clock/Control Registers (CCR)

The Control/Clock Registers are located in an area separate from the EEPROM array and are only accessible following a slave byte of “1101111x” and reads or writes to addresses [0000h:003Fh]. The clock/control memory map has memory

addresses from 0000h to 003Fh. The defined addresses are described in the Table 2. Writing to and reading from the undefined addresses are not recommended.

CCR Access

The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a three step process (see “Writing to the Clock/Control Registers” on page 13.)

The CCR is divided into 6 sections. These are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (5 bytes; non-volatile)

4. Unique ID (8 bytes, non-volatile)

5. Real-Time Clock (8 bytes; volatile)

6. Status (1 byte; volatile)

Each register is read and written through buffers. The nonvolatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one section of the CCR per operation. Access to another section requires a new operation. A read or write can begin at any address in the CCR.

It is not necessary to set the RWEL bit prior to writing the status register. Section 5 (status register) supports a singl e byte read or write only. Continued reads or writes from this section terminates the operation.

The state of the CCR can be read by performing a random read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read of the CCR will not result in the output of data from the memory array. At the end of a read , the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and continue reading the next Register.

Real-Time Clock Registers (Volatile)

SC, MN, HR, DT, MO, YR: Clock/Calendar Registers

These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.

FN6371.1

October 18, 2006

ISL12025

DW: Day of the Week Register

This register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as ‘0’.

Y2K: Year 2000 Register

Can have value 19 or 20. As of the date of the introduction of this device, there would be no real use for the value 19 in a true real-time clock, however.

24 Hour Time

If the MIL bit of the HR register is 1, the RTC uses a 24-hour format. If the MIL bit is 0, the RTC uses a 12-hour format and H21 bit functions as an AM/PM indicator with a ‘1’, representing PM. The clock defaults to standard time with H21 = 0.

Leap Years

Leap years add the day February 29 and are defined as those years that are divisible by 4.

Status Register (SR) (Volatile)

The Status Register is located in the CCR memory map at address 003Fh. This is a volatile register only and is used to control the WEL and RWEL write enable latches, read power status and two alarm bits. This register is separate from both the array and the Clock/Control Registers (CCR).

TABLE 1. STATUS REGISTER (SR)

ADDR 7 6 5 4 3 2 1 0

003Fh BAT AL1 AL0 OSCF 0 RWEL WEL RTCF

Default 0 0 0 0 0 0 0 1

OSCF: Oscillator Fail Indicator

This bit is set to “1” if the oscillator is not operating. The bit is set to “0” only if the oscillator is functioning. This bit is read only, and is set/reset by hardware.

RWEL: Register Write Enable Latch

This bit is a volatile latch that powers up in the LOW (disabled) state. The RWEL bit must be set to “1” prior to any writes to the Clock/Control Registers. Writes to RWEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the CCR requires both the RWEL and WEL bits to be set in a specific sequence.

WEL: Write Enable Latch

The WEL bit controls the access to the CCR during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR address will be ignored, although acknowledgment is still issued. The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the Status Register) or until the part powers up again. Writes to WEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition.

RTCF: Real-Time Clock Fail Bit

This bit is set to a ‘1’ after a total power failure. This is a read only bit that is set internally when the device powers up after having lost all power to the device (both V The bit is set regardless of whether V first. The loss of only one of the supplies does not result in setting the RTCF bit. The first valid write to the RTC after a complete power failure (writing one byte is sufficient) resets the RTCF bit to ‘0’.

or V

and V

BAT

=0V).

BAT

is applied

BAT: Battery Supply

This bit set to “1” indicates that the device is operating from V

, not VDD. It is a read-only bit and is set/reset by

BAT

hardware (ISL12025 internally). Once the device begins operating from V

, the device sets this bit to “0”.

AL1, AL0: Alarm Bits

These bits announce if either alarm 0 or alarm 1 match the real-time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the AL bits that are set when an SR read starts will be reset. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete.

Unused Bits:

Bit 3 in the SR is not used, but must be zero. The Data Byte output during a SR read will contain a zero in this bit location.

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ISL12025

TABLE 2. CLOCK/CONTROL MEMORY MAP

(Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation

ADDR. TYPE

003F Status SR BAT AL1 AL0 OSCF

0037 RTC 0036 DW 0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h 0034 MO 0033 DT 0032 HR MIL 0031 MN 0030 SC 0027 0026 ID6 ID67 ID66 ID65 ID64 ID63 ID62 ID61 ID60 * 0025 ID5 ID57 ID56 ID55 ID54 ID53 ID52 ID51 ID50 * 0024 ID4 ID47 ID46 ID45 ID44 ID43 ID42 ID41 ID40 * 0023 ID3 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 * 0022 ID2 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 * 0021 ID1 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 * 0020 ID0 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 * 0014 Control 0013 DTR 0012 ATR 0011 INT IM AL1E AL0E 0 0 0010 BL BP2 BP1 BP0 WD1 WD0

000F Alarm1 000E DWA1 EDW1 000D YRA1 Unused - Default = RTC Year value (No EEPROM) - Future expansion 000C MOA1 EMO1 000B DTA1 EDT1 000A HRA1 EHR1

0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h 0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h 0007 Alarm0 0006 DWA0 EDW0 0005 YRA0 Unused - Default = RTC Year value (No EEPROM) - Future expansion 0004 MOA0 EMO0 0003 DTA0 EDT0 0002 HRA0 EHR0 0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h 0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h

(SRAM)

Device ID

(EEPROM)

NAME

Y2K1

Y2K0

(see device ordering information). * indicates set at the factory, read-only)

BIT

REG

76543210

0 RWEL WEL RTCF 01h

Y2K

ID7 ID77 ID76 ID75 ID74 ID73 ID72 ID71 ID70 *

PWR SBIB BSW

0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 19/20 20h 0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0 0 0 G20 G13 G12 G11 G10 1-12 00h 0 0 D21 D20 D13 D12 D11 D10 1-31 01h

0 H21 H20 H13 H12 H11 H10 0-23 00h 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h

0 0 0 VTS2 VTS1 VTS0 4Xh 0 0 0 0 0 DTR2 DTR1 DTR0 00h 0 0 ATR5ATR4ATR3ATR2ATR1ATR0 00h

0 0 0 00h 0 0 0 18h

0 0 A1Y2K21 A1Y2K20 A1Y2K13 0 0 A1Y2K10 19/20 20h

0 0 0 0 DY2 DY1 DY0 0-6 00h

0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h

0 0 A0Y2K21 A0Y2K20 A0Y2K13 0 0 A0Y2K10 19/20 20h

0 0 0 0 DY2 DY1 DY0 0-6 00h

0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h

RANGE

DEFAULT

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ISL12025

Alarm Registers (Non-Volatile)

Alarm0 and Alarm1

The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. See “Device Operation” on page 13 and “Application Section” on page 21 for more information.

Control Registers (Non-Volatile)

The Control Bits and Registers described under this section are non-volatile.

BL Register

BP2, BP1, BP0 - Block Protect Bits

The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array. The partitions are described in Table 3.

TABLE 3.

PROTECTED ADDRESSES

BP2

BP1

BP0

0 0 0 None (Default) None 0 0 1 180 0 1 0 100 0 1 1 000 1 0 0 000 1 0 1 000 1 1 0 000 1 1 1 000

ISL12025 ARRAY LOCK

– 1FF

– 03F

– 07F

– 0FF

– 1FF

h h h h h h h

Upper 1/4 Upper 1/2

Full Array First 4 Pages First 8 Pages

First 16 Pages

Full Array

frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. For example, using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm adjustment range from -34ppm to +80ppm to the nominal frequency compensation.

FIGURE 12. DIAGRAM OF ATR

The effective on-chip series load capacitance, C

CRYSTAL

OSCILLATOR

LOAD

ranges from 4.5pF to 20.25pF with a mid-scale value of

12.5pF (default). C controlled capacitors, C and X2 pins to ground (see Figure 12). The value of C C

is given by the following formula:

CX16 b5⋅ 8b44b3 2b2 1b10.5b0 9+⋅+⋅+⋅+⋅+⋅+()pF=

is changed via two digitally

LOAD

and CX2, connected from the X1

and

(EQ. 1)

The effective series load capacitance is the combination of C

and CX2:

LOAD

---------------------------------- -

⎛⎞ ⎝⎠

⎛⎞

⎝⎠

---------- -

⋅ 8 b4 4 b3 2 b2 1 b1 0.5 b0 9+⋅+⋅+⋅+⋅+⋅+

16 b 5

-----------------------------------------------------------------------------------------------------------------------------

(EQ. 2)

For example: C

(ATR= 00000) = 12.5pF,

LOAD

(ATR= 100000) = 4.5pF, and

LOAD

(ATR= 011111) = 20.25pF.

LOAD

The entire range for the series combination of load capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values.

Oscillator Compensation Registers

There are two trimming options.

- ATR. Analog Trimming Register

- DTR. Digital Trimming Register These registers are non-volatile. The combination of analog and digital trimming can give up to -64ppm to +110ppm of total adjustment.

ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1, ATR0: Analog Trimming Register

Six analog trimming bits, ATR0 to ATR5, are provided in order to adjust the on-chip load capacitance value for

DTR Register - DTR2, DTR1, DTR0: Digital Trimming Register

The digital trimming Bits DTR2, DTR1 and DTR0 adjust the number of counts per second and average the ppm error to achieve better accuracy.

DTR2 is a sign bit, where: DTR2 = 0 means frequency compensation is >0. DTR2 = 1 means frequency compensation is <0.

DTR1 and DTR0 are scale bits. DTR1 gives 10ppm adjustment and DTR0 gives 20ppm adjustment.

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ISL12025

A range from -30ppm to +30ppm can be represented by using the three bits previously explained.

TABLE 4. DIGITAL TRIMMING REGISTERS

DTR REGISTER

000 0 010 +10 001 +20 011 +30 100 0 110 -10 101 -20 111 -30

ESTIMATED FREQUENCY

PPMDTR2 DTR1 DTR0

PWR Register: SBIB, BSW, VTS2, VTS1, VTS0 SBIB: Serial Bus Interface (Enable)

The serial bus can be disabled in Battery Backup Mode by setting this bit to “1”. This will minimize power drain on the battery. The Serial Interface can be enabled in Battery Backup Mode by setting this bit to “0” (default is “0”). See “Power Control Operation” on page 1 4.

BSW: Power Control Bit

The Power Control bit, BSW, determines the conditions for switching between V options.

Option 1. Standard: Set “BSW = 0” Option 2. Legacy /Default Mode: Set “BSW = 1” See “Power Control Operation” on page 14 for more details.

Also see “I

C Communications During Battery Backup and

LVR Operation” on page 23 for important details.

VTS2, VTS1, VTS0: V

The ISL12025 is shipped with a default VDD threshold (V a non-volatile with no protection, therefore any writes to this location can change the default value from that marked on the package. If not changed with a non-volatile write, this value will not change over normal operating and storage conditions. However, ISL12025 has four (4) additional selectable levels to fit the customers application. Levels are:

4.64V (default), 4.38V, 3.09V, 2.92V and 2.63V. The V selection is via 3 bits (VTS2, VTS1 and VTS0). See Table 5.

Care should be taken when changing the V bits. If the V the device will go into RESET and unless V the device will no longer be able to communicate using the

) per the ordering information table. This register is

RESET

C bus.

and Back Up Battery . There are two

RESET

Select Bits

RESET

select

voltage selected is higher than VDD, then

is increased,

VTS2 VTS1 VTS0 V

0 0 0 4.64V 0 0 1 4.38V 0 1 0 3.09V 0 1 1 2.92V 1 0 0 2.63V

TABLE 5.

RESET

Unique ID Registers

There are eight register bytes for storing the device ID. (Address 0020h to 0027h). Each device contains these bytes to provide a unique 64-bit ID programmed and tested in the factory before shipment. These registers are readonly, intended for serialization of end equipment, and cannot be changed or overwritten.

Device Operation

Writing to the Clock/Control Registers

Changing any of the bits of the clock/control registers requires the following steps:

1. Write a 02h to the St atus Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop).

2. Write a 06h to the Status Register to set both the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop).

Write all eight bytes to the RTC registers, or one byte to the SR, or one to five bytes to the control registers. This sequence starts with a start bit, requires a slave byte of “11011110” and an address within the CCR and is terminated by a stop bit. A write to the EEPROM registers in the CCR will initiate a non-volatile write cycle and will take up to 20ms to complete. A write to the RTC registers (SRAM) will require much shorter cycle time (t = t have no effect. The RWEL bit is reset by the completion of a write to the CCR, so the sequence must be repeated to again initiate another change to the CCR contents. If the sequence is not completed for any reason (by sending an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode. Writing all zeros to the status register resets both the WEL and RWEL bits. A read operation occurring between any of the previous operations will not interrupt the register write operation.

Alarm Operation

Since the alarm works as a comparison between the alarm registers and the RTC registers, it is ideal for notifying a host processor of a particular time event and trigger some action as a result. The host can be notified by polling the Status Register (SR) Alarm bits. These two volatile bits (AL1 for

). Writes to undefined areas

BUF

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October 18, 2006

ISL12025

Alarm 1 and AL0 for Alarm 0), indicate if an alarm has happened. The AL1 and AL0 bits in the status register are reset by the falling edge of the eighth clock of status register read.

There are two alarm operation modes: Single Event and periodic Interrupt Mode:

1. Single Event Mode is enabled by setting the AL0E or AL1E bit to “1”, the IM bit to “0”, and disabling the frequency output. This mode permits a one-time match between the alarm registers and the RTC registers. Once this match occurs, the AL0 or AL1 bit is set to “1”. Once the AL0 or AL1 bit is read, this will automatically resets it. Both Alarm registers can be set at the same time to trigger alarms. Polling the SR will reveal which alarm has been set.

2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is enabled by setting the AL0E or AL1E bit to “1” the IM bit to “1”, and disabling the frequency output. If both AL0E and AL1E bits are set to 1, then only the AL0E PIM alarm will function (AL0E overrides AL1E). This means that once the Interrupt Mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. Interrupt Mode CANNOT be used for general periodic alarms, however, since a specific time period cannot be programmed for interrupt, only matches to a specific time of day. The Interrupt Mode is only stopped by disabling the IM bit or the Alarm Enable bits.

Writing to the Alarm Registers

The Alarm Registers are non-volatile but require special attention to insure a proper non-volatile write takes place. Specifically , byte writes to individual registers are good for all but registers 0006h and 0000Eh, which are the DWA0 and DWA1 registers, respectively. Those registers will require a special page write for nonvolatile storage. The recommended page write sequences are as follows:

1. 16-byte page writes: The best way to write or update the Alarm Registers is to perform a 16-byte write beginning at address 0001h (MNA0) and wrapping around and ending at address 0000h (SCA0). This will insure that nonvolatile storage takes place. This means that the code must be designed so that the Alarm0 data is written starting with Minutes register, and then all the Alarm1 data, with the last byte being the Alarm0 Seconds (the page ends at the Alarm1 Y2k register and then wraps around to address 0000h).

Alternatively, the 16-byte page write could start with address 0009h, wrap around and finish with address 0008h. Note that any page write ending at address 0007h or 000Fh (the highest byte in each Alarm) will not trigger a nonvolatile write, so wrapping around or overlapping to the following Alarm's Seconds register is advised.

2. Other nonvolatile writes: It is possible to do writes of less than an entire page, but the final byte must always be addresses 0000h through 0004h or 0008h though 000Ch to trigger a nonvolatile write. Writing to those blocks of 5 bytes sequentially, or individually , will trigger a nonvolatile write. If the DWA0 or DWA1 registers need to be set, then enough bytes will need to be written to overlap with the other Alarm register and trigger the nonvolatile write. For Example, if the DWA0 register is being set, then the code can start with a multiple byte write beginning at address 0006h, and then write 3 bytes ending with the SCA1 register as follows:

Addr Name 0006h DWA0 0007h Y2K0 0008h SCA1

If the Alarm1 is used, SCA1 would need to have the correct data written.

Power Control Operation

The power control circuit accepts a VDD and a V Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power an Intersil RTC device for up to 10 years. Another option is to use a SuperCap for applications where V

for up to a month. See the “Application Section” on page 21 for more information.

There are two options for setting the change-over conditions from V

to Battery Backup Mode. The BSW bit in the PWR

- Option 1 - Standard Mode

- Option 2 - Legacy Mode (Default)

Note that the I

C bus may or may not be operational during battery backup, which is controlled by the SBIB bit. See “Backup Battery Operation” on page 22 for information.

Note that switching to battery backup initiates a three-second timeout period, during which the device will stay in Battery Backup Mode even if the V

normal power. The three-second delay is intended to lock out any power-up glitches that could cause communications errors. Also note that very fast (<10µs) power ramp rates will bypass this delay, so it is important to filter V

OPTION 1- STANDARD (POWER CONTROL) MODE

In the Standard Mode , the supply will switch over to the battery when V

drops below V

TRIP

or V

BAT

lower. In th is mode , accident al ope ration from the ba tte ry is prevented since the battery backup input will only be used when the

supply is shut off.

To select Option 1, BSW bit in the Power Register must be set to “BSW = 0”. A description of power switchover follows.

input.

BAT

is interrupted

resumes

well.

, whichever is

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October 18, 2006

ISL12025

Standard Mode Power Switchover

• Normal Operating Mode (VDD) to Battery Backup Mode )

BAT

To transition from the V

to V

following conditions must be met:

- Condition 1: V

< V

where V

- V

BAT

BATHYS

≈ 50mV

- Condition 2:

< V

where V

• Battery Backup Mode (V

TRIP

≈ 2.2V

BAT

The ISL12025 device will switch from the V mode when one of the following conditions occurs:

- Condition 1: V

> V

where V

+ V

BAT

BATHYS

≈ 50mV

- Condition 2:

> V

where V

+ V

TRIP

TRIPHYS

≈ 30mV There are two discrete situations that are possible when using Standard Mode:

BAT

< V These two power control situations are illustrated in Figures 13 and 14.

mode, both of the

BAT

) to Normal Mode (VDD)

to VDD

BAT

TRIP

and V

BAT

TRIP

whichever is the higher voltage. Care should be taken wh en changing from Normal to Legacy Mode. If the V higher than V

, then the device will enter battery back up

voltage is

BAT

and unless the battery is disconnected or the voltage decreases, the device will no longer operate from V

To select the Option 2, BSW bit in the Power Register must be set to “BSW = 1”.

• Normal Mode (V To transition from the V

) to Battery Backup Mode (V

to V

mode, the following

BAT

)

conditions must be met:

< V

• Battery Backup Mode (V The device will switch from the V

BAT

- V

BATHYS

) to Normal Mode (VDD)

BAT

to VDD mode when

BAT

the following condition occurs:

> V

BAT +VBATHYS

The Legacy Mode power control conditions are illustrated in Figure 15 below.

BAT

OFF

VOLTAGE

BATTERY BACKUP

TRIP

BAT

- V

BAT

BATHYS

FIGURE 13. BATTERY SWITCHOVER WHEN V

BAT

TRIP

FIGURE 14. BATTERY SWITCHOVER WHEN V

MODE

BATTERY BACKUP

MODE

TRIP

BAT

+ V

2.2V

1.8V

BATHYS

< V

TRIP

3.0V

2.2V

TRIPHYS

> V

TRIP

OPTION 2 - LEGACY (POWER CONTROL) MODE (DEFAULT)

The Legacy Mode follows conditions set in X1226 products. In this mode, switching from V

to V

is simply done by

BAT

comparing the voltages and the device operates from

FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE

Power-On Reset

Application of power to the ISL12025 activates a Power-On-Reset Circuit that pulls the RESET

pin active.

This signal provides several benefits.

- It prevents the system microprocessor from starting to

operate with insufficient voltage.

- It prevents the processor from operating prior to

stabilization of the oscillator.

- It allows time for an FPGA to download its configuration

prior to initialization of the circuit.

- It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power-up.

When V

exceeds the device V

typically 250ms the circuit releases RESET

threshold value for

RESET

, allowing the system to begin operation. Recommended slew rate is between 0.2V/ms and 50V/ms.

Watchdog Timer Ope ration

The watchdog timer timeout period is selectable. By writing a value to WD1 and WD0, the watchdog timer can be set to 3 different time out periods or off. When the Watchdog timer is set to off, the watchdog circuit is configured for low power operation. See Table 6.

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ISL12025

TABLE 6.

WD1 WD0 DURATION

1 1 disabled 1 0 250ms 0 1 750ms 0 0 1.75s

Watchdog Timer Restart

The Watchdog Timer is started by a falli ng edge of SDA when the SCL line is high (START condition). The start signal restarts the watchdog timer counter, resetting the period of the counter back to the maximum. If another START fails to be detected prior to the watchdog timer expiration, then the RESET

pin becomes active for one reset time out period. In the event that the start signal occurs during a reset time out period, the start will have no effect. When using a single START to refresh watchdog timer, a STOP condition should be followed to reset the device back to Standby Power Mode. See Figure 3.

Low Voltage Reset (LVR) Operation

When a power failure occurs, a voltage comparator compares the level of the V voltage (V below V V V

RESET

line rises above V

, then the RESET output will remain asserted low.

RESET

), then generates a RESET pulse if it is

RESET

. The reset pulse will timeout 250ms after the

line versus a preset threshold

. If the VDD remains below

RESET

Power-up and power-down waveforms are shown in Figure 4. The LVR circuit is to be designed so the RESET signal is valid down to V

= 1.0V.

When the LVR signal is active, unless the part has been switched into the Battery Backup Mode

, the completion of an

in-progress non-volatile write cycle is unaffected, allowing a non-volatile write to continue as long as possible (down to the Reset Valid Voltage). The LVR signal, when active, will terminate any in-progress communications to the device and prevents new commands from disrupting any current write operations. See “I

C Communications During Battery

Backup and LVR Operation” on page 23.

Serial Communication

Interface Conventions

The device supports the I2C Protocol.

Clock and Data

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 16.

Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 17.

Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby Power Mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 17.

Acknowledge

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. See Figure 18.

The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will not acknowledge if the slave address byte is incorrect.

In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to Standby Power Mode and place the device into a known state.

SCL

SDA

DATA STABLE DATA CHANGE DATA STABLE

FIGURE 16. VALID DATA CHANGES ON THE SDA BUS

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October 18, 2006

SCL

SDA

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ISL12025

START STOP

FIGURE 17. VALID START AND STOP CONDITIONS

81 9

START ACKNOWLEDGE

FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER

DEVICE IDENTIFIER

ARRAY

CCR

1 1

D7 D6 D5 D2D4 D3 D1 D0

0 1

00 0 0 0A80

A6 A5

1 0

0 1

FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)

Device Addressing

Following a start condition, the master must output a Slave Address Byte. The first four bits of the Slave Address Byte specify access to either the EEPROM array or to the CCR. Slave bits ‘1010’ access the EEPROM array. Slave bits ‘1101’ access the CCR.

When shipped from the factory, EEPROM array is UNDEFINED, and should be programmed by the customer to a known state.

R/W

A0A7 A2A4 A3 A1

SLAVE ADDRESS BYTE

BYTE 0

WORD ADDRESS 1

BYTE 1

WORD ADDRESS 0

BYTE 2

DATA BYTE

BYTE 3

Bit 3 through Bit 1 of the slave byte specify the device select bits. These are set to ‘111’.

The last bit of the Slave Address Byte defines the operation to be performed. When this R/W

bit is a one, then a read operation is selected. A zero selects a write operation. See Figure 19.

After loading the entire Slave Address Byte from the SDA bus, the ISL12025 compares the device identifier and device select bits with ‘1010111’ or ‘1101111’. Upon a correct

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October 18, 2006

ISL12025

compare, the device outputs an acknowledge on the SDA line.

Following the Slave Byte is a two byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power-up the internal address counter is set to address 0h, so a current address read of the EEPROM array starts at address 0. When required, as part of a random read, the master must supply the 2 Word Address Bytes as shown in Figure 19.

In a random read operation, the slave byte in the “dummy write” portion must match the slave byte in the “read” section. That is if the random read is from the array the slave byte must be 1010111x in both instances. Similarly, for a random read of the Clock/Control Registers, the slave byte must be 1101111x i n both places.

Write Operations

Byte Write

For a write operation, the device requires the Slave Address Byte and the Word Address Bytes. This gives the master access to any one of the words in the array or CCR. (Note: Prior to writing to the CCR, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. See “Writing to the Clock/Control Registers” on page 1 3.) Upon receipt of each address byte, the ISL12025 responds with an acknowledge. After receiving both address bytes the ISL12025 awaits the eight bits of data. After receiving the 8 data bits, the ISL12025 again responds with an acknowledge. The master then terminates the transfer by generating a stop condition. The ISL12025 then begins an internal write cycle of the data to the non-volatile memory. During the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 20.

A write to a protected block of memory is ignored, but will still receive an acknowledge. At the end of the write command, the ISL12025 will not initiate an internal write cycle, and will continue to ACK commands.

Byte writes to all of the nonvolatile registers are allowed, except the DWAn registers which require multiple byte writes

or page writes to trigger nonvolatile writes. See the Device Operation section for more information.

Page Write

The ISL12025 has a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 15 more bytes to the memory array and up to 7 more bytes to the clock/control registers. The RTC registers require a page write (8 bytes), individual register writes are not allowed. (Note: Prior to writing to the CCR, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. See “Writing to the Clock/Control Registers” on page 13.)

After the receipt of each byte, the ISL12025 responds with an acknowledge, and the address is internally incremented by one. The address pointer remains at the last address byte written. When the counter reaches the end of the page, it “rolls over” and goes back to the first address on the same page. This means that the master can write 16 bytes to a memory array page or 8 bytes to a CCR section starting at any location on that page. For example, if the master begins writing at location 10 of the memory and loads 15 bytes, then the first 6 bytes are written to addresses 10 through 15, and the last 6 bytes are written to columns 0 through 5. Afterwards, the address counter would point to location 6 on the page that was just written. If the master supplies more than the maximum bytes in a page, then the previously loaded data is over-written by the new data, one byte at a time. See Figure 21.The master terminates the Data Byte loading by issuing a stop condition, which causes the ISL12025 to begin the non-volatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 22 for the address, acknowledge, and data transfer sequence.

Stops and Write Modes

Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and its associated ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte + ACK is sent, then the ISL12025 resets itself without performing the write. The contents of the array are not affected.

SIGNALS FROM THE MASTER

SDA BUS

SIGNALS FROM THE SLAVE

S T A

SLAVE

R T

ADDRESS

FIGURE 20. BYTE WRITE SEQUENCE

1111

A C K

WORD

ADDRESS 1

0000000

A C K

WORD

ADDRESS 0

DATA

A C K

T O P

A C K

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ISL12025

6 BYTES

ADDRESS = 5

ADDRESS POINTER ENDS

AT ADDR = 5

FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10

SIGNALS FROM THE MASTER

SDA BUS

SIGNALS FROM THE SLAVE

T A R T

SLAVE

ADDRESS

1111

0000000

A C K

WORD

ADDRESS 1

FIGURE 22. PAGE WRITE SEQUENCE

Acknowledge Polling

Disabling of the inputs during non-volatile write cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the ISL12025 initiates the internal non-volatile write cycle. Acknowledge polling can begin immediately. To do this, the master issues a start condition followed by the Memory Array Slave Address Byte for a write or read operation (AEh or AFh). If the ISL12025 is still busy with the non-volatile write cycle, then no ACK will be returned. When the ISL12025 has completed the write operation, an ACK is returned and the host can proceed with the read or write operation. See the flow chart in Figure 24. Note: Do not use the CCR Slave byte (DEh or DFh) for Acknowledge Polling.

Read Operations

There are three basic read operations: Current Address Read, Random Read, and Sequential Read.

6 BYTES

A C K

ADDRESS

WORD

ADDRESS 0

1 ≤ n ≤ 16 for EEPROM array

≤ n ≤ 8 for CCR

DATA

(1)

A C K

ADDRESS

DATA

(n)

acknowledge, then transmits eight data bits. The master terminates the read operation by not responding with an acknowledge during the ninth clock and issuing a stop condition. See Figure 23 for the address, acknowledge, and data transfer sequence.

SIGNALS FROM THE MASTER

SDA BUS

SIGNALS FROM THE SLAVE

FIGURE 23. CURRENT ADDRESS READ SEQUENCE

T A R T

SLAVE

ADDRESS

11111

A C

DATA

S T

A C K

S T O P

Current Address Read

Internally the ISL12025 contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up, the sixteen bit address is initialized to 0h. In this way, a current address read immediately after the power-on reset can download the entire contents of memory starting at the first location. Upon receipt of the Slave Address Byte with the R/W

bit set to one, the ISL12025 issues an

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ISL12025

Byte load completed

by issuing STOP.

Enter ACK Polling

Issue START

Issue Memory Array Slave

Address Byte

AFh (Read) or AEh (Write)

ACK

returned?

YES

Non-volatile write

cycle complete. Continue

command sequence?

YES

Continue normal

Read or Write

command sequence

PROCEED

Issue STOP

FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE

It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.

Random Read

Random read operations allow the master to access any location in the ISL12025. Prior to issuing the Slave Address

Byte with the R/W

bit set to zero, the master must first

perform a “dummy” write operation. The master issues the start condition and the slave address

byte, receives an acknowledge, then issues the word address bytes. After acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte with the R/W

bit set to one. This is followed by an acknowledge from the device and then by the eight bit data word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 25 for the address, acknowledge, and data transfer sequence.

In a similar operation called “Set Current Address,” the device sets the address if a stop is issued instead of the second start shown in Figure 25. The ISL12025 then goes into Standby Power Mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current address read or random address read. The first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition.

The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter “rolls over” to the start of the address space and the ISL12025 continues to output data for each acknowledge received. See Figure 26 for the acknowledge and data transfer sequence.

SIGNALS FROM THE MASTER

SDA BUS

SIGNALS FROM THE SLAVE

S T

SLAVE

A R T

ADDRESS

1111

A C K

WORD

ADDRESS 1

0000000

ADDRESS 0

A C K

WORD

FIGURE 25. RANDOM ADDRESS READ SEQUENCE

A C K

T A R

ADDRESS

SLAVE

1111

S T

A C K

DATA

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ISL12025

SIGNALS FROM THE MASTER

SDA BUS

SIGNALS FROM THE SLAVE

SLAVE

ADDRESS

A C K

DATA

(1)

FIGURE 26. SEQUENTIAL READ SEQUENCE

Application Section

Crystal Oscillator and Temperature Compensation

Intersil has now integrated the oscillator compensation circuity on-chip, to eliminate the need for external components and adjust for crystal drift over temperature and enable very high accuracy time keeping (<5ppm drift).

The Intersil RTC family uses an oscillator circuit with on-chip crystal compensation network, including adjustable load-capacitance. The only external component required is the crystal. The compensation network is optimized for operation with certain crystal parameters which are common in many of the surface mount or tuning-fork crystals available today. Table 7 summarizes these parameters.

Table 8 contains some crystal manufacturers and part numbers that meet the requirements for the Intersil RTC products.

The turnover temperature in Table 7 describes the temperature where the apex of the of the drift vs. temperature curve occurs. This curve is parabolic with the drift increasing as (T-T0) example, the turnover temperature is typically +25°C, and a peak drift of >110ppm occurs at the temperature extremes of

. For an Epson MC-405 device, for

A C K

DATA

(2)

A C K

DATA

(n-1)

(n is any integer greater than 1)

A C K

DATA

(n)

S T

-40 and +85°C. It is possible to address this variable drift by adjusting the load capacitance of the crystal, which will result in predictable change to the crystal frequency. The Intersil RTC family allows this adjustment over temperature since the devices include on-chip load capacitor trimming. This control is handled by the Analog Trimming Register, or ATR, which has 6 bits of control. The load capacitance range covered by the ATR circuit is approximately 3.25pF to

18.75pF , in 0.25pF increments. Note that actual capacitance would also include about 2pF of package related capacitance. In-circuit tests with commercially available crystals demonstrate that this range of capacitance allows frequency control from +116ppm to -37ppm, using a 12.5pF load crystal.

In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are three bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ±30ppm in increments of 10ppm. The default setting is 0ppm. The DTR control can be used for coarse adjustments of frequency drift over temperature or for crystal initial accuracy correction.

TABLE 7. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTC’S

PARAMETER MIN TYP MAX UNITS NOTES

Frequency 32.768 kHz Frequency Tolerance ±100 ppm Down to 20p pm if desired Turnover Temperature 20 25 30 °C Typically the value used for most crystals Operating Temperature Range -40 85 °C Parallel Load Capacitance 12.5 pF Equivalent Series Resistance 50 k

Ω For best oscillator performance

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ISL12025

TABLE 8. CRYSTAL MANUFACTURERS

MANUFACTURER PART NUMBER TEMP RANGE +25°C FREQUENCY TOLERANCE

Citizen CM201, CM202, CM200S -40 to +85°C ±20ppm Epson MC-405, MC-406 -40 to +85°C ±20ppm Raltron RSM-200S-A or B -40 to +85°C ±20ppm SaRonix 32S12A or B -40 to +85°C ±20ppm Ecliptek ECPSM29T-32.768K -10 to +60°C ±20ppm ECS ECX-306/ECX-306I -10 to +60°C ±20ppm Fox FSM-327 -40 to +85°C ±20ppm

A final application for the ATR control is in-circuit calibration for high accuracy applications, along with a temperature sensor chip. Once the RTC circuit is powered up with battery backup, and frequency drift is measured. The ATR control is then adjusted to a setting which minimizes drift. Once adjusted at a particular temperature, it is possible to adjust at other discrete temperatures for minimal overall drift, and store the resulting settings in the EEPROM. Extremely low overall temperature drift is possible with this method. The Intersil evaluation board contains the circuitry necessary to implement this control.

For more detailed operation, see Intersil’s application note AN154 on Intersil’s website at www.intersil.com.

Layout Considerations

The crystal input at X1 has a very high impedance and will pick up high frequency signals from other circuits on the board. Since the X2 pin is tied to the other side of the crystal, it is also a sensitive node. These signals can couple into the oscillator circuit and produce double clocking or mis-clocking, seriously affecting the accuracy of the RTC. Care needs to be taken in layout of the RTC circuit to avoid noise pickup. Figure 27 shows a suggested layout for the ISL12025 or ISL12027 devices.

The X1 and X2 connections to the crystal are to be kept as short as possible. A thick ground trace around the crystal is advised to minimize noise intrusion, but ground near the X1 and X2 pins should be avoided as it will add to the load capacitance at those pins. Keep in mind these guidelines for other PCB layers in the vicinity of the RTC device. A small decoupling capacitor at the V

pin of the chip is mandatory,

with a solid connection to ground (Figure 27).

Oscillator Measurements

When a proper crystal is selected and the layout guidelines above are observed, the oscillator should start up in most circuits in less than one second. Some circuits may take slightly longer, but startup should definitely occur in less than 5s. When testing RTC circuits, the most common impulse is to apply a scope probe to the circuit at the X2 pin (oscillator output) and observe the waveform. DO NOT DO THIS! Although in some cases you may see a usable waveform, due to the parasitics (usually 10pF to ground) applied with the scope probe, there will be no useful information in that waveform other than the fact that the circuit is oscillating. The X2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be affected by the parasitic elements in the scope probe. Applying a scope probe can possibly cause a faulty oscillator to start up, hiding other issues (although in the Intersil RTC’s, the internal circuitry assures startup when using the proper crystal and layout).

FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8

The best way to analyze the RTC circuit is to power it up and read the real-time clock as time advances. Alternatively the frequency can be checked by setting an alarm for each minute. Using the pulse interrupt mode setting, the once-perminute interrupt functions as an indication of proper oscillation.

Backup Battery Operation

Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for up to 10 years. Another option is to use a supercapacitor for applications where V short periods of time. Depending on the value of supercapacitor used, backup time can last from a few days

may disappear intermittently for

October 18, 2006

FN6371.1

ISL12025

to two weeks (with >1F). A simple silicon or Schottky barrier diode can be used in series with V supercapacitor, which is connected to the V use Schottky diodes with very low leakages, <1µA

to charge the

pin. Try to

BAT

desirable.

Do not use the diode to charge a battery (especially lithium batteries!).

There are two possible modes for battery backup operation, Standard and Legacy Mode. In S tandard Mode, there are no operational concerns when switching over to battery backup since all other devices functions are disabled. Battery drain is minimal in Standard Mode, and return to Normal V powered operations predictable. In Legacy modes, the V pin can power the chip if the voltage is above V V

This makes it possible to generate alarms and

TRIP.

BAT

and

communicate with the device under battery backup, but the supply current drain is much higher than the Standard Mode and backup time is reduced. During initial power-up, the default mode is the Legacy Mode.

I2C Communications During Battery Backup and LVR Operation

Operation in Battery Backup Mode and LVR is affected by the BSW and SBIB bits as described previously. These bits allow flexible operation of the serial bus and EEPROM in Battery Backup Mode, but certain operational details need to be clear before utilizing the different modes. The most significant detail is that once V

C communications cease regardless of whether the device

is programmed for I

C operation in Battery Backup Mode.

goes below V

RESET

, then

Mode. In actuality the VDD will go below V

RESET

before switching to battery backup, which will disable I2C ANYTIME the device goes into Battery Backup Mode. Regardless of the battery voltage, the I to the V

voltage (see Figure 29).

RESET

C will work down

• Mode B - In this mode the selection bits indicate switchover to battery backup at V

DD<VBAT

, and I2C communications in battery backup. In order to communicate in Battery Backup Mode, the V voltage must be less than the V must be greater than V bus pins must go to V

RESET

to communicate. This mode is

BAT

voltage AND VDD

BAT

. Also, pull-ups on the I2C

RESET

the same as the normal operating mode of the X1227 device

• Mode C - In this mode the selection bits indicate a low V

switchover combined with no communications in

battery backup. Operation is actually identical to Mode A

C communications down to VDD = V

with I

RESET

, then no

communications (see Figure 28).

• Mode D - In this mode the selection bits indicate

< V

switchover to battery backup at V

, and no I2C

BAT

communications in battery backup. This mode is unique in that there is I2C communication as long as VDD is higher than V

RESET

or V

, whichever is greater. This mode is

BAT

the safest for guaranteeing I2C communications only when there is a Valid VDD (see Figure 29).

2.7V TO 5.5V

BAT

SUPERCAPACITOR

Table 9 describes four different modes possible with using the BSW and SBIB bits, and how they are affect LVR and battery backup operation.

• Mode A - In this mode selection bits indicate a low V

switchover combined with I2C operation in Battery Backup

TABLE 9. I2C, LV RESET, AND BATTERY BACKUP OPERATION SUMMARY (Shaded Row is same as X1227 operation)

BSW

MODE SBIB BIT

A 0 0 Standard Mode,

(X1227

Mode)

C 1 0 Standard Mode,

D 1 1 Legacy Mode,

0 1 Legacy Mode,

BIT

SWITCHOVER

VOLTAGE

TRIP

VBAT

= 2.2V typ

< V

BAT

= 2.2V typ

< V

BAT

I2C ACTIVE IN

BATTERY

BACKUP?

NO NO Operation of I2C bus down to

YES, only if

BAT>VRESET

NO NO Operation of I2C bus down to

NO NO Operation of I2C bus down to V

FIGURE 28. SUPERCAPACITOR CHARGING CIRCUIT

EE PROM WRITE/READ IN BATTERY BACKUP?

YES Operation of I2C bus into Battery Backup

DD=VRESET

communications. Battery switchover at V

TRIP

Mode, but only for V

> V

BAT

Bus must have pullups to V

DD=VRESET

communications. Battery switchover at V

TRIP

, whichever is higher.

BAT

NOTES

, then below that no

> V

RESET

, then below that no

BAT

RESET

FN6371.1

October 18, 2006

RESET

TRIP

(2.2V)

RESET

BAT

(2.63V)

ISL12025

(3.0V)

tPURST

I2C BUS ACTIVE

BAT

RESET

BAT

TRIP

(2.2V)

RESET

(VDD POWER, V

NOT CONNECTED)

BAT

FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C

(3.0V)

BAT

(2.63V)

tPURST

I2C BUS ACTIVE

FIGURE 30. RESET OPERATION IN MODE D

(BATTERY BACKUP MODE)

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ISL12025

Alarm Operation Examples

Below are examples of both Single Event and periodic Interrupt Mode alarms.

Example 1 – Alarm 0 set with single interrupt (IM = “0”) A single alarm will occur on January 1 at 11:30am. A. Set Alarm0 registers as follows:

ALARM0

SCA0 00000000 00hSeconds disabled MNA0 10110000B0hMinutes set to 30,

HRA0 10010001 91hHours set to 11,

DTA0 10000001 81hDate set to 1,

MOA0 10000001 81hMonth set to 1,

DWA0 00000000 00hDay of week

B. Also, the AL0E bit must be set as follows:

CONTROL

INT 00100000x0hEnable Alarm

BIT

DESCRIPTION76543210HEX

enabled

disabled

BIT

DESCRIPTION76543210HEX

After these registers are set, an alarm will be gene rated when the RTC advances to exactly 11:30am on January 1 (after seconds change from 59 to 00) by setting the AL0 bit in the status register to “1”.

Example 2 – Pulsed interrupt once per minute ( IM= “1”) Interrupts at one minute intervals when the seconds register

is at 30s. A. Set Alarm0 registers as follows:

ALARM0

SCA0 10110000B0hSeconds set to 30,

MNA0 0000000000hMinutes disabled HRA0 0000000000hHours disabled

DTA0 0000000000hDate disabled MOA0 0000000000hMonth disabled DWA0 0000000000hDay of week disabled

BIT

DESCRIPTION76543210HEX

enabled

B. Set the Interrupt register as follows:

CONTROL REGISTER

INT 10100000x0hEnable Alarm and Int

BIT

DESCRIPTION76543210HEX

Mode

Note that the status register AL0 bit will be set each time the alarm is triggered, but does not need to be read or cleared.

FN6371.1

October 18, 2006

Small Outline Plastic Packages (SOIC)

ISL12025

INDEX AREA

123

-A-

-B-

SEATING PLANE

-C-

0.25(0.010) BM M

h x 45°

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

FN6371.1

October 18, 2006

ISL12025

Thin Shrink Small Outline Plastic Packages (TSSOP)

INDEX AREA

123

-A-

0.05(0.002)

SEATING PLANE

0.10(0.004) C AM BS

-B-

-C-

0.25(0.010) BM M

0.10(0.004)

GAUGE

PLANE

0.25

0.010

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)

M8.173

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N8 87

Rev. 1 12/00

NOTESMIN MAX MIN MAX

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6371.1

October 18, 2006

intersil ISL12025 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual