intersil ISI6556B DATA SHEET

®

ISL6556B

Data Sheet December 28, 2004

Optimized Multi-Phase PWM Controller
with 6-Bit DA C and Programmable Internal
Temperature Compensation for VR10.X
Application

The ISL6556B controls microprocessor core voltage
regulation by driving up to 4 synchronous-rectified buck
channels in parallel. Multi-phase buck converter architecture
uses interleaved timing to multiply channel ripple frequency
and reduce input and output ripple currents.

The ISL6556B utilizes r

current sensing in each

DS(ON)

phase for adaptive voltage positioning (droop), channel­current balancing, and overcurrent protection. To ensure the
accuracy of droop, a programmable internal temperature
compensation function is implemented to nullify the effect of
r

temperature sensitivity.

DS(ON)

A unity gain, differential amplifier is provided for remote voltage
sensing. Any potential difference between remote and local
grounds can be eliminated using the remote-sense amplifier.
The precision threshold-sensitive enable input is available to
accurately coordinate the startup of the ISL6556B with Intersil
MOSF ET driver IC. Dynamic-VID™ technology allows
seamless on-the-fly VID changes. The offset pin allow s accurate
voltage offset settings that are independent of VID setting. The
ISL6556B uses 5V bias and has a built-in shunt regulator to
allow 12V bias using only a small external limiting resistor.

Ordering Information

PART NUMBER TEMP. (°C) PACKAGE PKG. DWG. #

ISL6556BCB* 0 to 70 28 Ld SOIC M28.3

ISL6556BCBZ*

(Note)

ISL6556BCBZA

-T (Note)

ISL6556BCR* 0 to 70 32 Ld 5x5B QFN L32.5x5B

ISL6556BCRZ*

(Note)
* Add “-T” suffix for tape and reel.

0 to 70 28 Ld SOIC (Pb-free) M28.3

0 to 70 28 Ld SOIC Tape and

Reel (Pb-free)

0 to 70 32 Ld 5x5B QFN

(Pb-free)

M28.3

L32.5x5B

FN9097.4

Features

• Precision Multi-Phase Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over Temperature and Life

- Adjustable Reference-Voltage Offset

• Precision r

DS(ON)

- Integrated Programmable Temperature Compensation

- Accurate Load-Line Programming

- Accurate Channel-Current Balancing

- Low-Cost, Lossless Current Sensing

• Internal Shunt Regulator for 5V or 12V Biasing

• Microprocessor Voltage Identification Input

- Dynamic VID™ Technology

- 6-Bit VID Input

- 0.8375V to 1.600V in 12.5mV Steps

• Threshold Enable Function for Precision Sequencing

• Overcurrent Protection

• Overvoltage Protection

- No Additional External Components Needed

- OVP Pin to drive optional Crowbar Device

• 2, 3, or 4 Phase Operation up to 1.5MHz per Phase

• QFN Package Option

- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline

- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile

• Pb-free Available (RoHS Compliant)

Current Sensing

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free sold ering operations. Intersil Pb-fre e

products are MSL classified at Pb-free peak re flow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDE C J STD-020.

1

Dynamic VID™ is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinouts

32 LEAD QFN

TOP VIEW

ISL6556B

28 LEAD SOIC

TOP VIEW

VID3

VID2

VID1

VID0

VID12.5

OFS

TCOMP

REF

VID4

PGOOD

OVP

FS

GND

ENLL

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

9 10111213141516

FB

OFSOUT

COMP

VDIFF

VSEN

RGND

EN

GND

VCC

PWM3

OVP

1

PGOOD

PWM4

24

23

ISEN4

22

ISEN2

21

PWM2

20

PWM1

19

ISEN1

18

GND

ISEN3

17

VID12.5

TCOMP

VID4

VID3

VID2

VID1

VID0

OFS

REF

FB

COMP

VDIFF

2

3

4

5

6

7

8

9

10

11

12

13

14

FS

28

27

EN

26

VCC

25

PWM4

24

ISEN4

23

ISEN2

22

PWM2

PWM1

21

ISEN1

20

ISEN3

19

PWM3

18

GND

17

16

RGND

15

VSEN

2

FN9097.4

December 28, 2004

ISL6565BCB Block Diagram

ISL6556B

RGND

VSEN

OFS

OVP

VDIFF

PGOOD

SOFT-START

AND

FAULT LOG IC

OVP

OVP

S

LATCH

∑

∑

∑

VCC

POWER-ON

RESET (POR)

CLOCK AND

SAWTOOTH

GENERATOR

∑

1.24V

EN

THREE-STATE

FS

PWM1

PWM2

PWM3

VID4

VID3

VID2

VID1

VID0

VID12.5

COMP

FB

DYNAMIC

VID

D/A

I_TOT

I_TRIP

∑

∑

GND

CHANNEL
CURRENT
BALANCE

CHANNEL

DETECT

SAMPLE

&

HOLD

CHANNEL

CURRENT

SENSE

PWM4

ISEN1

ISEN2

ISEN3

ISEN4

3

FN9097.4

December 28, 2004

ISL6565BCR Block Diagram

ISL6556B

RGND

VSEN

OFS

OFSOUT

REF

x1

OVP

+200mV

OFFSET

VDIFF

PGOOD

SOFT-START

AND

FAULT LOG IC

OVP

OVP

S

LATCH

R

Q

VCC

POWER-ON

RESET (POR)

CLOCK AND

SAWTOOTH

GENERATOR

∑

PWM

∑

∑

PWM

∑

PWM

ENLL

1.24V

EN

THREE-STATE

FS

PWM1

PWM2

PWM3

VID4

VID3

VID2

VID1

VID0

VID12.5

COMP

FB

TCOMP

DYNAMIC

VID

D/A

∑

PWM

E/A

CHANNEL
CURRENT
BALANCE

I_TRIP

OC

∑

I_TOT

T

GND

CHANNEL

DETECT

SAMPLE

&

HOLD

CHANNEL

CURRENT

SENSE

PWM4

ISEN1

ISEN2

ISEN3

ISEN4

4

FN9097.4

December 28, 2004

Typical Application of ISL6556BCB

+5V

COMP

VID_PGOOD
(BUFFERED)

R

FB

VDIFF

VSEN

RGND

PGOOD

OVP

VID4

VID3

VID2

VID1

VID0

VID12.5

OFS

FS

GND

T

ISL6556BCB

VCC

TCOMP

REF

PWM1

ISEN1

PWM2

ISEN2

PWM3

ISEN3

PWM4

ISEN4

EN

ISL6556B

+12V

VCC

PVCC

HIP6601B

PWM

+12V

VCC

PVCC

HIP6601B

PWM

+12V

VCC

PVCC

HIP6601B

PWM

VIN

BOOT

UGATE

PHASE

LGATE

GND

VIN

BOOT

UGATE

PHASE

LGATE

GND

VIN

µP

LOAD

BOOT

UGATE

PHASE

LGATE

GND

+12V

VIN

VCC

BOOT

UGATE

PVCC

PHASE

HIP6601B

LGATE

PWM

5

GND

FN9097.4

December 28, 2004

Typical Application of ISL6556BCR

+5V

COMP

VID_PGOOD

R

FB

VDIFF

VSEN

RGND

PGOOD

OVP

VID4

VID3

VID2

VID1

VID0

VID12.5

OFS

FS

GND

T

ISL6556BCR

ENLL

VCC

OFSOUT

TCOMP

REF

ISEN1

PWM1

PWM2

ISEN2

PWM3

ISEN3

PWM4

ISEN4

EN

+12V

ISL6556B

+12V

VCC

PVCC

HIP6601B

PWM

+12V

VCC

PVCC

HIP6601B

PWM

+12V

VCC

PVCC

HIP6601B

PWM

VIN

BOOT

UGATE

PHASE

LGATE

GND

VIN

BOOT

UGATE

PHASE

LGATE

GND

VIN

µP

LOAD

BOOT

UGATE

PHASE

LGATE

GND

+12V

VIN

VCC

BOOT

UGATE

PVCC

PHASE

HIP6601B

LGATE

PWM

6

GND

FN9097.4

December 28, 2004

ISL6556B

Absolute Maximum Ratings

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V

Input, Output, or I/O Voltage (except OVP) . .GND -0.3V to V

OVP Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V

ESD (Human body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV

ESD (Machine model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V

ESD (Charged device model) . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV

CC

+ 0.3V

Thermal Information

Thermal Resistance θJA (°C/W) θJC (°C/W)

SOIC Package (Note 1) . . . . . . . . . . . . 60 N/A

QFN Package (Notes 2, 3). . . . . . . . . . 32 3.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Operating Conditions

Supply Voltage, VCC (5V bias mode, Note 3) . . . . . . . . . . +5V ±5%

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C

CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is no t implied.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

2. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

3. For θ

Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 4), T

VCC SUPPLY CURRENT

Nominal Supply VCC = 5VDC; EN = 5VDC; R

Shutdown Supply VCC = 5VDC; EN = 0VDC; R

SHUNT REGULATOR

VCC Voltage VCC tied to 12VDC thru 300Ω resistor, R
VCC Sink Current VCC tied to 12VDC thru 300Ω resistor, R

POWER-ON RESET AND ENABLE

POR Threshold VCC Rising 4.2 4.31 4.50 V

ENABLE Threshold EN Rising 1.22 1.24 1.26 V

ENLL Input Logic Low Level --0.4V
ENLL input Logic High Level 0.8 - - V
ENLL Leakage Current ENLL = 5V - - 1 µA

REFERENCE VOLTAGE AND DAC

System Accuracy (VID = 1.2V-1.6V) (Note 5) -0.5 - 0.5 %VID
System Accuracy (VID = 0.8375V-1.1875V) (Note 5) -0.8 - 0.8 %VID
VID Pull Up -65 -50 -35 µA
VID Input Low Level --0.4V
VID Input High Level 0.8 - - V
DAC Source/Sink Current VID = 010100 -200 - 200 µA
OFSOUT Source/Sink Current (ISL6556BCR Only) -50 - 50 µA
REF Source/Sink Current -50 - 50 µA

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Unless Otherwise Specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

= 100kΩ,

ISEN1 = ISEN2 = ISEN3 = ISEN4 = -70µA

VCC Falling 3.7 3.82 4.00 V

Hysteresis - 100 - mV
Fault Reset 1.10 1.14 1.18 V

T

= 100kΩ -1014mA

T

J

= 100kΩ 5.6 5.9 6.2 V

T

= 100kΩ --25mA

T

= 0°C to 105°C.

-1418mA

7

FN9097.4

December 28, 2004

ISL6556B

Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 4), T

= 0°C to 105°C.

J

Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

PIN-ADJUSTABLE OFFSET

Voltage at OFS pin Offset resistor connected to ground 485 500 515 mV

VCC = 5.00V, offset resistor connected to VCC 2.91 3.00 3.09 V

OSCILLATOR

Accuracy R

= 100kΩ -10 - 10 %

T

Adjustment Range 0.08 - 1.5 MHz
Sawtooth Amplitude -1.5- V
Max Duty Cycle - 66.7 - %

ERROR AMPLIFIER

Open-Loop Gain R
Open-Loop Bandwidth C
Slew Rate C

= 10kΩ to ground - 80 - dB

L

= 100pF, RL = 10kΩ to ground - 18 - MHz

L

= 100pF 4.5 6.0 7.5 V/µs

L

Maximum Output Voltage 4.0 4.3 - V
Output High Voltage @ 2mA 3.7 - - V
Output Low Voltage @ 2mA --1.35V

REMOTE-SENSE AMPLIFIER

Bandwidth -20- MHz
Output High Current VSEN - RGND = 2.5V -500 - 500 µA
Output High Current VSEN - RGND = 0.6 -500 - 500 µA

PWM OUTPUT

PWM Output Voltage LOW Threshold Iload = ±500µA --0.3V
PWM Output Voltage HIGH Threshold Iload = ±500µA 4.3 - - V

TEMPERATURE COMPENSATION

Temperature Compensation Current @ 40°C and

10 15 20 µA

Tcomp = 0.5V
Temperature Compensation Transconductance - 1 - 1µA/V/°C

SENSE CURRENT

Sensed Current Tolerance ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA, 0°C to 105°C 74 81 91 µA
Overcurrent Trip Level 98 110 122 µA

POWER GOOD AND PROTECTION MONITORS

PGOOD Low Voltage I

= 4mA - - 0.4 V

PGOOD

Undervoltage Offset From VID VSEN Falling 72 74 76 %VID
Overvoltage Threshold Voltage above VID, after Soft-Start (Note 5) 180 200 220 mV

Before Enable - 1.63 - V
VCC < POR Threshold 1.7 1.8 1.87 V

Overvoltage Reset Voltage VCC ≥ POR Threshold, VSEN Falling - 0.6 - V

VCC < POR Threshold - 1.5 - V

OVP Drive Voltage I

= -100mA, VCC = 5V - 1.9 - V

OVP

Minimum VCC for OVP 1.4 - - V

NOTES:

4. When using the internal shunt regulator, VCC is clamped to 6.02V (max). Current must be limited to 25mA or less.

5. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

6. During soft-start, VDAC rises from 0 to VID. The overvoltage trip level is the higher of 1.7V and VDAC + 0.2V.

8

FN9097.4

December 28, 2004