Intersil IRFP150N Datasheet

TM

IRFP150N

Data Sheet March 2000

44A, 100V, 0.030 Ohm, N-Channel Power MOSFET
Packaging

JEDEC TO-247

SOURCE

DRAIN

GATE

DRAIN
(TAB)

Symbol

D

G

File Number 4844

Features

• Ultra Low On-Resistance

-r

= 0.030Ω, VGS= 10V

DS(ON)

• Simulation Models

- Temperature Compensated PSPICE™ and SABER
Electrical Models

- Spice and SABER

©

Thermal Impedance Models

- www.intersil.com

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

Ordering Information

PART NUMBER PACKAGE BRAND

IRFP150N TO-247 IRFP150N

©

S

Absolute Maximum Ratings T

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain Current

Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Figures 6, 14, 15

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

NOTES:

1. TJ = 25oC to 150oC.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

= 25oC, Unless Otherwise Specified

C

DSS

DGR

GS

DM

STG

pkg

IRFP150N

UNITS

100 V
100 V
±20 V

D
D

D

L

44
31

Figure 4

155

1.03

-55 to 175

300
260

A
A

W

W/oC

o

C

o

C

o

C

1

1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation. SABER© is a Copyright of Analogy Inc.

IRFP150N

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV
Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R
Thermal Resistance Junction to

Ambient
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q
Gate Charge at 10V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Gate to Drain "Miller" Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

DSSID

DSS

VDS = 95V, VGS = 0V - - 1 µA
VDS = 90V, VGS = 0V, TC = 150oC - - 250 µA

GSS

GS(TH)VGS

DS(ON)ID

θJC

R

θJA

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(10)

g(TH)

ISS

OSS

RSS

VGS = ±20V - - ±100 nA

TO-247 - - 0.97oC/W

VDD = 50V, ID = 44A
VGS= 10V,
RGS = 6.2Ω
(Figures 18, 19)

r

f

VGS = 0V to 10V - 48 58 nC
VGS = 0V to 2V - 3.1 3.8 nC

gs

gd

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)

= 250µA, VGS = 0V (Figure 11) 100 - - V

= VDS, ID = 250µA (Figure 10) 2 - 4 V

= 44A, VGS = 10V (Figure 9) - 0.0255 0.030 Ω

--30oC/W

- - 130 ns

-11-ns

-75-ns

-37-ns

-61-ns

- - 150 ns

= 0V to 20V VDD = 50V,

- 90 108 nC
ID = 44A,
I

= 1.0mA

g(REF)

(Figures 13, 16, 17)

- 6.5 - nC

-17-nC

- 1700 - pF

- 460 - pF

- 145 - pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

Reverse Recovery Time t
Reverse Recovered Charge Q

2

SD

RR

ISD = 44A - - 1.25 V
ISD = 22A - - 1.00 V

rr

ISD = 44A, dISD/dt = 100A/µs - - 105 ns
ISD = 44A, dISD/dt = 100A/µs - - 305 nC

Typical Performance Curves

IRFP150N

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs

CASE TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

-5

10

-4

10

50

40

30

20

, DRAIN CURRENT (A)

D

I

20

150

0

25

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

VGS= 10V

50 75 100 125 150

TC, CASE TEMPERATURE (oC)

CASE TEMPERATURE

P

DM

t

1

t

NOTES:
DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

-1

10

θJC

10

0

2

x R

θJC

+ T

175

2

C

1

10

600

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

30

-5

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

3

TC = 25oC
FOR TEMPERATURES
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

0

10

C

150

1

10

Typical Performance Curves (Continued)

IRFP150N

300

100

10

OPERATION IN THIS

D

AREA MAY BE
LIMITED BY r

1

1

V

DS

, DRAIN CURRENT (A)
I

DS(ON)

10

, DRAIN TO SOURCE VOLTAGE (V)

SINGLE PULSE
TJ = MAX RATED

TC = 25oC

100µs

1ms

10ms

100

300

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

80

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 15V

V

DD

60

40

TJ = 175oC

DRAIN CURRENT (A)

D,

20

I

0

234 6

VGS, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

TJ = 25oC

5

300

100

, AVALANCHE CURRENT (A)

AS

I

10

10

0.001 0.01 0.1 1

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

STARTING TJ = 150oC

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPEDINDUCTIVE SWITCHING

CAPABILITY

80

60

40

, DRAIN CURRENT (A)

D

20

I

0

01 2 3 4

VGS = 20V

= 10V

V

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

T

= 25oC

C

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 7V
V

GS

VGS =5V

= 6V

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

3.0
PULSE DURATION =
DUTY CYCLE = 0.5% MAX

2.5

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)

80µs

VGS = 10V, ID = 44A

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

160

200

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-80 -40 0 40 80 120 200
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

4

VGS = VDS, ID = 250µA

160

Typical Performance Curves (Continued)

IRFP150N

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 200
T

, JUNCTION TEMPERATURE (oC)

J

160160

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

VDD = 50V

8

6

6000

1000

C

≅ CDS+ C

OSS

C, CAPACITANCE (pF)

100

30

0.1 1.0 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)

GD

VGS= 0V, f = 1MHz

C

= CGS + C

ISS

C

= C

RSS

GD

GD

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

, GATE TO SOURCE VOLTAGE (V)

GS

V

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

Test Circuits and Waveforms

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

4

WAVEFORMS IN

2

0

0

V

DS

I

AS

10 20 30 40 50

Q

, GATE CHARGE (nC)

g

L

+

V

DD

-

DUT

0.01Ω

DESCENDING ORDER:

ID = 44A

= 22A

I

D

0

BV

DSS

t

P

I

AS

t

AV

V

DS

V

DD

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

5

Test Circuits and Waveforms (Continued)

V

DS

R

L

V

GS

DUT

I

g(REF)

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

+

V

-

IRFP150N

DD

V

DD

VGS= 2V

0

I

g(REF)

0

Q

g(TOT)

V

DS

VGS= 20V

Q

g(10)

V

GS

Q

g(TH)

Q

gs

Q

gd

VGS = 10V

V

DS

R

L

V

GS

+

V

DD

-

V

DS

0

t

d(ON)

90%

t

ON

t

r

10%

DUT

R

GS

V

GS

V

GS

10%

0

50%

PULSE WIDTH

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

6

PSPICE Electrical Model

.SUBCKT IRFP150N 2 1 3 ; rev 15 Jan 2000

CA 12 8 2.70e-9
CB 15 14 2.70e-9
CIN 6 8 1.56e-9

IRFP150N

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 113.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1.0e-9

LGATE 1 9 6.5e-9
LSOURCE 3 7 2.3e-9

GATE

1

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.68e-2
RGATE 9 20 0.86
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.65e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD

LGATE

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

6
8

13

10

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

15

CB

CIN

-

+

-

5

51

5

51

21

MSTRO

14

5
8

RSLC1

+

ESLC

-

50
RDRAIN

16

8

MMED

DBREAK

11

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

SOURCE

S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*98),3.5))}
.MODEL DBODYMOD D (IS = 1.30e-12 IKF = 19 RS = 2.86e-3 XTI = 5 TRS1 = 2.25e-3 TRS2 = 1.00e-6 CJO = 1.90e-9 TT = 6.5e-8 M = 0.55)

.MODEL DBREAKMOD D (RS = 3.05e-1 IKF = 1 TRS1 = 8e-4 TRS2 = 3e-6)
.MODEL DPLCAPMOD D (CJO = 2.20e-9 IS = 1e-30 M = 0.83)
.MODEL MMEDMOD NMOS (VTO = 3.21 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.86)
.MODEL MSTROMOD NMOS (VTO = 3.58 KP = 37.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.81 KP = 0.07 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.60 )
.MODEL RBREAKMOD RES (TC1 =1.08e-3 TC2 = -8.6e-7)
.MODEL RDRAINMOD RES (TC1 = 7.70e-3 TC2 = 2.20e-5)
.MODEL RSLCMOD RES (TC1 = 4.25e-3 TC2 = 1.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.07e-3 TC2 = -6.65e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.20e-3 TC2 =9.67e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.2 VOFF= -2.4)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.4 VOFF= -6.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.8 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.8)

.ENDS

2

3

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

7

IRFP150N

SABER Electrical Model

REV 15 Jan 2000
template IRFP150N n2,n1,n3

electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.30e-12, cjo = 1.90e-9, tt = 6.5e-8, xti = 5, m = 0.55)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.20e-9, is = 1e-30, vj=1.0, m = 0.83)
m..model mmedmod = (type=_n, vto = 3.21, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.58, kp = 37.5, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.81, kp = 0.07, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2.4)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -6.2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8)

c.ca n12 n8 = 2.70e-9
c.cb n15 n14 = 2.70e-9
c.cin n6 n8 = 1.56e-9

d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 6.5e-9
l.lsource n3 n7 = 2.3e-9

GATE

LGATE

1

RLGATE

RGATE

9

EVTEMP
+

20

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1 = 1.08e-3, tc2 = -8.6e-7
res.rdbody n71 n5 = 2.86e-3, tc1 = 2.25e-3, tc2 = 1e-6

S1A

12

res.rdbreak n72 n5 = 3.05e-1, tc1 = 8e-4, tc2 = 3e-6
res.rdrain n50 n16 = 1.68e-2, tc1 = 7.70e-3, tc2 = 2.20e-5
res.rgate n9 n20 = 0.86
res.rldrain n2 n5 = 10

S1B

CA

res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e-6, tc1 = 4.25e-3, tc2 = 1.00e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.65e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -3.20e-3, tc2 = 9.67e-7
res.rvthres n22 n8 = 1, tc1 = -2.07e-3, tc2 = -6.65e-6

spe.ebreak n11 n7 n17 n18 = 113.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {

i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3.5))
}
}

10

-

6

ESG

8

+

-

18
22

13

14

8

13

13

+

+

EGS EDS

-

-

DPLCAP

RSLC2

EVTHRES

+

6

S2A

S2B

6
8

71

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

RDBODY

DBODY

LSOURCE

VBAT

5

RSLC1

51

ISCL

50
RDRAIN

21

-

19

8

MSTRO

CIN

15

CB

14

+

5
8

-

16

8

RDBREAK

MMED

8

72

DBREAK

11

MWEAK

EBREAK

+

17
18

-

RSOURCE

RBREAK

17 18

IT

RVTHRES

DRAIN

2

SOURCE

3

8

SPICE Thermal Model

REV 15 Jan 2000

IRFP150NT

CTHERM1 th 6 3.10e-3
CTHERM2 6 5 1.60e-2
CTHERM3 5 4 1.34e-2
CTHERM4 4 3 1.22e-2
CTHERM5 3 2 1.40e-2
CTHERM6 2 tl 1.05e-1

RTHERM1 th 6 1.20e-2
RTHERM2 6 5 3.50e-2
RTHERM3 5 4 5.20e-2
RTHERM4 4 3 1.45e-1
RTHERM5 3 2 2.62e-1
RTHERM6 2 tl 2.64e-1

IRFP150N

RTHERM1

RTHERM2

JUNCTION

th

CTHERM1

6

CTHERM2

5

SABER Thermal Model

SABER thermal model IRFP150NT
template thermal_model th tl

thermal_c th, tl
{
ctherm.ctherm1 th 6 = 3.10e-3
ctherm.ctherm2 6 5 = 1.60e-2
ctherm.ctherm3 5 4 = 1.34e-2
ctherm.ctherm4 4 3 = 1.22e-2
ctherm.ctherm5 3 2 = 1.40e-2
ctherm.ctherm6 2 tl = 1.05e-1

rtherm.rtherm1 th 6 = 1.20e-2
rtherm.rtherm2 6 5 = 3.50e-2
rtherm.rtherm3 5 4 = 5.20e-2
rtherm.rtherm4 4 3 = 1.45e-1
rtherm.rtherm5 3 2 = 2.62e-1
rtherm.rtherm6 2 tl = 2.64e-1
}

RTHERM3

RTHERM4

RTHERM5

RTHERM6

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

CASE

tl

9

TO-247

3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE

IRFP150N

E

Q

ØR

D

A

ØS

TERM. 4

ØP

SYMBOL

A 0.180 0.190 4.58 4.82 -

b 0.046 0.051 1.17 1.29 2, 3

b

1

b

2

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

0.060 0.070 1.53 1.77 1, 2

0.095 0.105 2.42 2.66 1, 2

c 0.020 0.026 0.51 0.66 1, 2, 3

D 0.800 0.820 20.32 20.82 -

L

1

L

b

1

b

2

c

b

2

1

e

3

e

1

J

1

3

BACK VIEW

2

1

E 0.605 0.625 15.37 15.87 -

e 0.219 TYP 5.56 TYP 4

e

1

J

1

0.438 BSC 11.12 BSC 4

0.090 0.105 2.29 2.66 5

L 0.620 0.640 15.75 16.25 -

L

1

0.145 0.155 3.69 3.93 1

ØP 0.138 0.144 3.51 3.65 -

Q 0.210 0.220 5.34 5.58 ­ØR 0.195 0.205 4.96 5.20 ­ØS 0.260 0.270 6.61 6.85 -

NOTES:

1. Lead dimension and finish uncontrolled in L1.

2. Lead dimension (without solder).

3. Add typically 0.002 inches (0.05mm) for solder coating.

4. Positionoflead to bemeasured0.250inches (6.35mm) from bottom
of dimension D.

5. Positionoflead to bemeasured0.100inches (2.54mm) from bottom
of dimension D.

6. Controlling dimension: Inch.

7. Revision 1 dated 1-93.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringementsof patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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TEL: [phone]
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10

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