Intersil IRF131, IRF130, IRF133, IRF132 Datasheet

IRF130

Data Sheet March 1999

14A, 100V, 0.160 Ohm, N-Channel
Power MOSFET

This N-Channel enhancementmode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdownavalanchemodeof operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.

Formerly developmental type TA17411.

Ordering Information

PART NUMBER PACKAGE BRAND

IRF130 TO-204AA IRF130

NOTE: When ordering, use the entire part number .

File Number

Features

• 14A, 100V

•r

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

= 0.160Ω

DS(ON)

Components to PC Boards”

Symbol

D

G

1566.4

Packaging

DRAIN
(FLANGE)

JEDEC TO-204AA

GATE (PIN 1)

S

SOURCE (PIN 2)

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

IRF130

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

IRF130 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

TC= 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DS

D
D

DM

GS

D

100 V
100 V

14

9.9
56 A

±20 V

79 W

A
A

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.53 W/oC

Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

AS

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

50 mJ

-55 to 175

300
260

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VDS

Zero Gate Voltage Drain Current I

On-State Drain Current (Note 2) I

D(ON)VDS

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Forward Transconductance (Note 2) g
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge

Q

g(TOT)VGS

(Gate to Source + Gate to Drain)
Gate to Source Charge Q
Gate to Drain “Miller” Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Internal Drain Inductance L

Internal Source Inductance L

Thermal Resistance, Junction to Case R
Thermal Resistance, Junction to Ambient R

DSSID

DSS

GSS

ts

r

f

gs
gd

ISS
OSS
RSS

D

S

θJC

θJA

= 250µA, VGS = 0V (Figure 10) 100 - - V

= VGS, ID = 250µA 2.0 - 4.0 V
VDS = Rated BV
VDS = 0.8 x Rated BV

> I

D(ON)

, VGS = 0V - - 25 µA

DSS

, VGS = 0V, TJ = 150oC - - 250 µA

DSS

x r

DS(ON)MAX

, VGS = 10V 14 - - A

VGS = ±20V - - ±100 nA

= 8.3A, VGS = 10V (Figures 8, 9) - 0.12 0.16 Ω
VDS≥ 50V, ID = 8.3A (Figure 12) 4.6 6.9 - S
VDD = 50V, ID≈ 14A, RG = 12Ω, RL = 3.5Ω

(Figures 17, 18) MOSFET Switching Times are
Essentially Independent of Operating Temperature

- - 30 ns

- - 75 ns

- - 40 ns

- - 45 ns

= 10V, ID = 14A, VDS = 0.8 x Rated BV

I

= 1.5mA (Figures 14, 19, 20) Gate Charge is

g(REF)

Essentially Independent of Operating Temperature

DSS

,

-1826nC

- 5.5 - nC

-11-nC

VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 600 - pF

- 300 - pF

- 100 - pF

Measured between the
Contact Screw on the
Flange that is Closer to
Source and Gate Pins and
the Center of Die

Measured from the Source
Lead, 6mm (0.25in) from
the Flange and the Source
Bonding Pad

Modified MOSFET
Symbol Showing the
Internal Device
Inductances

D

L

D

G

L

S

S

- 5.0 - nH

- 12.5 - nH

- - 1.9oC/W

Free Air Operation - - 30

o

C/W

2

IRF130

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I
Pulse Source to Drain Current (Note 3) I

Source to Drain Diode Voltage (Note 2) V

SD

SDM

SD

Reverse Recovery Time t
Reverse Recovery Charge Q

RR

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD = 50V, starting TJ = 25oC, L = 380µH, RG = 25Ω, peak IAS = 14A. See Figures 15, 16.

Modified MOSFET
Symbol Showing the
Integral Reverse P-N

D

- - 14 A

- - 56 A

Junction Diode

G

S

TJ = 25oC, ISD = 14A, VGS = 0V (Figure 13) - - 2.5 V
TJ = 25oC, ISD = 14A, dISD/dt = 100A/µs 55 120 250 ns

rr

TJ = 25oC, ISD = 5.5A, dISD/dt = 100A/µs 0.26 0.58 1.3 µC

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

25 50 75 100 125 150 1750

T

, CASE TEMPERATURE (oC)

C

Unless Otherwise Specified

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

10

C)

o

1.0

0.5

15

12

9

6

, DRAIN CURRENT (A)

D

I

3

0

25 50 75 100 125 150 175

T

, CASE TEMPERATURE (oC)

C

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

0.1

, THERMAL IMPEDANCE (

θJC

Z

-2

10

10

-5

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

P

DM

t

1

t

θJC

1/t2

2

+ T

C

10

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-4

10

-3

10

t1, RECTANGULAR PULSE DURATION (s)

-2

10

0.1 1

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

3

IRF130

Typical Performance Curves

3

10

2

10

10

, DRAIN CURRENT (A)

TJ = MAX RATED

D

1

I

= 25oC

T

C

0.1
110

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

Unless Otherwise Specified (Continued)

10µs
100µs

1ms

10ms

DC

2

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

25

80µs PULSE TEST

20

15

VGS = 8V

VGS = 10V

VGS = 7V

VGS = 6V

25

8V

20

15

10

, DRAIN CURRENT (A)

D

I

5

3

10

0

010203040

10V

80µs PULSE TEST

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

VGS = 7V

6V

5V

4V

50

FIGURE 5. OUTPUT CHARACTERISTICS

2

10

VDS≥ 50V
80µs PULSE TEST

10

10

1

, DRAIN CURRENT (A)

D

I

5

0

0.0 1.0 2.0 3.0 4.0 5.0
V

, DRAIN TO SOURCE VOLTAGE (V)

DS

VGS = 5V

VGS = 4V

, DRAIN CURRENT (A)

D

I

0.1

TJ = 175oC

TJ = 25oC

0246810

, GATE TO SOURCE VOLTAGE (V)

V

GS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

1.5

80µs PULSE TEST

1.2

0.9

0.6

0.3

DRAIN TO SOURCE ON RESISTANCE

0.0
01224364860

I

, DRAIN CURRENT (A)

D

VGS = 10V

VGS = 20V

3.0
ID = 14A

V

= 10V

GS

2.4

1.8

1.2

ON RESISTANCE

0.6

NORMALIZED DRAIN TO SOURCE

0.0

-60 0 60 120 180
T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

4

FIGURE 9. NORMALIZED DRAIN TOSOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

IRF130

Typical Performance Curves

1.25
ID = 250µA

1.15

1.05

0.95

BREAKDOWN VOLTAGE

0.85

NORMALIZED DRAIN TO SOURCE

0.75

-60 0 60 120 180
TJ, JUNCTION TEMPERATURE (oC)

Unless Otherwise Specified (Continued)

FIGURE 10. NORMALIZED DRAINTO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

VDS 50V
80µs PULSE TEST

8

6

4

, TRANSCONDUCTANCE (S)

2

fs

g

TJ = 25oC

TJ = 175oC

1500

1200

900

600

C, CAPACITANCE (pF)

300

0

110

C

RSS

25 25

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

VGS = 0V, f = 1MHz

= CGS + C

C

ISS

C

= C

RSS

ISS

OSS

≈ C

GD
DS

C

C

C

OSS

+ C

GD

GD

10

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

3

10

2

10

10

TJ = 175oC

, DRAIN CURRENT (A)

1

SD

I

TJ = 25oC

2

0

5101520250

ID, DRAIN CURRENT (A)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT

20

ID = 14A
FOR TEST CIRCUIT
SEE FIGURE 18

16

12

8

4

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 6 12 18 24 30

Q

g(TOT)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

0.1
0

FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

VDS = 50V

VDS = 20V

, TOTAL GATE CHARGE (nC)

0.4
VSD, SOURCE TO DRAIN VOLTAGE (V)

VDS = 80V

1.2 1.6 2.00.8

5

Test Circuits and Waveforms

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

IRF130

V

DS

BV

DSS

L

+

V

DD

-

DUT

I

AS

0

0.01Ω

t

P

I

AS

t

AV

V

DS

V

DD

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT

R

L

R

G

+

V

DD

-

FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

d(ON)

t

V

DS

0

r

90%

10%

DUT

V

GS

V

GS

10%

0

50%

PULSE WIDTH

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

V

DS

(ISOLATED
SUPPLY)

SAME TYPE
AS DUT

V

DD

Q

g(TOT)

Q

gd

Q

gs

12V

BATTERY

0.2µF

50kΩ

CURRENT

REGULATOR

0.3µF

t

d(OFF)

90%

V

GS

t

OFF

50%

t

f

90%

10%

D

V

DS

S

CURRENT

I

D

SAMPLING

DUT

0

V

DS

I

G(REF)

0

G

I

0

g(REF)

IG CURRENT

SAMPLING

RESISTOR RESISTOR

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

6

IRF130

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Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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