intersil ICM7243 DATA SHEET

®

ICM7243

Data Sheet FN3162.3October 28, 2005

8-Character, Microprocessor­Compatible, LED Display Decoder Driver

The ICM7243 is an 8-character, alphanumeric display driver
and controller which provides all the circuitry required to
interface a microprocessor or digital system to a 14-segment
or 16-segment display. It is primarily intended for use in
microprocessor systems, where it minimizes hardware and
software overhead. Incorporated on-chip are a 64-character
ASClI decoder, 8 x 6 memory, high power character and
segment drivers, and the multiplex scan circuitry.

6-bit ASCll data to be displayed is written into the memory
directly from the microprocessor data bus. Data location
depends upon the selection of either Sequential
(MODE = 1) or Random access mode (MODE = 0). In the
Sequential Access mode the first entry is stored in the
lowest location and displayed in the “left-most” character
position. Each subsequent entry is automatically stored in
the next higher location and displayed to the immediate
“right” of the previous entry. A DISPlay FULL signal is
provided after 8 entries; this signal can be used for
cascading devices together. A CLeaR
clear the memory and reset the location counter. The
Random Access mode allows the processor to select the
memory address and display digit for each input word.

pin is provided to

Features

• 14-Segment and 16-Segment Fonts with Decimal Point

• Mask Programmable for Other Font-Sets Up to 64
Characters

• Microprocessor Compatible

• Directly Drives LED Common Cathode Displays

• Cascadable Without Additional Hardware

• Standby Feature Turns Display Off; Puts Chip in Low
Power Mode

• Sequential Entry or Random Entry of Data Into Display

• Single +5V Operation

• Character and Segment Drivers, All MUX Scan Circuitry, 8
x 6 Static Memory and 64-Character ASCll Font Generator
Included On-Chip

• Pb-Free Plus Anneal Available (RoHS Compliant)

The character multiplex scan runs whenever data is not
being entered. It scans the memory and CHARacter drivers,
and ensures that the decoding from memory to display is
done in the proper sequence. Intercharacter blanking is
provided to avoid display ghosting.

Ordering Information

PART NUMBER

ICM7243BlPL ICM7243BlPL -25°C to 85°C 40 Ld PDIP E40.6

ICM7243BlPLZ (See Note) ICM7243BlPLZ -25°C to 85°C 40 Ld PDIP (Pb-free) E40.6

ICM7243AIM44Z (See Note) ICM7243AIM44Z -25°C to 85°C 44 Ld MQFP (Pb-free) Q44.10x10

ICM7243AIM44ZT (See Note) ICM7243AIM44Z -25°C to 85°C 44 Ld MQFP (Tape and Reel)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART MARKING

TEMP. RANGE (°C) PACKAGE PKG. DWG. #

Q44.10x10

(Pb-free)

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Pinouts

ICM7243ICM7243

ICM7243B (14-SEGMENT CHARACTER)

(PDIP, CERDIP)

TOP VIEW

1

V

DD

SEG e

SEG g1

SEG k
SEG c
SEG d
SEG a

D0
D1
D2
D3
D4
D5
CS
CS
CS

WR
CHAR 8
CHAR 7
CHAR 6

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

m

SEG
SEG l
SEG g2
SEG b
SEG i
SEG f
DP

h

SEG
SEG j
MODE
A0/SEN
A1/CLR
A2/DISP FULL
OSC/OFF
CHAR 1
CHAR 2
CHAR 3
CHAR 4
V

SS

CHAR 5

SEG d1
SEG a1
SEG

a2

D0

D1

D2

D3

D4

D5

CS

NC

ICM7243A (16-SEGMENT CHARACTER)

(MQFP)

TOP VIEW

DD

V

SEG l

SEG g2

SEG b

SEG i

CHAR3

CHAR2

SEG f

33

32

31

30

29

28

27

26

25

24

23

2221201918

NC

SEG c

SEG k

SEG g1

SEG e

44 43 42 41 40

1

2

3

4

5

6

7

8

9

10

11

12 13 14 15 16 17

NC

WR

CHAR8

CHAR7

SEG m

39 38 37 36 35 34

SS

V

CHAR6

CHAR5

CHAR4

SEG d2

DP

SEG h
SEG j

MODE

A0/SEN
A1/CLR
A2/DISP FULL
OSC/OFF

CHAR1

NC

2

FN3162.3

October 28, 2005

Functional Block Diagram

ICM7243ICM7243

(NOTE 1)

MODE

A0/SEN

A1/CLR

A2/DISP FULL

DATA INPUT

D0 - D5

WR

CS

CS
CS

CL

D

SEL

MUX

DATA

D

LATCHES

CL

CL

D

ADDRESS

LATCHES

CL

D

CONTROL

LATCH

Q

Q

8 x 6

D1

DATA

MEMORY

CLR

CL

ADR

ONE

SHOT

CL

EN

SEQUENTIAL

SEQUENTIAL

ADDRESS

COUNTER

CLR

OVERFLOW

D0

8

3

3

ROM

(NOTE 1)

SEL

ADDRESS

MULITPLEXER

MULTIPLEXER

AND

DECODER

64 x 17

6

17

(NOTE 1)

8

SEGMENT

DRIVERS

8

CHARACTER

CHARACTER

DRIVERS

SEGMENT
OUTPUTS
SEG x

CHAR N
CHARACTER
OUTPUTS

OSC/OFF

NOTE:

1. ICM7243A has only one CS and no CS
ICM7243B has 15 Segments.

OSCILLATOR

MULTIPLEX

OSCILLATOR

.

CHARACTER

MULTIPLEX

COUNTER

3

INTER-CHARACTER BLANKING

3

FN3162.3

October 28, 2005

ICM7243ICM7243

Absolute Maximu m Ratings Thermal Information

Supply Voltage VDD - VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V

Input Voltage (Any Terminal). . . . . . . . . . . V

CHARacter Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA

+0.3V to VSS -0.3V

DD

SEGment Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ

is measured with the component mounted on an evaluation PC board in free air.

JA

Thermal Resistance (Typical, Note 1) θ

(°C/W) θJC (°C/W)

JA

PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A

MQFP Package . . . . . . . . . . . . . . . . . . 70 N/A

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(MQFP - Lead Tips Only)

Electrical Specifications V

= 5V, VSS = 0V, TA = 25°C, Unless Otherwise Specified

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DC CHARACTERISTICS

Supply Voltage (V

Operating Supply Current, I

Quiescent Supply Current, I

Input High Voltage, V

Input Low Voltage, V

Input Current, I

CHARacter Drive Current, I

CHARacter Leakage Current, I

SEGment Drive Current, I

SEGment Leakage Current, I

DISPlay FULL Output Low, V

DISPlay FULL Output High, V

Display Scan Rate, f

IN

- VSS), V

DD

IH

IL

DS

DD

CHAR

SEG

SUPP

STBY

CHLK

SLK

OL

OH

V

= 5.25V, 10 Segments ON, All 8 Characters - 180 - mA

SUPP

V

= 5.25V, OSC/OFF Pin < 0.5V, CS = V

SUPP

V

SUPP

V

SUPP

= 5V, V

= 5V, V

= 1V 140 190 - mA

OUT

= 2.5V 14 19 - mA

OUT

SS

IOL = 1.6mA - - 0.4 V

lIH = 100µA2.4--V

Electrical Specifications Drive levels 0.4V and 2.4V, timing measured at 0.8V and 2.0V. V

Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

AC CHARACTERISTICS

WR

, CLeaR Pulse Width Low, t

WR

, CLeaR Pulse Width High (Note 1), t

Data Hold Time, t

Data Setup Time, t

Address Hold Time, t

Address Setup Time, t

CS, CS

Setup Time, t

DH

DS

AH

AS

CS

Pulse Transition Time, t

SEN Setup Time, t

Display Full Delay, t

SEN

WDF

WPI

WPH

T

4.75 5.0 5.25 V

- 30 250 µA

2- -V

--0.8V

-10 - +10 µA

- - 100 µA

-0.0110µA

- 400 - Hz

= 5V, TA = 25°C,

DD

300 250 - ns

- 250 - ns

0 -100 - ns

250 150 - ns

125 - - ns

40 15 - ns

0--ns

--100ns

0-25- ns

700 480 - ns

Capacitance

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Input Capacitance, C

Output Capacitance, C

NOTES:

1. In Sequential mode WR

2. For design reference only, not tested.

lN

O

high must be ≥ T

4

(Note 2) - 5 - pF

(Note 2) - 5 - pF

+T

WDF

.

SEN

FN3162.3

October 28, 2005

Timing Waveforms

CS

CS

ADDRESS

WRITE

DATA

ICM7243ICM7243

t

CS

t

AH

t

AS

VAL ID

t

WC

t

WPI

t

t

T

DS

VAL ID

FIGURE 1. RANDOM ACCESS TIMING

t

DH

t

t

T

WHP

WR

CLEAR

SEN

DISPLAY FULL

INTERNAL

INTER-CHARACTER

BLANKING

SIGNAL

CHAR 1

CHAR 2

CHAR 3

CHAR

12

t

SEN

CHAR

CHAR

FIGURE 2. SEQUENTIAL ACCESS MODE TIMING (MODE = 1)

~5µs

~300µs

8

t

WPH

t

WDF

CHARACTERS

DRIVE

SIGNALS

CHAR 4

CHAR 5

CHAR 6

CHAR 7

CHAR 8

FIGURE 3. DISPLAY CHARACTERS MULTIPLEX TIMING DIAGRAM

5

INTER-CHARACTER BLANKING

FN3162.3

October 28, 2005

Performance Curves

30

ICM7243ICM7243

VDD = 5.5V

20

(mA)

SEG

I

10

0

012 3

SEGMENT VOLTAGE (V)

5.0V

4.5V

500

400

(mA)

300

CHAR

I

200

100

012 3

VDD = 5.5V

5.0V

4.5V

SEGMENT VOLTAGE (V)

FIGURE 4. SEGMENT CURRENT vs OUTPUT VOLTAGE FIGURE 5. CHARACTER CURRENT vs OUPUT VOLTAGE

Pin Descriptions

SIGNAL PIN FUNCTION

ICM7243A(B)

D0 - D5 10 - 15

(8 - 13)

Six-Bit ASCll Data input pins (active high).

CS, CS

16

Chip Select from µP address decoder, etc.

(14 - 16)

WR

17 WRite pulse input pin (active low). For an active high write pulse, CS can be used, and WR can be used

as CS

.

MODE 31 Selects data entry MODE. High selects Sequential Access (SA) mode where first entry is displayed in

“leftmost” character and subsequent entries appear to the “right”. Low selects the Random Access
(RA) mode where data is displayed on the character addressed via A0 - A2 Address pins.

A0/SEN 30 In RA mode it is the LSB of the character Address. In SA mode it is used for cascading devices for

displays of more than 8 characters (active high enables device controller).

A1/CLeaR

29 In RA mode this is the second bit of the address. In SA mode, a low input will CLeaR the Serial Address

Counter, the Data Memory and the display.

A2/DISPlay FULL 28 In

RA mode this is the MSB of the Address. In SA mode, the output goes high after eight entries,

indicating DISPlay FULL.

OSC/OFF

27 OSCillator input pin. Adding capacitance to VDD will lower the internal oscillator frequency. An external

oscillator can be applied to this pin. A low at this input sets the device into a (shutdown) mode, shutting
OFF the display and oscillator but retaining data stored in memory.

SEG a - SEG m, DP2 - 9, 32 - 40

SEGment driver outputs.

(2 - 7), (32 - 40)

CHARacter 1 - 8 18 - 21,

CHARacter driver outputs.

23 - 26

6

FN3162.3

October 28, 2005

Test Circuit

ICM7243ICM7243

17 SEGMENTS

CHAR 8

V

1

DD

SEG m

SEG

SEG g1

SEGMENTS

V

DD

SEG k

SEG c
SEG d1
SEG a1
SEG a2

CHAR 8
CHAR 7
CHAR 6

D0
D1
D2
D3
D4
D5

CS

WR

2

e

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

ICM7243A

CHAR 7 CHAR 6 CHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1

l

SEG

40

SEG g2

39

SEG b

38

SEG i

37

SEG f

36

SEG d2

35

DP

34

SEG

33

SEG j

32

MODE (SA/RA)

31

A0/SEN

30

A1/CLR

29

A2/DISP FULL

28

OSC/OFF

27

CHAR 1

26

CHAR 2

25

CHAR 3

24

CHAR 4

23

V

SS

22
21

CHAR 5

SEGMENTS

h

8 CHARACTERS

V

NC (FOR SA MODE)

V

DD

DISPLAY
FULL
OUTPUT

DD

FIGURE 6.

7

FN3162.3

October 28, 2005

Typical Applications

ICM7243ICM7243

8 CHARACTERS 8 CHARACTERS

RRI

DRR

OUT

ICL7555

DELAY

IM6403

UART

+5V

+

V

TR

TH

RBR8

RBR7

RBR1 - RBR6

DR

20K

200pF

+5V

6 BIT BUS

+5V +5V

CHAR

CLR

CS

SEN

CS

CS

SEN

CS

CLR

ICM7243B

,WR

D0 - D5 CS

D0 - D5 WR

ICM7243B

CHAR

SEG

CS

SEG

DISP

FULL

WR

DISP

FULL

CHAR

CLR

CS

SEN

,WR

CS

D0 - D5 CS

D0 - D5

CS

SEN

CS

CLR

CHAR

ICM7243B

ICM7243B

SEG

CS

SEG

DISP

FULL

DISP

FULL

ETC.

ETC.

8 CHARACTERS 8 CHARACTERS

FIGURE 7. DRIVING TWO ROWS OF CHARACTERS FROM A SERIAL INPUT

8

FN3162.3

October 28, 2005

Typical Applications (Continued)

ICM7243ICM7243

8-CHARACTER LED DISPLAY

CLR

DATA

BUS

WR

(CS

CS,

(WR)

6

,

)

+5V SEN

+5V

CLR

MODE

WR

D0 - D5

FIRST 8 CHARACTERS SECOND 8 CHARACTERS NTH 8 CHARACTERS

CHAR

DISP FULL

CS

NOTE: 17 for ICM7243A, 15 for ICM7243B.

FIGURE 8. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE

SEG

V

DD

V

SS

8-CHARACTER LED DISPLAY 8-CHARACTER LED DISPLAY

8

NOTE

CLR

SEN

+5V

+5V

6

MODE

WR

D0 - D5

DISP FULL

CS

88

NOTE NOTE

CHAR

SEG

V

DD

V

+5V

+5V

SS

6

CLR

SEN
MODE

WR

D0 - D5

DISP FULL

CS

CHAR

SEG

V

DD

V

SS

+5V

+5V

100Ω

1mA

SEG

ICM7243

CHAR

= 4Ω

R

ON

GND

14mA

+5V

2N2219

14Ω (100mA

2N6034

GND

1.4A

PEAK

PEAK

1K

1K

1K

+5V

1.4A

PEAK

2N6034

25Ω

(100mA

2N2219

GND

PEAK

)

+5V

100Ω

SEG

)

ICM7243

= 4Ω

R

ON

CHAR

GND

+5V

300Ω

GND

FIGURE 9A. COMMON CATHODE DISPLAY FIGURE 9B. COMMON ANODE DISPLAY

FIGURE 9. DRIVING LARGE DISPLAYS

9

FN3162.3

October 28, 2005

Typical Applications (Continued)

8 CHARACTERS 8 CHARACTERS 8 CHARACTERS 8 CHARACTERS

ICM7243A/B ICM7243A/B ICM7243A/B ICM7243A/B

P22

P21

80C35
80C48

WR

P20

DB7

DB6

DB5 - DB0

6 BIT BUS

FIGURE 10. RANDOM ACCESS 32-CHARACTER DISPLAY IN A 80C48 SYSTEM

ICM7243ICM7243

CS A2 A1 A0 D0 - D5 WR CS A2 A1 A0 D0 - D5 WR CS A2 A1 A0 D0 - D5 WRCS A2 A1 A0 D0 - D5 WR

Display Font and Segment Assignments

a1

f

g1 g2

e

d2 d1

00

01

D5, D410

11

hji

a2

kml

b

c

DP

D30000000011111111

D20000111100001111

D10011001100110011

D00101010101010101

FIGURE 11. ICM7243A 16-SEGMENT CHARACTER FONT WITH DECIMAL POINT

10

FN3162.3

October 28, 2005

ICM7243ICM7243

Display Font and Segment Assignments (Continued)

00

01

D5, D410

11

D30000000011111111

a1

f

hji

f

hji

g1 g2

g1 g2

e

e

d2 d1

a2

a

b

b

kml

c

km

d1

c

DP

l

d

D20000111100001111

D10011001100110011

D00101010101010101

NOTE: Segments a and d appear as 2 segments each, but both halves are driven together.

FIGURE 12. ICM7243B 14-SEGMENT CHARACTER FONT WITH DECIMAL POINT

V

DRIVER

~ 4ÞΩ

DD

= 1.6V

V

LED

R

R

SEG x DISPLAY

CHAR N SEGMENT LEDs

V

SS

TYPICAL

= 100µ

SEGMENT

DRIVER

CHARACTER

R

DS(ON)

FIGURE 13. SEGMENT AND CHARACTER DRIVERS OUTPUT CIRCUIT

11

FN3162.3

October 28, 2005

Detailed Description

ICM7243ICM7243

WR, CS, CS - These pins are immediately functionally
ANDed, so all actions described as occurring on an edge of
WR

, with CS and CS enabled, will occur on the equivalent
(last) enabling or (first) disabling edge of any of these
inputs. The delays from CS pins are slightly (about 5ns)
greater than from WR

or CS due to the additional inverter

required on the former.

MODE - The MODE pin input is latched on the falling edge
of WR

(or its equivalent, see above). The location (in Data
Memory) where incoming data will be placed is determined
either from the Address pins or the Sequential Address
Counter. This is controlled by MODE input. MODE also
controls the function of A0/SEN, A1/CLR

, and A2/DlSPlay

FULL lines.

Random Access Mode - When the internal mode latch is
set for Random Access (RA) (MODE latched low), the
Address input on A0, A1 and A2 will be latched by the
falling edge of WR

(or its equivalent). Subsequent changes
on the Address lines will not affect device operation. This
allows use of a multiplexed 6-bit bus controlling both
address and data, with timing controlled by WR

.

Sequential Access Mode - If the internal latch is set for
Sequential Access (SA), (MODE latched high), the Serial

ENable input or SEN will be latched on the falling edge of
WR

(or its equivalent). The CLR input is asynchronous, and
will force-clear the Sequential Address Counter to address
000 (CHARacter 1), and set all Data Memory contents to
100000 (blank) at any time. The DISPlay FULL output will
be active in SA mode to indicate the overflow status of the
Sequential Address Counter. If this output is low, and SEN
is (latched) high, the contents of the Counter will be used to
establish the Data Memory location for the Data input. The
Counter is then incremented on the rising edge of WR

. If
SEN is low, or DISPlay FULL is high, no action will occur.
This allows easy “daisy-chaining” of display drivers for
multiple character displays in a Sequential Access mode.

Changing Modes - Care must be exercised in any
application involving changing from one mode to another.
The change will occur only on a falling edge of WR (or its
equivalent). When changing mode from Sequential
Access to Random Access, note that A2/DlSPlay FULL
will be an output until WR has fallen low, and an Address
drive here could cause a conflict. When changing from
Random Access to Sequential Access, A1/CLR should
be high to avoid inadvertent clearing of the Data Memory
and Sequential Address Counter. DISPlay FULL will
become active immediately after the rising edge of WR.

Data Entry - The input Data is latched on the rising edge of
WR

(or its equivalent) and then stored in the Data Memory
location determined as described above. The six Data bits
can be multiplexed with the Address information on the
same lines in Random Access mode. Timing is controlled
by the WR

input.

OSC/OFF - The device includes a relaxation oscillator with
an internal capacitor and a nominal frequency of 200kHz.
By adding external capacitance to V

at the OSC/OFF

DD

pin, this frequency can be reduced as far as desired.
Alternatively, an external signal can be injected on this pin.
The oscillator (or external) frequency is pre-divided by 64,
and then further divided by 8 in the Multiplex Counter, to
drive the CHARacter drive lines (see Figure 3). An inter­character blanking signal is derived from the pre-divider. An
additional comparator on the OSC/OFF

input detects a
level lower than the relaxation oscillator's range, and
blanks the display, disables the DISPlay FULL output (if
active), and clears the pre-divider and Multiplex Counter.
This puts the circuit in a low-power-dissipation mode in
which all outputs are effectively open circuits, except for
parasitic diodes to the supply lines. Thus a display
connected to the output may be driven by another circuit
(including another ICM7243) without driver conflicts.

Display Output - The output of the Multiplex Counter is
decoded and multiplexed into the address input of the Data
Memory, except during WR

operations (in Sequential
Access mode, with SEN high and DISPlay FULL low),
when it scans through the display data. The address
decoder also drives the CHARacter outputs, except during
the inter-character blanking interval (nominally about 5µs).
Each CHARacter output lasts nominally about 300µs, and
is repeated nominally every 2.5ms, i.e., at a 400Hz rate
(times are based on internal oscillator without external
capacitor).

The 6 bits read from the Data Memory are decoded in the
ROM to the 17 (15 for ICM7243B) segment signals, which
drive the SEGment outputs. Both CHARacter and
SEGment outputs are disabled during WR

operations (with
SEN high and DISPlay FULL Low for Sequential Access
mode). The outputs may also be disabled by pulling
OSC/OFF

low.

The decode pattern from 6 bits to 17 (15) segments is done
by a ROM pattern according to the ASCll font shown.
Custom decode patterns can be arranged, within these
limitations, by consultation with the factory.

12

FN3162.3

October 28, 2005

Dual-In-Line Plastic Packages (PDIP)

ICM7243ICM7243

N

D1

-C-

E1

-B-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

12 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be

7. e

e

perpendicular to datum .

A

and eC are measured at the lead tips with the leads

B

unconstrained. e

-C-

must be zero or greater.

C

8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A-0.250 - 6.35 4
A1 0.015 - 0.39 -4
A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 ­D 1.980 2.095 50.3 53.2 5

D1 0.005 - 0.13 -5

E 0.600 0.625 15.24 15.87 6

E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.600 BSC 15.24 BSC 6

- 0.700 - 17.78 7

L 0.115 0.200 2.93 5.08 4

N40 409

NOTESMIN MAX MIN MAX

Rev. 0 12/93

13

FN3162.3

October 28, 2005

ICM7243ICM7243

Metric Plastic Quad Flatpack Packages (MQFP)

E

E1

0.40

0.016

0o MIN

0o-7

-H-

-A-

o

MIN

D

D1

-D-

Q44.10x10 (JEDEC MS-022AB ISSUE B)

44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

INCHES MILLIMETERS

SYMBOL

NOTESMIN MAX MIN MAX

A-0.096 - 2.45 -

A1 0.004 0.010 0.10 0.25 -

-B-

A2 0.077 0.083 1.95 2.10 -

b 0.012 0.018 0.30 0.45 6

b1 0.012 0.016 0.30 0.40 -

D 0.515 0.524 13.08 13.32 3

D1 0.389 0.399 9.88 10.12 4, 5

E 0.516 0.523 13.10 13.30 3

e

E1 0.390 0.398 9.90 10.10 4, 5

L 0.029 0.040 0.73 1.03 -

PIN 1

A

SEATING

PLANE

N44 447

e 0.032 BSC 0.80 BSC -

Rev. 2 4/99

NOTES:

12o-16

A2

0.076

o

A1

0.20

0.008

A-B SD SCM

0.003

-C-

b

b1

1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.

2. All dimensions and tolerances per ANSI Y14.5M-1982.

3. Dimensions D and E to be determined at seating plane .

-C-

4. Dimensions D1 and E1 to be determined at datum plane

.

-H-

5. Dimensions D1 and E1 do not include mold protrusion.

0.13/0.17

o

L

12o-16

0.005/0.007

BASE METAL

WITH PLATING

0.13/0.23

0.005/0.009

Allowable protrusion is 0.25mm (0.010 inch) per side.

6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.

7. “N” is the number of terminal positions.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

14

FN3162.3

October 28, 2005