INTERSIL ICM 7242 Datasheet

®

ICM7242

Data Sheet FN2866.4February 9, 2007

Long Range Fixed Timer

The ICM7242 is a CMOS timer/counter circuit consisting of
an RC oscillator followed by an 8-bit binary counter. It will
replace the 2242 in most applications, with a sign ificant
reduction in the number of external components.

Three outputs are provided. They are the oscillator output,
and buffered outputs from the first and eighth counters.

Ordering Information

PART

PART NUMBER

ICM7242IPA 7242 IPA -25 to +85 8 Ld PDIP E8.3
ICM7242IPAZ

(See Note)
ICM7242CBAZ* 7242 CBAZ 0 to +70 8 Ld SOIC

ICM7242IBAZ* 7242 IBAZ -25 to +85 8 Ld SOIC

*Add “-T” suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing
applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020

MARKING

7242 IPAZ -25 to +85 8 Ld PDIP**

TEMP.

RANGE (°C) PACKAGE

(Pb-free)

(Pb-free)

(Pb-free)

PKG.

DWG. #

E8.3

M8.15

M8.15

Features

• Replaces the 2242 in Most Applications

• Timing From Microseconds to Days

• Cascadable

• Monostable or Astable Operation

• Wide Supply Voltage Range . . . . . . . . . . . . . . .2V to 16V

• Low Supply Current . . . . . . . . . . . . . . . . . . . . 115µA at 5V

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinout

ICM7242

(8 LD PDIP, SOIC)

TOP VIEW

V

DD

÷2 OUT

÷128/256 OUT

V

SS

1

2

3

4

8

TB I/O

7

RC

6

TRIGGER

5

RESET

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 1996, 2005, 2007. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

ICM7242

Functional Block Diagram

R

1

50k

+

R

2

86k

7

R

3

RC

50k

1 4 8 5 6 2 3

V

DD

-

+

-

V

SS

R

Q

S

Q

R

CL

Q

Q

S

CL

CL

Q

Q

S

Q

Q

S

CL

CL

Q

Q

S

Q

Q

S

Q

CL

Q

S

Q

CL

Q

S

TRIGGERRESET ÷2 OUTTB I/O

CL

S

Q

Q

÷128/256
OUTPUT

2

FN2866.4

February 9, 2007

ICM7242ICM7242

Absolute Maximum Ratings Thermal Information

Supply Voltage (VDD to VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . .18V

Input Voltage (Note 1)

Terminals (Pins 5, 6, 7, 8). . . . . . . . . . (V

-0.3V) to (VDD +0.3V)

SS

Continuous Output Current (Each Output). . . . . . . . . . . . . . . . 50mA

Operating Conditions

Temperature Range

ICM7242I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C

ICM7242C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltage s greater than V
destructive device latchup. For this reason, it is recommended that no inp uts from external sources not operating on the same supply be applied
to the device before its supply is e stablished and, that in multiple supply systems, the supply t o t he I C M72 42 be tu rned o n f irst.

2. θ

is measured with the component mounted on an evaluation PC board in free air.

JA

Thermal Resistance (Typical, Note2) θ

(°C/W)

JA

PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C

Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.

or less than VSS may cause

DD

Electrical Specifications V

= 5V, TA = +25°C, R = 10kΩ, C = 0.1µF, VSS = 0V, Unless Otherwise Specified

DD

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Guaranteed Supply Voltage V
Supply Current I

DD

DD

Reset - 125 - µA

2-16V

Operating, R = 10kΩ, C = 0.1µF - 340 800 µA
Operating, R = 1MΩ, C = 0.1µF - 220 600 µA
TB Inhibited, RC Connected to V

SS

- 225 - µA
Timing Accuracy -5-%
RC Oscillator Frequency Temperature

Δf/Δt Independent of RC Components - 250 - ppm/°C

Drift
Time Base Output Voltage V

Time Base Output Leakage Current I
Trigger Input Voltage V

Reset Input Voltage V

Trigger/Reset Input Current I

TRIG

Max Count Toggle Rate f

OTB

TBLK

TRIG

RST

, I

T

I

SOURCE

I

SINK

RC = Ground - - 25 µA
VDD = 5V - 1.6 2.0 V
V
VDD = 5V - 1.3 2.0 V
V

RST

VDD = 2V
V
V

= 100µA - 3.5 - V

= 1.0mA - 0.40 - V

= 15V - 3.5 4.5 V

DD

= 15V - 2.7 4.0 V

DD

-10-µA

-1-MHz

= 5V 2 6 - MHz

DD

= 15V - 13 - MHz

DD

Counter/Divider Mode

50% Duty Cycle Input with Peak to Peak

Output Saturation Voltage V

Output Sourcing Current I

SOURCEVDD

MIN Timing Capacitor (Note 3) C
Timing Resistor Range (Note 3) R

SAT

T
T

Voltages Equal to V
All Outputs Except TB Output VDD = 5V,

I

= 3.2mA

OUT

= 5V Terminals 2 and 3, V

VDD = 2 - 16V 1k - 22M Ω

DD

and V

SS

- 0.22 0.4 V

= 1V - 300 - µA

OUT

10 - - pF

NOTE:

3. For design only, not tested.

3

FN2866.4

February 9, 2007

Test Circuit

V

DD

÷21 (RC/2) OUTPUT

÷28 (RC/256) OUTPUT

ICM7242ICM7242

1
2
3
4

TIME BASE INPUT/OUTPUT

8
7
6
5

C

V

R

DD

NOTE:

1

4.

÷2

and ÷28 outputs are inverters and have active pullups.

Application Information

Operating Considerations

Shorting the RC terminal or output terminals to VDD may
exceed dissipation ratings and/or maximum DC current limits
(especially at high supply voltages).

There is a limitation of 50pF maximum loading on the TB I/O
terminal if the timebase is being used to drive the counter
section. If higher value loading is used, the counter sections
may miscount.

For greatest accuracy, use timing component values shown
in Figure 8. For highest frequency operation it will be
desirable to use very low values for the capacitor; accuracy
will decrease for oscillator frequencies in excess of 200kHz.

The timing capacitor should be connected between the RC
pin and the positive supply rail, V
When system power is turned off, any charge remaining on
the capacitor will be discharged to ground through a large
internal diode between the RC node and V
reference the timing capacitor to ground, since there is no
high current path in this direction to safely discharge the
capacitor when power is turned off. The discharge current
from such a configuration could potentially damage the
device.

When driving the counter section from an external clock, the
optimum drive waveform is a square wave with an amplitude
equal to the supply voltage. If the clock is a very slow ramp
triangular, sine wave, etc., it will be necessary to “square up”
the waveform; this can be done by using two CMOS
inverters in series, operating from the same supply voltage
as the ICM7242.

The ICM7242 is a non-programmable timer whose principal
applications will be very low frequency oscillators and long
range timers; it makes a much better low frequency
oscillator/timer than a 555 or ICM7555, because of the on­chip 8-bit counter. Also, devices can be cascaded to produce
extremely low frequency signals.

Because outputs will not be ANDed, output inverters are
used instead of open drain N-Channel transistors, and the

, as shown in Figure 1.

DD

. Do NOT

SS

TRIGGERRESET

TIME BASE PERIOD = 1.0RC;
1s = 1MΩ x 1µF

external resistors used for the 2242 will not be required for
the ICM7242. The ICM7242 will, however, plug into a socket
for the 2242 having these resistors.

The timing diagram for the ICM7242 is shown in Figure 1.
Assuming that the device is in the RESET mode, which
occurs on power up or after a positive signal on the RESET
terminal (if TRIGGER is low), a positive edge on the trigger
input signal will initiate normal operation. The discharge
transistor turns on, discharging the timing capacitor C, and
all the flip-flops in the counter chain change states. Thus, the
outputs on terminals 2 and 3 change from high to low states.
After 128 negative timebase edges, the ÷2

8

output returns to

the high state.

TRIGGER INPUT
(TERMINAL 6)

TIMEBASE INPUT
(TERMINAL 8)

÷2 OUTPUT
(TERMINAL 2)

÷128/256 OUTPUT
(TERMINAL 3) (ASTABLE

128RC 128RC

128RC

FIGURE 1. TIMING DIAGRAMS OF OUTPUT WAVEFORMS

FOR THE ICM7242 (COMPARE WITH FIGURE 5)

V

DD

1

f

IN/2

OUTPUTS

FIGURE 2. USING THE ICM7242 AS A RIPPLE COUNTER

f

IN/256

(DIVIDER)

2
3
4

OR “FREE RUN” MODE)
÷128/256 OUTPUT

(TERMINAL 3)
(MONOSTABLE
OR “ONE SHOT” MODE)

f

IN

8
7
6

V

DD

5

>3/4 (V+)
<1/4 (V+)

4

FN2866.4

February 9, 2007

ICM7242ICM7242

To use the 8-bit counter without the timebase, Terminal 7
(RC) should be connected to ground and the outputs taken
from Terminals 2 and 3.

The ICM7242 may be used for a very low frequency square
wave reference. For this application the timing components
are more convenient than those that would be required by a
555 timer. For very low frequencies, devices may be
cascaded (see Figure 3).

V

DD

1
2
3
4

R

8
7
6
5

1

C

2

ICM7242ICM7242

3
4

16

f

RC/2

=

8
7
6
5

FIGURE 3. LOW FREQUENCY REFERENCE (OSCILLATOR)

For monostable operation the ÷2

8

output is connected to the
RESET terminal. A positive edge on TRIGGER initiates the
cycle (NOTE: TRIGGER overrides RESET).

V

DD

OUTPUT

1
2
3
4

ICM7242

8
7
6
5

100kΩ

S

1

RESET

R

C

TRIGGER

TABLE 1. COMPARING THE ICM7242 WITH THE 2242

CHARACTERISTICS ICM7242 2242

Operating Voltage 2V to 16V 4V to 15V
Operating Temperature Range -25°C to 85°C0°C to 70°C
Supply Current, V

= 5V 0.7mA (Max) 7mA (Max)

DD

Pullup Resistors

TB Output No Yes

÷2 Output No Yes
÷256 Output No Yes

Toggle Rate 3.0MHz 0.5MHz
Resistor to Inhibit Oscillator No Yes
Resistor in Series with Reset for

No Yes

Monostable Operation
Capacitor TB Terminal for HF

No Sometimes

Operation

By selection of R and C, a wide variety of sequence timing
can be realized. A typical flow chart for a machine tool
controller could be as shown in Figure 5.

TRIGGERING CAN BE
OBTAINED FROM A
PREVIOUS STAGE,
A LIMIT SWITCH,

-

OPERATOR SWITCH, ETC.

STOP

START STOP

START

ENABLE

5s

ICM7242 ICM7240 ICM7242

ICM7242 ICM7242

WAIT

5s

COUNT

TO 185

ENABLE

10s

WAIT

5s

TRIGGER

TB OUTPUT

OUTPUT TERMINAL 3

TERMINAL 6

TERMINAL 8

FIGURE 4. MONOSTABLE OPERATION

The ICM7242 is superior in all respects to the 2242 except
for initial accuracy and oscillator stability. This is primarily
due to the fact that high value p-resistors have been used on
the ICM7242 to provide the comparator timing points.

5

WAIT

5s

ENABLE

10s

WAIT

5s

COUNT

TO 185

ENABLE

5s

FIGURE 5. FLOW CHART FOR MACHINE TOOL CONTROLLER

By cascading devices, use of low cost CMOS AND/OR gates
and appropriate RC delays between stages, numerous
sequential control variations can be obtained. Typical
applications include injection molding machine controllers,
phonograph record production machines, automatic
sequencers (no metal contacts or moving parts), milling
machine controllers, process timers, automatic lubrication
systems, etc.

Sequence Timing

• Process Control

• Machine Automation

• Electro-Pneumatic Drivers

• Multi Operation (Serial or Parallel Controlling)

FN2866.4

February 9, 2007

ICM7242ICM7242

TRIGGER

V

DD

S

1

TO START SEQUENCE:

PUSH S

1

TRIGGER

OUTPUT A (NOTE)

OUTPUT B (NOTE)

50k

V

DD

R (NOTE)

A

C

1µF

63

ICM7242
A

33k

10k

5

100pF

MUST BE SHORTER THAN “ON TIME

128RC

V

DD

R (NOTE)

C

63

ICM7242

B

33k

5

100pF

128RC

V

DD

B

1µF

R (NOTE)

C

CD

1µF

63

10k

ICM7242

C

33k

5

100pF

”

A

10k

V

DD

R (NOTE)

C

63

ICM7242
D

33k

5

100pF

OUTPUT C (NOTE)

OUTPUT D (NOTE)

ON TIME

A

NOTE: Select RC values for desired “ON TIME” for each ICM7242.

FIGURE 6. SEQUENCE TIMER

ON TIME

128RC

128RC

ON TIME

B

C

ON TIME

D

6

FN2866.4

February 9, 2007

Typical Performance Curves

ICM7242ICM7242

260
240
220
200
180
160
140
120
100

80
60

SUPPLY CURRENT (µA)

40
20

0

0 2 4 6 8 10 12 14 16

SUPPLY VOLTAGE (V)

TA = -20°C

TA = +25°C

TA = +75°C

RESET MODE

100M

10M

1M

100k

10k

TIMING RESISTOR, R (Ω)

1k

100

100pF 0.01 1 10 100 1000 10,000

RECOMMENDED RANGE OF

TIMING COMPONENT VALUES

0.10.001

TIMING CAPACITOR, C (µF)

FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 8. RECOMMENDED RANGE OF TIMING

COMPONENT VALUES FOR ACCURATE TIMING

10,000

1,000

100

10

1

0.1

CAPACITANCE (µF)

0.01

0.001
100p

10p

1MΩ

1p

0.1 1 10 100 1k 10k 100k 1M 10M
TIME BASE FREQUENCY (Hz)

10kΩ

100kΩ

10MΩ

VDD = 5.0V
T

= +25°C

A

1kΩ

1500
1400
1300
1200
1100
1000

900
800
700
600
500
400
300

TRIGGER PULSE WIDTH (ns)

200

VDD = 2V

100

0

012345678910

VDD = 5V

VDD = 16V

TRIGGER AMPLITUDE (V)

TA = +25°C

TA = +25°C

FIGURE 9. TIMEBASE FREE RUNNING FREQUENCY vs R AND C FIGURE 10. MINIMUM TRIGGER PULSE WIDTH vs TRIGGER

AMPLITUDE

1500
1400
1300
1200
1100
1000

900
800
700
600
500
400

RESET PULSE WIDTH (ns)

300
200
100

0

012345678910

VDD = 5V

VDD = 2V

VDD = 16V

RESET AMPLITUDE (V)

TA = 25°C

FIGURE 11. MINIMUM RESET PULSE WIDTH vs RESET

AMPLITUDE

7

+10.0

TA = +25°C

R

10kΩ

0.001µF

1MΩ

100pF

1kΩ

0.1µF

100kΩ

0.001µF

10kΩ

0.01µF

100kΩ

0.01µF

2 101214161820

864

SUPPLY VOLTAGE (V)

NORMALIZED FREQUENCY DEVIATION (%)

+8.0
+6.0
+4.0
+2.0

0.0

-2.0

-4.0

-6.0

-8.0

-10.0

FIGURE 12. NORMALIZED FREQUENCY STABILITY IN THE

ASTABLE MODE vs SUPPLY VOL TAGE

FN2866.4

February 9, 2007

C

Typical Performance Curves (Continued)

ICM7242ICM7242

+5

5V ≤ VDD ≤ 15V

+4
+3
+2
+1

0

-1

-2

-3

-4

NORMALIZED FREQUENCY DEVIATION (%)

-5

-25 0 25 50 75
TEMPERATURE (°C)

R = 10MΩ

C = 0.1µF

R = 1kΩ
C = 0.1µF

FIGURE 13. NORMALIZED FREQUENCY STABILITY IN THE

ASTABLE MODE vs TEM PERATURE

100

TA = +25°C

VDD = 15V

VDD = 5V

10

100M

MAXIMUM DIVIDER FREQUENCY (Hz)

10M

1M

100k

10k

0

2 101214161820

864

SUPPLY VOLTAGE (V)

TA = +25°C
RC CONNECTED

TO GROUND

FIGURE 14. MAXIMUM DIVIDER FREQUENCY vs SUPPLY

VOLTAGE

100

TA = +25°C

10

VDD = 15V

VDD = 5V

VDD = 2V

1

DISCHARGE SINK CURRENT (mA)

0.1

0.01 0.1 1 10
DISCHARGE SATURATION VOLTAGE (V)

FIGURE 15. DISCHARGE OUTPUT CURRENT vs DISCHARGE

OUTPUT VOLTAGE

VDD = 2V

1

OUTPUT SATURATION CURRENT (mA)

0.1

0.01 0.1 1 10
OUTPUT SATURATION VOL TAGE (V)

FIGURE 16. OUTPUT SATURATION CURRENT vs OUTPUT

SATURATION VOLTAGE

8

FN2866.4

February 9, 2007

Dual-In-Line Plastic Packages (PDIP)

S

ICM7242

E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4

A1 0.015 - 0.39 - 4

A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.355 0.400 9.01 10.16 5

D1 0.005 - 0.13 - 5

NOTESMIN MAX MIN MAX

INDEX

AREA

BASE

PLANE

EATING

PLANE

N

12 3 N/2

-A-

D1

B1

B

E1

-B-

D

A2

-C-

A

D1

e

0.010 (0.25) C AM BS

1

E

A

L

e

C

C

L

e

A

C

e

B

E 0.300 0.325 7.62 8.25 6

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru-

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N8 89

Rev. 0 12/93

sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).

6. E and are measured with the leads constrained to be per-

7. e

e

pendicular to datum .

A

and eC are measured at the lead tips with the leads uncon-

B

strained. e

must be zero or greater.

C

-C-

8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

9

FN2866.4

February 9, 2007

Small Outline Plastic Packages (SOIC)

ICM7242ICM7242

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

10

FN2866.4

February 9, 2007