Intersil Corporation ICM7224IPL Datasheet

ICM7224

May 2001

Features

• High Frequency Counting - Guaranteed 15MHz, Typically 25MHz at 5V

• Low Power Operation - Typically Less Than 100µW Quiescent

•STORE

and RESET Inputs Permit Operation as

Frequency or Period Counter

• True COUNT INHIBIT

• CARRY

Output for Cascading Four-Digit Blocks

Disables First Counter Stage

• Schmitt-Trigger on the COUNT Input Allows Operation in Noisy Environments or with Slowly Changing Inputs

• Leading Zero Blanking INput and OUTput for Correct Leading Zero Blanking with Cascaded Devices

• Provides Complete Onboard Oscillator and Divider Chain to Generate Backplane Frequency, or Backplane Driver May be Disabled Allowing Segments to be Slaved to a Master Backplane Signal

Pinout

ICM7224

(PDIP)

TOP VIEW

41/2 Digit LCD Display Counter

Description

The ICM7224 device is a high-performance, CMOS 41/ digit counter, including decoder, output latch, display driver, count inhibit, leading zero blanking, and reset circuitry.

The counter section provides direct static counting, guaranteed from DC to 15MHz, using a 5V ±10% supply over the operating temperature range. At normal ambient temperatures, the devices will typically count up to 25MHz. The COUNT input is provided with a Schmitt trigger to allow operation in noisy environments and correct counting with slowly changing inputs. The COUNT INHIBIT, STORE and RESET inputs allow a direct interface with the ICM7207 and ICM7207A to implement a low cost, low power frequency counter with a minimum component count.

These devices also incorporate several features intended to simplify cascading four-digit blocks. The CARRY allows the counter to be cascaded, while the Leading Zero Blanking INput and OUTput allows correct Leading Zero Blanking between four-decade blocks. The BackPlane driver of the LCD devices may be disabled, allowing the segments to be slaved to another backplane signal, necessary when using an eight or twelve digit, single backplane display.

These devices provide maximum count of 19999. The display drivers are not of the multiplexed type and each display segment has its own individual drive pin, providing high quality display outputs.

output

OSCILLATOR

STORE

RESET

COUNT

COUNT INHIBIT

LZB OUT

LZB IN

CARRY

/2 - DIGIT

Part Number Information

TEMP.

PART NUMBER

ICM7224IPL -25 to 85 40 Ld PDIP E40.6

RANGE (oC) PACKAGE

PKG.

NO.

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

File Number 3168.2

Functional Block Diagram

ICM7224

STORE

LEADING

ZERO

BLANKING

OUTPUT

COUNT

INHIBIT

COUNT

INPUT

RESET

OSCILLATOR

INPUT

SCHMITT

TRIGGER

LSD

DIGIT 1

SEGMENT OUTPUTS

7 WIDE DRIVER

7 WIDE LATCH

DECODER

OSCILLATOR +124

ENABLE

DETECTOR

DIGIT 2

SEGMENT OUTP UTS

7 WIDE DRIVER

7 WIDE LATCH

DECODER DECODER DECODER

BLACKPLANE

DRIVER

ENABLE

DIGIT 3

SEGMENT OUTPUTS

7 WIDE DRIVER

7 WIDE LATCH

SEGMENT OUTPUTS

7 WIDE DRIVER

DIGIT 4

7 WIDE LATCH

MSD

/2 DIGIT

OUTPUT

/2 DIGIT

DRIVER

/2 DIGIT LATCH

LEADING ZERO BLANKING INPUT

DIGIT

CARRY OUTPUT

BP INPUT/OUTPUT

ICM7224

Absolute Maximum Ratings Thermal Information

Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V

Input Voltage (Any Terminal) (Note 1) . . .(V

+ 0.3V) to (V

- 0.3V)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical, Note 2)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . . -65

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300

NOTES:

1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than V cause destructive device latchup. For this reason, it is recommended that no inputs from sources operating on a different power supply

or less than VSS may

be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7224 be turned on first.

2. θ

is measured with the component mounted on an evaluation PC board in free air.

(oC/W)

C to 150oC

Electrical Specifications V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Operating Current, I

Operating Supply Voltage Range (V

- V

), V

OSClLLATOR Input Current, I

Segment Rise/Fall Time, t

BackPlane Rise/Fall Time, t

Oscillator Frequency, f

Backplane Frequency, f

Input Pullup Currents, I

Input High Voltage, V

Input Low Voltage, V

COUNT

Input Threshold, V

COUNT

Input Hysteresis, V

Output High Current, I

Output Low Current, I

Count Frequency, f

STORE

, RESET Minimum Pulse Width, tS, t

SUPPLY

COUNT

OSC

OSCI

, t

= 5V, V

= 0V, TA = 25oC, Unless Otherwise Indicated

Test Circuit, Display Blank - 10 50 µA

3-6V

Pin 36 - ±2 ±10 µA

= 200pF - 0.5 - µs

LOAD

= 5000pF - 1.5 - µs

LOAD

Pin 36 Floating - 19 - kHz

Pin 36 Floating - 150 - Hz

Pins 29, 31, 33, 34, VIN = VDD - 3V - 10 - µA

Pins 29, 31, 33, 34 3 - - V

Pins 29, 31, 33, 34 - - 1 V

-2-V

-0.5- V

CARRY Pin 28

-350 -500 - µA Leading Zero Blanking OUT Pin 30 V

= VDD - 3V

OUT

CARRY Pin 28

350 500 - µA Leading Zero Blanking OUT Pin 30 V

= +3V

OUT

4.5V < VDD < 6V 0 - 15 MHz

3--µs

Timing Waveforms

OSCILLATOR

FREQUENCY

BACKPLANE

INPUT/OUTPUT

OFF SEGMENTS

ON SEGMENTS

FIGURE 1. ICM7224 DISPLAY WAVEFORMS

128 CYCLES

64 CYCLES

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