intersil ICL7660S DATA SHEET

®

www.BDTIC.com/Intersil

ICL7660S

Data Sheet March 6, 2008

Super Voltage Converter

The ICL7660S Super Volt ag e Converter is a monolithic
CMOS voltage conversion IC that guarantees significant
performance advantages over other similar devices. It is a
direct replacement for the industry standard ICL7660 of fering
an extended operating supply voltage range up to 12V, with
lower supply current. No external diode is needed for the
ICL7660S. In addition, a Frequency Boost pin has been
incorporated to enable the user to achieve lower output
impedance despite using smaller capacitors. All
improvements are highlighted in the “Electrical S pecifications”
section on page 3. Critical parameters are guaranteed over

the entire commercial, industrial and military temperature
ranges.

The ICL7660S performs supply voltage conversion from
positive to negative for an input range of 1.5V to 12V,
resulting in complementary output voltages of -1.5V to -12V.
Only 2 non-critical external capacitors are needed for the
charge pump and charge reservoir functions. The ICL7660S
can be connected to function as a voltage doubler and will
generate up to 22.8V with a 12V input. It can also be used as
a voltage multiplier or voltage divider.

The chip contains a series DC power supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. The oscillator, when unloaded, oscillates at a
nominal frequency of 10kHz for an input supply voltage of

5.0V. This frequency can be lowered by the addition of an
external capacitor to the “OSC” terminal, or the oscillator
may be over-driven by an external clock.

FN3179.5

Features

• Guaranteed Lower Max Supply Current for All
Temperature Ranges

• Wide Operating Voltage Range 1.5V to 12V

• 100% Tested at 3V

• No External Diode Over Full Temperature and Voltage
Range

• Boost Pin (Pin 1) for Higher Switching Frequency

• Guaranteed Minimum Power Efficiency of 96%

• Improved Minimum Open Circuit Voltage Conversion
Efficiency of 99%

• Improved SCR Latchup Protection

• Simple Conversion of +5V Logic Supply to ±5V Supplies

• Simple Voltage Multiplication V

OUT

= (-)nV

IN

• Easy to Use - Requires Only 2 External Non-Critical
Passive Components

• Improved Direct Replacement for Industry Standard
ICL7660 and Other Second Source Devices

• Pb-Free Available (RoHS Compliant)

Applications

• Simple Conversion of +5V to ±5V Supplies

• Voltage Multiplication V

• Negative Supplies for Data Acquisition Systems and
Instrumentation

• RS232 Power Supplies

• Supply Splitter, V

OUT

= ±nV

OUT

= ±VS/2

IN

The “LV” terminal may be tied to GND to bypass the internal
series regulator and improve low voltage (LV) operation. At
medium to high voltages (3.5V to 12V), the LV pin is left
floating to prevent device latchup.

Pinout

ICL7660S

(8 LD PDIP, SOIC)

TOP VIEW

BOOST

CAP+

GND

CAP-

1
2
3
4

1

8

V+

7

OSC

6

LV

5

V

OUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2004, 2005, 2008. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

ICL7660S

www.BDTIC.com/Intersil

Ordering Information

TEMP. RANGE

PART NUMBER PART MARKING

ICL7660SCBA 7660 SCBA 0
ICL7660SCBA-T

(Note 3)
ICL7660SCBAZ

(Note 1)
ICL7660SCBAZ-T

(Notes 1, 3)
ICL7660SCPA 7660S CPA 0
ICL7660SCPAZ

(Note 1)
ICL7660SIBA 7660 SIBA -40
ICL7660SIBAT

(Note 3)
ICL7660SIBAZ

(Note 1)
ICL7660SIBAZT

(Notes 1, 3)
ICL7660SIPA 7660 SIPA -40
ICL7660SIPAZ

(Note 1)
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

2. Add /883B to part number if 883B processing is required.

3. Please refer to TB347 for details on reel specifications.

7660 SCBA 0

7660 SCBAZ 0

7660 SCBAZ 0

7660S CPAZ 0

7660 SIBA -40

7660 SIBAZ -40

7660 SIBAZ -40

7660S IPAZ -40

(°C) PACKAGE PKG. DWG. #

to +70 8 Ld SOIC M8.15
to +70 8 Ld SOIC T ape and Reel M8.15

to +70 8 Ld SOIC

(Pb-free)

to +70 8 Ld SOIC T ape and Reel

to +70 8 Ld PDIP E8.3
to +70 8 Ld PDIP*

to +85 8 Ld SOIC M8.15
to +85 8 Ld SOIC T ape and Reel M8.15

to +85 8 Ld SOIC

to +85 8 Ld SOIC T ape and Reel

to +85 8 Ld PDIP E8.3
to +85 8 Ld PDIP*

(Pb-free)

(Pb-free)

(Pb-free)

(Pb-free)

(Pb-free)

M8.15

M8.15

E8.3

M8.15

M8.15

E8.3

2

FN3179.5

March 6, 2008

ICL7660S

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V

LV and OSC Input Voltage (Note 4)

V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V

V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ -5.5V to V+ +0.3V

Current into LV (Note 4)

V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20μA

Output Short Duration

V

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

≤ 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous

SUPPLY

Thermal Resistance (Typical, Note 5) θ

8 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

8 Ld Plastic SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing. applications.

Operating Conditions

Temperature Range

ICL7660SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

ICL7660SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

4. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to “power up” of ICL7660S.

is measured with the component mounted on an evaluation PC board in free air.

5. θ

JA

(°C/W)

JA

Electrical Specifications V+ = 5V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Supply Current (Note 8) I+ R

Supply Voltage Range - High
(Note 9)

Supply Voltage Range - Low V+
Output Source Resistance R

Oscillator Frequency (Note 7) f

Power Efficiency P

Voltage Conversion Efficiency V

OUT

= +25°C, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified.

A

V+

H

L

OUTIOUT

OSC

EFF

EFF RL = ∞ 99 99.9 - %

= ∞, +25°C - 80 160 µA

L

0°C < T

-40°C < T

-55°C < T
RL = 10k, LV Open, T

RL = 10k, LV to GND, T

I
I
I
I

0°C < T
I

-40°C < T
I

-55°C < T
C
C
RL = 5kΩ 96 98 - %
T

< +70°C - - 180 µA

A

< +85°C - - 180 µA

A

< +125°C - - 200 µA

A

< TA < T

MIN

MIN

= 20mA - 60 100 Ω
= 20mA, 0°C < TA < +70°C - - 120 Ω

OUT

= 20mA, -25°C < TA < +85°C - - 120 Ω

OUT

= 20mA, -55°C < TA < +125°C - - 150 Ω

OUT

= 3mA, V+ = 2V, LV = GND,

OUT

< +70°C

A

= 3mA, V+ = 2V, LV = GND,

OUT

OUT

OSC
OSC

MIN

< +85°C

A

= 3mA, V+ = 2V, LV = GND,

< +125°C

A

= 0, Pin 1 Open or GND 5 10 - kHz
= 0, Pin 1 = V+ - 35 - kHz

< TA < T

= 5kΩ 95 97 - -

MAX RL

< TA < T

MAX

MAX

3.0 - 12 V

1.5 - 3.5 V

- - 250 Ω

- - 300 Ω

- - 400 Ω

3

FN3179.5

March 6, 2008

ICL7660S

www.BDTIC.com/Intersil

Electrical Specifications V+ = 5V, T

= +25°C, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified. (Continued)

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Oscillator Impedance Z

OSC

V+ = 2V - 1 - MΩ
V+ = 5V - 100 - kΩ

NOTES:

6. Derate linearly above +50°C by 5.5mW/°C

7. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, of the order of 5pF.

8. The Intersil ICL7660S can operate without an external diode over the full temperature and voltage range. This device will function in existing
designs which incorporate an external diode with no degradation in overall circuit performance.

9. All significant improvements over the industry standard ICL7660 are highlighted.

Typical Performance Curves (Test Circuit Figure 12)

12

10

8

6

4

SUPPLY VOLTAGE (V)

2

0

-55 -25 0 25 50 100 125

SUPPLY VOLTAGE RANGE

(NO DIODE REQUIRED)

TEMPERATURE (°C)

FIGURE 1. OPERATING VOLT AGE AS A

FUNCTION OF TEMPERATURE

250

TA = +125°C

200

TA = +25°C

150

TA = -55°C

100

50

OUTPUT SOURCE RESISTANCE (W)

0

02 4681012

SUPPLY VOLTAGE (V)

FIGURE 2. OUTPUT SOURCE RESISTANCE AS A

FUNCTION OF SUPPLY VOLTAGE

350

300

250

I

200

150

100

50

OUTPUT SOURCE RESISTANCE (Ω)

0

-50 -25 0 25 50 75 100 125

= 20mA,

OUT

V+ = 5V

TEMPERATURE (°C)

I

OUT

V+ = 2V

I

= 20mA,

OUT

V+ = 5V

I

= 20mA,

OUT

V+ = 12V

= 3mA,

FIGURE 3. OUTPUT SOURCE RESISTANCE AS A

FUNCTION OF TEMPERATURE

4

98
96

V+ = 5V
T

= +25°C

A

94

I

= 1mA

OUT

92
90
88
86
84
82

POWER CONVERSION EFFICIENCY (%)

80

100 1k 10k 50k

OSC FREQUENCY f

OSC

(Hz)

FIGURE 4. POWER CONVERSION EFFICIENCY AS A

FUNCTION OF OSCILLATOR FREQUENCY

March 6, 2008

FN3179.5

ICL7660S

www.BDTIC.com/Intersil

Typical Performance Curves (Test Circuit Figure 12) (Continued)

10

9

(kHz)

8

OSC

7
6
5
4
3
2
1

OSCILLATOR FREQUENCY f

0

1 10 100 1k

C

OSC

(pF)

V+ = 5V

= +25°C

T

A

FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION

OF EXTERNAL OSCILLATOR CAPACITANCE

1

V+ = 5V
T

= +25°C

0

A

-1

-2

-3

OUTPUT VOLTAGE (V)

-4

-5
010203040

LOAD CURRENT (mA)

FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION

OF OUTPUT CURRENT

20

18

(kHz)

OSC

16

14

12

10

8

OSCILLATO R FREQUENCY f

-55 -25 0 25 50 75 100 125

V+ = 5V

V+ = 10V

TEMPERATURE (°C)

FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A

FUNCTION OF TEMPERATURE

100

90
80
70
60
50
40
30
20
10

POWER CONVERSION EFFICIENCY (%)

0

010203040 5060

LOAD CURRENT (mA)

V+ = 5V

= +25°C

T

A

100
90
80
70
60
50
40
30
20
10
0

FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION

EFFICIENCY AS A FUNCTION OF LOAD
CURRENT

SUPPL Y CURRENT (mA)

2

V+ = 2V
TA = +25°C

1

0

-1

OUTPUT VOLTAGE (V)

-2
012 3456789

LOAD CURRENT (mA)

FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT

100

90
80
70
60
50
40

EFFICIENCY (%)

30

POWER CONVERSION

20
10

0

0 1.5 3.0 4.5 6.0 7.5 9.0

FIGURE 10. SUPPLY CU RRENT AND POWER CONVERSION

CURRENT

5

16
14
12
10
8

V+ = 2V
T

= +25°C

A

LOAD CURRENT (mA)

6
4
2
0

EFFICIENCY AS A FUNCTION OF LOAD CURRENT

FN3179.5

March 6, 2008

SUPPLY CURRENT (mA) (NOTE 9)

ICL7660S

www.BDTIC.com/Intersil

Typical Performance Curves (Test Circuit Figure 12) (Continued)

V+ = 5V
T

= +25°C

A

400

300

200

100

OUTPUT RESISTANCE (Ω)

NOTE:

10. These curves include in the supply current that current fed directly into the load R
supply current goes directly to the positive side of the load, and the other half, through the ICL7660S, to the negative side of the load. Ideally,

∼ 2VIN, IS ∼ 2IL, so VIN x IS ∼ V

V

OUT

FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY

x IL.

OUT

I = 10mA

C1 = C2 = 10mF

C1 = C2 = 100mF

0

100 1k 10k 100k

OSCILLATOR FREQUENCY (Hz)

Detailed Description

The ICL7660S contains all the necessary circuitry to
complete a negative voltage converter, with the exception of
2 external capacitors which may be inexpensive 10µF
polarized electrolytic types. The mode of operation of the
device may be best understood by considering Figure 12,
which shows an idealized negat i ve vo ltage converter.
Capacitor C
when switches S
and S
half cycle of operation, switches S
S

and S3 open, thereby shifting capacitor C1 to C2 such

1

that the voltage on C
and no load on C
situation more closely than existing non-mechanical circuits.

+

C

1

10µF

-

is charged to a voltage, V+, for the half cycle

1

and S3 are closed. (Note: Switches S2

are open during this half cycle). During the second

4

V+

1

and S4 are closed, with

2

is exactly V+, assuming ideal switches

2

. The ICL7660S approaches this ideal

2

1

2

3

4

ICL7660S

8

7

6

5

-

C

2

+

10µF

ISV+

I

L

R

L

(+5V)

-V

OUT

C1 = C2 = 1mF

from the V+ (See Figure 12). Thus, approximately half the

L

approach is that in integrating the switches, the substrates of
S

and S4 must always remain reverse biased with respect

3

to their sources, but not so much as to degrade their “ON”
resistances. In addition, at circuit start-up, and under output
short circuit conditions (V

= V+), the output voltage must

OUT

be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latch-up.

This problem is eliminated in the ICL7660S by a logic network
which senses the output voltage (V
level translators, and switches the substrates of S

) together with the

OUT

and S4 to

3

the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7660S is an integral

part of the anti-latchup circuitry, however its inherent voltage
drop can degrade operation at low voltages. Therefore, to
improve low voltage operation “LV” pin should be connected
to GND, disabling the regulator. For supply voltages greater
than 3.5V the LV terminal must be left open to insure latchup
proof operation, and prevent device damage.

Theoretical Power Efficiency
Considerations

In theory, a volt age converter can approach 100% efficiency
if certain conditions are met:

1. The drive circuitry consumes minimal power.

NOTE: For large values of C
should be increased to 100µF.

FIGURE 12. ICL7660S TEST CIRCUIT

In the ICL7660S, the 4 switches of Figure 13 are MOS
power switches; S
S

are N-Channel devices. The main difficulty with this

4

is a P-Channel devices and S2, S3 and

1

(>1000pF) the values of C1 and C2

OSC

2. The output switches have extremely low ON resistance
and virtually no offset.

3. The impedance of the pump and reservoir capacitors are
negligible at the pump frequency.

6

FN3179.5

March 6, 2008

ICL7660S

www.BDTIC.com/Intersil

The ICL7660S approaches these conditions for negative
voltage conversion if large values of C

and C2 are used.

1

ENERGY IS LOST ONL Y IN THE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:

1

-- -

E

2

where V
and transfer cycles. If the impedances of C

2

2

V

–()=

C

1V1

1

2

and V2 are the voltages on C1 during the pump

and C2 are

1

(EQ. 1)

Typical Applications

Simple Negative Voltage Converter

The majority of applications will undoubtedly utilize the
ICL7660S for generation of negative supply voltages.
Figure 14 shows typical connections to provide a negative
supply where a positive supply of +1.5V to +12V is available.
Keep in mind that pin 6 (LV) is tied to the supply negative
(GND) for supply voltage below 3.5V.

relatively high at the pump frequency (refer to Figure 13)
compared to the value of R
difference in the voltages V
desirable to make C

2

voltage ripple, but also to employ a correspondingly large
value for C

in order to achieve maximum efficiency of

1

operation.

8

V

IN

33

S

1

S

3

, there will be substantial

L

and V2. Therefore it is not only

1

as large as possible to eliminate output

S

2

4

2

C

1

C

2

S

4

V

OUT

5

= -V

10µF

FIGURE 14. SIMPLE NEGATIVE CONVERTER AND ITS

1
2

+

-

ICL7660S

3
4

OUTPUT EQUIVALENT

The output characteristics of the circuit in Figure 14 can be
approximated by an ideal voltage source in series with a

IN

resistance as shown in Figure 14B. The voltage source has
a value of -(V+). The output impedance (R
the ON resistance of the internal MOS switches (shown in

7

FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER

Figure 13), the switching frequency, the value of C
and the ESR (equivalent series resistance) of C
good first order approximation for R

Do’s and Don’ts

1. Do not exceed maximum supply voltages.

2. Do not connect LV terminal to GND for supply voltage
greater than 3.5V.

3. Do not short circuit the output to V

+

supply for supply

2R

R

0

1

------------------------------- -

f

PUMPC1

f

PUMP

++()2R

SW1RSW3

+

ESR

×

=

f

OSC

------------- -

C2

R

SWX

2

voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay.

4. When using polarized capacitors, the + terminal of C
must be connected to pin 2 of the ICL7660S and the +
terminal of C

must be connected to GND.

2

5. If the voltage supply driving the ICL7660S has a large
source impedance (25Ω to 30Ω), then a 2.2μF capacitor
from pin 8 to ground may be required to limit rate of rise
of input voltage to less than 2V/µs.

6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions. A 1N914 or similar diode placed
in parallel with C2 will prevent the device from latching up
under these conditions. (Anode pin 5, Cathode pin 3).

1

Combining the four R

R

2xR

0

SW

+++≅

------------------------------- -

f

PUMPC1

RSW, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resist ance
graphs), typically 23Ω at +25°C and 5V. Careful selection of
C

and C2 will reduce the remaining terms, minimizing the

1

output impedance. High value capacitors will reduce the
1/(f

x C1) component, and low ESR capacitors will lower

PUMP

the ESR term. Increasing the oscillator frequency will reduce
the 1/(f

x C1) term, but may have the side effect of a net

PUMP

increase in output impedance when C
enough to fully charge the capacitors every cycle. In a typical
application where f

OSC

V+

8
7
6
5

-

V

= -V+

C1

+

OUT

O

is:

O

++()++(≅

SW2RSW4

ESR

C1

C2

> 10µF and is not long

1

10µF

14A. 14B.

ESR

MOSFET Switch Resistance=()

terms as RSW, we see that:

SWX

1

4xESR

×

R

O V

OUT

-

V+

+

) is a function of

and C2,

1

and C2. A

1

ESR

C1

(EQ. 2)

(EQ. 3)

= 10kHz and C = C1 = C2 = 10µF:

7

FN3179.5

March 6, 2008

ICL7660S

www.BDTIC.com/Intersil

R02x23

46 20 5++ ESR

R

0

---------------------------------------------------

+++≅

510

1

3

× 10× 106–×

×≅

C

4xESR

C1

ESR

C2

(EQ. 4)

Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/f

x C1) term, rendering

PUMP

an increase in switching frequency or filter capacitance
ineffective. Typical electrolytic capacitors may have ESRs as
high as 10Ω.

Output Ripple

ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 15. Segment A is the voltage drop across the ESR of
C

at the instant it goes from being charged by C1 (current

2

flowing into C
(current flowing out of C
change is 2 x I
ESR

C2

time t

, the half of the cycle when C2 supplies current the

2

load. The drop at B is I
voltage is the sum of these voltage drops:

V

RIPPLE

Again, a low ESR capacitor will result in a higher
performance output.

) to being discharged through the load

2

OUT

). The magnitude of this current

2

, hence the total drop is 2 x I

OUT

x

V . Segment B is the voltage change across C2 during

x t2/C2V . The peak-to-peak ripple

OUT

1

⎛⎞

-----------------------------------------

≅

⎝⎠

2f

× C2×

PUMP

2ESR

×+

C2IOUT

(EQ. 5)

Changing the ICL7660S Os c ill at or Fre q ue n cy

It may be desirable in some applications, due to noise or other
considerations, to alter the oscillator frequency. This can be
achieved simply by one of several methods described in the
following.

By connecting the Boost Pin (Pin 1) to V+, the oscillator
charge and discharge current is increased and, hence, the
oscillator frequency is increased by approximately 3
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount
applications where capacitor size and cost are critical.
Smaller capacitors, e.g. 0.1µF, can be used in conjunction
with the Boost Pin in order to achieve similar output currents
compared to the device free running with C

= C2 = 10µF or

1

100µF. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).

Increasing the oscillator frequency can also be achieved by
overdriving the oscillator from an external clock, as shown in
Figure 18. In order to prevent device latchup, a 1kΩ resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock
frequency using TTL logic, the addition of a 10kΩ pull-up
resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,

1

will be

/2 of the clock frequency. Output transitions occur on

the positive going edge of the clock.

1

/2

Paralleling Devices

Any number of ICL7660S voltage converters may be
paralleled to reduce output resistance. The reservoir
capacitor , C
its own pump capacitor, C

, serves all devices while each device requires

2

. The resultant output resistance

1

would be approximately:

R

OUT of ICL7660S()

R

---------------------------------------------------------

=

OUT

n number of devices()

(EQ. 6)

Cascading Devices

The ICL7660S may be cascaded as shown to produce larger
negative multiplication of the initial supply voltage. However,
due to the finite efficiency of each device, the practical limi t is
10 devices for light loads. The output voltage is defined by:

V

OUT

where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660S
R

OUT

nVIN()–=

values.

(EQ. 7)

10µF

1

2

+

-

ICL7660S

3

4

FIGURE 15. EXTERNAL CLOCKING

8

7

6

5

V+

1kΩ

-

10µF

+

V

V+

OUT

CMOS
GATE

It is also possible to increase the conversion efficiency of the
ICL7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 19. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C
increasing the values of C

) and reservoir (C2) capacitors; this is overcome by

1

and C2 by the same factor that

1

the frequency has been reduced. For example, the addition
of a 100pF capacitor between pin 7 (OSC and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10), and thereby necessitate
corresponding increase in the value of C

and C2 (from

1

10µF to 100µF).

8

FN3179.5

March 6, 2008

ICL7660S

www.BDTIC.com/Intersil

V+

1
2

+

C

1

-

ICL7660S

3
4

8
7
6
5

C

OSC

V

-

+

OUT

C

2

FIGURE 16. LOWERING OSCILLATOR FREQUENCY

Positive Voltage Doubling

The ICL7660S may be employed to achieve positive voltage
doubling using the circuit shown in Figure 20. In this
application, the pump inverter switches of the ICL7660S are
used to charge C
the supply voltage and V
the supply voltage (V+) is applied through diode D
capacitor C
(2V+) - (2V
combined forward voltage drops of diodes D

The source impedance of the output (V
the output current, but for V+ = 5V and an output current of
10mA it will be approximately 60Ω.

to a voltage level of V+ -VF (where V+ is

1

is the forward voltage on C1 plus

F

2

. The voltage thus created on C2 becomes

2

) or twice the supply voltage minus the

F

V+

and D2.

1

) will depend on

OUT

to

V+

= -V

1
2

+

C

1

-

ICL7660S

3
4

­C

8
7
6
5

+

2

D

1

D

2

V

OUT

IN

­C

3

+

V

= (2V+) -

OUT

(V

) - (V

FD1

+

C

4

-

FD2

FIGURE 18. COMBINED NEGATIVE VOLTAGE CONVERTER

AND POSITIVE DOUBLER

Voltage Splitting

The bidirectional characteristics can also be used to split a
high supply in half, as shown in Figure 22. The combined
load will be evenly shared between the two sides, and a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel, the output impedance is
much lower than in the standard circuits, and higher currents
can be drawn from the device. By using this circuit, and then
the circuit of Figure 17, +15V can be converted (via +7.5,
and -7.5 to a nominal -15V, although with rather high se ries
output resistance (

∼250Ω).

)

1

2

3

4

ICL7660S

8

D

7

6

5

1

D

2

+

C

1

-

V

=

OUT

- (2V

(2V+)

+

C

2

-

)

F

NOTE: D1 and D2 can be any suitable diode.

FIGURE 17. POSITIVE VOLTAGE DOUBLER

Combined Negative Voltage Conversion and
Positive Supply Doubling

Figure 21 combines the functions shown in Figure 14 and
Figure 20 to provide negative voltage conversion and
positive voltage doubling simultaneously. This approach
would be, for example, suitable for generating +9V and -5V
from an existing +5V supply. In this instance capacitors C
and C

perform the pump and reservoir functions

3

respectively for the generation of the negative voltage, while
capacitors C

and C4 are pump and reservoir respectively

2

for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher due to the finite impedance of the common
charge pump driver at pin 2 of the device.

1

V+

V-

V

R

OUT

R

+

=

V+ - V-

2

50µF

50µF

50µF

­1

2

+

-

+

-

ICL7660S

3
4

8
7
6
5

L1

L2

FIGURE 19. SPLITTING A SUPPLY IN HALF

Regulated Negative Voltage Supply

In some cases, the output impedance of the ICL7660S can
be a problem, particularly if the load current varies
substantially. The circuit of Figure 23 can be used to
overcome this by controlling the input voltage, via an
ICL7611 low-power CMOS op amp, in such a way as to
maintain a nearly constant output voltage. Direct feedback is
inadvisable, since the ICL7660S’s output does not respond
instantaneously to change in input, but only after the
switching delay. The circuit shown supplies enough delay to
accommodate the ICL7660S, while maintaining adequate
feedback. An increase in pump and storage capacitors is
desirable, and the values shown provides an output
impedance of less than 5Ω to a load of 10mA.

9

FN3179.5

March 6, 2008

ICL7660S

www.BDTIC.com/Intersil

TTL DATA

INPUT

+

10µF

-

+8V

56k

50k

50k

+8V

100Ω

-

100k

ICL8069

FIGURE 20. REGULATING THE OUTPUT VOLTAGE

1

2

ICL7660S

3

4

ICL7611

+

+

100µF

-

800k

+5V LOGIC SUPPLY

16

8

7

6

5

15

1
2
3
4

4

ICL7660S

250k

VOLTAGE

ADJUST

12 11

IH5142

13

-

10µF

+

8
7
6
5

14

-

100µF

+

1
3

V

OUT

RS232
DATA
OUTPUT

+5V

-5V

FIGURE 21. RS232 LEVELS FROM A SINGLE 5V SUPPLY

Other Applications

Further information on the operation and use of the
ICL7660S may be found in AN051 “Principles and
Applications of the ICL7660 CMOS Voltage Converter”.

10

10µF

-

+

FN3179.5

March 6, 2008

Dual-In-Line Plastic Packages (PDIP)

www.BDTIC.com/Intersil

ICL7660S

N

D1

-C-

E1

-B-

A2

A

L

A

1

e

C

e

e

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

12 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru­sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).

6. E and are measured with the leads constrained to be per-

7. e

e

pendicular to datum .

A

and eC are measured at the lead tips with the leads uncon-

B

strained. e

must be zero or greater.

C

-C-

8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A-0.210 - 5.33 4

E

A1 0.015 - 0.39 -4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

C

L

A

C

B

B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 ­D 0.355 0.400 9.01 10.16 5

D1 0.005 - 0.13 -5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89

NOTESMIN MAX MIN MAX

Rev. 0 12/93

11

FN3179.5

March 6, 2008

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

ICL7660S

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12

FN3179.5

March 6, 2008