intersil ICL7126 DATA SHEET

®

ICL7126

Data Sheet October 25, 2004

3 1/2 Digit, Low Power, Single Chip A/D
Converter

The ICL7126 is a high performance, very low power

1

3

/2-digit, A/D converter. All the necessary active devices
are contained on a single CMOS IC, including seven
segment decoders, display drivers, reference, and cloc k. The
ICL7126 is designed to interface with a liquid crystal display
(LCD) and includes a backplane drive. The supply current of
100µA is ideally suited for 9V battery operation.

The ICL7126 brings together an unprecedented combination
of high accuracy, versatility, and true economy. It features
auto-zero to less than 10µV, zero drift of less than 1µV/

o

C,
input bias current of 10pA maximum, and rollover error of
less than one count. The versatility of true differential input
and reference is useful in all systems, b ut gives the designer
an uncommon advantage when measuring load cells, strain
gauges and other bridge-type transducers. And finally the
true economy of single power operation allows a high
performance panel meter or multi-meter to be built with the
addition of only 10 passive components and a display.

The ICL7126 can be used as a plug-in replacement for the
ICL7106 in a wide variety of applications, changing only the
passive components.

Ordering Information

TEMP. RANGE

PART NUMBER

(°C) PACKAGE

ICL7126CPL 0 to 70 40 Ld PDIP E40.6
ICL7126CPLZ

(Note 1)

0 to 70 40 Ld PDIP

(Pb-free) (Note 2)

NOTES:

1. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020C.

2. Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.

PKG.

DWG. #

E40.6

FN3084.5

Features

• 8,000 Hours Typical 9V Battery Life

• Guaranteed Zero Reading for 0V Input on All Scales

• True Polarity at Zero for Precise Null Detection

• 1pA Typical Input Current

• True Differential Input and Reference

• Direct LCD Display Drive - No External Components
Required

• Pin Compatible With the ICL7106

• Low Noise - Less Than 15µV

P-P

• On-Chip Clock and Reference

• Low Power Dissipation Guaranteed Less Than 1mW

• No Additional Active Circuits Required

• Pb-Free Available (RoHS Compliant)

Pinout

ICL7126 (PDIP)

TOP VIEW

OSC 1

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

OSC 2
OSC 3
TEST
REF HI
REF LO
C

+

REF

C

-

REF

COMMON
IN HI
IN LO
A-Z
BUFF
INT
V­G2 (10s)
C3

(100s)

A3
G3
BP/GND

(1s)

(10s)

(100s)

(1000) AB4

(MINUS)

V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3

POL

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

ICL7126

Absolute Maximum Ratings Thermal Information

Supply Voltage V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . .V+ to V-

Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . .V+ to V-

Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEST to V+

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
is measured with the component mounted on an evaluation PC board in free air.

2. θ

JA

Thermal Resistance (Typical, Note 2)

θ

JA

(oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . . -65

o

C to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

NOTE: Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.

o

o

C

C

Electrical Specifications T

= 25oC, V

A

= 100mV, f

REF

= 48kHz (Notes 1, 3)

CLOCK

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Zero Input Reading V

= 0.0V, Full Scale = 200mV -000.0 ±000.0 +000.0 Digital

IN

Reading

Ratiometric Reading V

Rollover Error -V

= V

lN

IN

, V

REF

= +VlN ≅ 200mV

= 100mV 999 999/10001000 Digital

REF

- ±0.2 ±1 Counts

Reading

Difference in Reading for Equal Positiv e and Negative
Inputs Near Full Scale

Linearity Full Scale = 200mV or Full Scale = 2V Maximum Deviation

- ±0.2 ±1 Counts

from Best Straight Line Fit (Note 5)
Common Mode Rejection Ratio V
Noise V

= ±1V, VIN = 0V, Full Scale = 200mV (Note 5) - 50 - µV/V

CM

= 0V, Full Scale = 200mV

IN

-15-µV

(Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5)
Leakage Current Input V
Zero Reading Drift V
Scale Factor Temperature Coefficient V

V+ Supply Current V
COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply

= 0V (Note 5) - 1 10 pA

lN

o

= 0V, 0

lN

= 199mV, 0

IN

(Ext. Ref. 0ppm/×oC) (Note 5)

= 0V (Does Not Include COMMON Current) - 70 100 µA

IN

C To 70

o

C To 70

o

C (Note 5) - 0.2 1 µV/oC

o

C,

-15ppm/

2.4 3.0 3.2 V

(With Respect to + Supply)
Temperature Coefficient of Analog Common 25kΩ Between Common and Positive Supply

-80-ppm/

(With Respect to + Supply) (Note 5)
Peak-To-Peak Segment Drive Voltage

V+ = to V- = 9V (Note 4) 4 5.5 6 V
Peak-To-Peak Backplane Drive Voltage

Power Dissipation Capacitance vs Clock Frequency - 40 - pF

NOTES:

3. Unless otherwise noted, specifications are tested using the circuit of Figure 1.

4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times conversion
rate. Average DC component is less than 50mV.

5. Not tested, guaranteed by design.

o

C

o

C

2

FN3084.5

Typical Application Schematics

ICL7126

IN

+ -

R

R

1

5

1MΩ

240kΩ

C

R

TEST

REF HI

REF LO

4

10kΩ

C

1

0.1µF

+

REF

C

-

REF

C

COM

IN HI

R

3

C

4

50pF

180kΩ

4039383736353433323130

OSC 1

OSC 2

OSC 3

ICL7126

V+D1C1B1A1F1G1E1D2C2B2
123456789

101112

DISPLAY

9V

+

-

5

0.01

C

2

0.22µF

IN LO

750Ω

R

2

C

3

180kΩ

0.047µF

28

29

27262524232221

INT

A-Z

BUFF

A2F2E2D3B3F3E3

13

14151617181920

C1 = 0.1µF

DISPLAY

V-

C3

A3

G2

G3

AB4

BP

POL

C2 = 0.22µF

= 0.047µF

C

3

C4 = 50pF

= 0.01µF

C

5

= 240kΩ

R

1

R

= 180kΩ

2

= 180kΩ

R

3

R4 = 10kΩ

= 1MΩ

R

5

FIGURE 1. ICL7126 TEST CIRCUIT AND T YPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED

FOR 200mV FULL SCALE

SET REF = 100.0mV

R

3

C

4

50pF

180kΩ

4039383736353433323130

OSC 2

OSC 3

TEST

REF HI

OSC 1

V+D1C1B1A1F1G1E1D2C2B2

123456789

FIGURE 2. ICL7126 CLOCK FREQUENCY 16kHz, 1 READING/S

R

1

240kΩ

R

4

10kΩ

C

0.1µF

1

+

REF

C

REF LO

1MΩ

-

REF

C

R

COM

IN

+ -

5

C

5

C

2

0.01

IN HI

IN LO

ICL7126

101112

DISPLAY

9V

+

-

R

2

C

3

0.33µF

180kΩ

28

29

A-Z

BUFF

A2F2E2D3B3F3E3

13

DISPLAY

0.15µF

27262524232221

V-

C3

G2

INT

14151617181920

C1 = 0.1µF
C2 = 0.33µF

= 0.5µF

C

3

C

= 50pF

4

= 0.01µF

C

5

R

= 240kΩ

A3

G3

BP

AB4

POL

1

= 180kΩ

R

2

= 180kΩ

R

3

= 10kΩ

R

4

R5 = 1MΩ

3

FN3084.5

Typical Application Schematics (Continued)

IN

+ -

ICL7126

9V

+

-

R

1

240kΩ

R

3

C

4

50pF

180kΩ

4039383736353433323130

OSC 1

TEST

OSC 2

OSC 3

REF HI

REF LO

R

4

10kΩ

C

1

0.1µF

+

REF

C

1MΩ

-

REF

C

R

COM

5

C

5

C

2

0.01

0.22µF

IN HI

IN LO

750Ω

R

2

C

3

180kΩ

0.047µF

28

29

27262524232221

V-

INT

A-Z

BUFF

DISPLAY

G2

ICL7126

V+D1C1B1A1F1G1E1D2C2B2A2F2E2D3B3F3
123456789

FIGURE 3. CLOCK FREQUENCY 48kHz, 3 READINGS/S

101112

DISPLAY

13

14151617181920

C1 = 0.1µF

= 0.22µF

C

2

C3 = 0.047µF

= 50pF

C

4

C5 = 0.01µF

= 240kΩ

C3

A3

G3

BP

E3

AB4

POL

R

1

R2 = 180kΩ

= 180kΩ

R

3

= 10kΩ

R

4

R

= 1MΩ

5

4

FN3084.5

Design Information Summary Sheet

• OSCILLATOR FREQUENCY
f

= 0.45/RC

OSC

> 50pF; R

C

OSC

f

(Typ) = 48kHz

OSC

• OSCILLATOR PERIOD

= RC/0.45

t

OSC

• INTEGRATION CLOCK FREQUENCY

CLOCK

= f

OSC

f

• INTEGRATION PERIOD

= 1000 x (4/f

t

INT

• 60/50Hz REJECTION CRITERION
t

INT/t60Hz

or t

• OPTIMUM INTEGRATION CURRENT

= 4µA

I

INT

• FULL-SCALE ANALOG INPUT VOLTAGE

(Typ) = 200mV or 2V

V

lNFS

• INTEGRATE RESIST O R

V

R

INT

-----------------=

I

INFS

INT

• INTEGRATE CAPACITOR

t

()I

INT

INT

--------------------------------=

V

INT

C

• INTEGRATOR OUTPUT VOLTAGE SWING

t

()I

V

INT

INT

--------------------------------=

C

INT

> 50kΩ

OSC

/4

OSC

lNT/t50Hz

()

INT

()

INT

)

= Integer

ICL7126

• DISPLAY COUNT

V

IN

COUNT 1000

×=

---------------

V

REF

• CONVERSION CYCLE
t

CYC

t

CYC

when f

= t
= t

OSC

x 4000

CL0CK

x 16,000

OSC

= 48KHz; t

CYC

= 333ms

• COMMON MODE INPUT VOLTAGE
(V- + 1V) < V

< (V+ - 0.5V)

lN

• AUTO-ZERO CAPACITOR

0.01µF < C

AZ

< 1µF

• REFERENCE CAPACITOR

0.1µF < C

• V

COM

REF

< 1µF

Biased between V+ and V-

• V

≅ V+ - 2.8V

COM

Regulation lost when V+ to V- < ≅6.8V;
If V
the V

is externally pulled down to (V + to V -)/2,

COM

circuit will turn off

COM

• ICL7126 POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
Digital supply is generated internally

≅ V+ - 4.5V

V

TEST

• ICL7126 DISPLAY: LCD
Type: Direct drive with digital logic supply amplitude

•V

MAXIMUM SWING:

INT

(V- + 0.5V) < V

< (V+ - 0.5V), V

INT

(Typ) = 2V

INT

Typical Integrator Amplifier Output Waveform (INT Pin)

AUTO ZERO PHASE

(COUNTS)
2999 - 1000

SIGNAL INTEGRATE

PHASE FIXED
1000 COUNTS

TOTAL CONVERSION TIME = 4000 x t

CLOCK

DE-INTEGRATE PHASE

0 - 1999 COUNTS

= 16,000 x t

OSC

5

FN3084.5

ICL7126

Detailed Description

Analog Section

Figure 4 shows the Functional Diagram of the Analog
Section for the ICL7126. Each measurement cycle is divided
into three phases. They are (1) auto-zero (A-Z), (2) signal
integrate (INT) and (3) de-integrate (DE).

Auto-Zero Phase

During auto-zero three things happen. First, input high and
low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
C

to compensate for offset voltages in the buffer amplifier,

AZ

integrator, and comparator . Since the comparator is included
in the loop, the A-Z accuracy is limited only by the noise of
the system. In any case, the offset referred to the input is
less than 10µV.

Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential v oltage can be within a wide
common mode range: up to 1V from either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog
COMMON to establish the correct common mode voltage. At
the end of this phase, the polarity of the integrated signal is
determined.

De-integrate Phase

The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator to output to return to zero. The time required for
the output to return to zero is proportional to the input signal.

Specifically, the digi tal reading displayed is:

V



IN

Display Count = 1000

---------------

.



V



REF

Differential Input

The input can accept differential voltages anywhere within
the common mode range of the input amplifier, or specifically
from 0.5V below the positive supply to 1V above the negative
supply. In this range, the system has a CMRR of 86dB
typical. However, care must be exercised to assure the
integrator output does not saturate. A worst case condition
would be a large positive common mode voltage with a near
full-scale negative differential input voltage. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common mode
voltage. For these critical applications the integrator output
swing can be reduced to less than the recommended 2V full
scale swing with little loss of accuracy. The integrator output
can swing to within 0.5V of either supply without loss of
linearity.

IN HI

COMMON

IN LO

C

REF

R

INT

+

A-Z

REF

REF HI

34

36

A-Z A-Z

DE- DE+

A-Z AND DE(±)

C

V+

1µA

31

INT

32

30

INT

REF LO

35

DE-DE+

FIGURE 4. ANALOG SECTION OF ICL7126

C

-

REF

33

-

+

INPUT

HIGH

N

26

V -

BUFFER

28 29 27

+

V+

1

2.8V

-

C

AZ

A-Z INT

INTEGRATOR

6.2V

INPUT
LOW

A-Z

-

+

COMPARATOR

6

C

INT

TO

+

DIGITAL
SECTION

FN3084.5

V+

REF HI

REF LO

ICL7126

FIGURE 5A.

V+

V-

6.8V
ZENER

I

Z

ICL7126

FIGURE 5.

V+

ICL7126

REF HI

REF LO

COMMON

200kΩ

FIGURE 5B.

V+

27kΩ

ICL8069

1.2V
REFERENCE

Differential Reference

The reference voltage ca n be gen er ated an yw here with in the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity
on its nodes. If there is a large common mode voltage , the
reference capacitor can gain charge (increase v oltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integra te a negative
input signal. This difference in reference for positiv e or
negative input voltage wil l give a roll-over error. Howe ver, b y
selecting the reference capacitor large en ough in comparison
to the stray capacitance, this error can be held to less than 0.5
count worst case. (See Component Value Selection.)

Analog COMMON

This pin is included primarily to set the common mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 2.8V
more negative than the positive supply. This is selected to
give a minimum end-of-life battery voltage of about 6.8V.
However, analog COMMON has some of the attributes of a
reference voltage. When the total supply voltage is large
enough to cause the zener to regulate (<6.8V), the
COMMON voltage will have a low voltage coefficient
(0.001%/V), low output impedance (≅15Ω), and a
temperature coefficient typically less than 80ppm/

o

C.

COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If
reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.

Within the lC, analog COMMON is tied to an N channel FET
that can sink approximately 3mA of current to hold the volt­age 2.8V below the positive supply (when a load is trying to
pull the common line positive). However, there is only 1µA of
source current, so COMMON may easily be tied to a more
negative voltage thus overriding the internal reference.

The limitations of the on-chip reference should also be
recognized, however . The re ference Temperature Coeffi cient
(TC), can cause some degradation in performance.
Temperature changes of 2

o

C to 8oC, typical for instruments,
can give a scale factor error of a count or more. Also the
common voltage will have a poor voltage coefficient when the
total supply voltage is less than that which will cause the zene r
to regulate (<7V). These problems are eliminated if an
external reference is used, as shown in Figure 5.

Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog

7

FN3084.5

ICL7126

V+

ICL7126

BP

21

TEST

37

FIGURE 6. SIMPLE INVERTER FOR FIXED

DECIMAL POINT

1MΩ

TO LC D
DECIMAL
POINT

TO LCD
BACKPLANE

TEST

The TEST pin serves two functions. It is coupled to the
internally generated digital supply through a 500Ω resistor.
Thus it can be used as the negative supply for externally
generated segment drivers such as decimal points or any
other presentation the user may want to include on the LCD
display. Figures 6 and 7 show such an application. No more
than a 1mA load should be applied.

The second function is a “lamp test”. When TEST is pulled
high (to V+) all segments will be turned on and the display
should read “-1888”. The TEST pin will sink about 10mA
under these conditions.

V+

BP

ICL7126

TEST

FIGURE 7. EXCLUSIVE ‘OR’ GATE FOR

DECIMAL

POINT

SELECT

V+ = DP ON
GND = DP OFF

DECIMAL POINT DRIVE

V+

CD4030

GND

TO LC D
DECIMAL
POINTS

to 3000 counts). For signals less than full-scale, auto-zero gets
the unused portion of reference de-integrate. This makes a
complete measure cycle of 4,000 counts (16,000 clock pulses)
independent of input voltage. For three readings/second, an
oscillator frequency of 48kHz would be used.

To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 60kHz, 48kHz, 40kHz, 33

1

/3kHz, etc. should

be selected. For 50Hz rejection, oscillator frequencies of

2

66

/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that
40kHz (2.5 readings/sec.) will reject both 50Hz and 60Hz
(also 400Hz and 440Hz).

CAUTION: In the l amp test mode, the segments have a constant DC v olt­age (no square-wave) and may burn the LCD display if left in this mode for
several minutes.

Digital Section

Figure 8 shows the digital section for the ICL7126. An internal
digital ground is generated from a 6V Zener diode and a large
P-Channel source follower . This supply is made stiff to absorb
the relative large capacitive currents when the back plane (BP)
voltage is switched. The BP frequency is the clock frequency
divided by 800. For three readings/second this is a 60Hz
square wave with a nominal amplitude of 5V . The segments are
driven at the same frequency and amplitude and are in phase
with BP when OFF, b ut out of phase when ON. In all cases
negligible DC voltage exists across the segments. The polarity
indication is “ON” for negative analog inputs. If IN LO and IN HI
are reversed, this indication can be rev ersed also, if desired.

System Timing

Figure 9 shows the clocking arrangement used in the
ICL7126. Two basic clocking arrangements can be used:

Figure 9A, an external oscillator connected to pin 40.
Figure 9B, an R-C oscillator using all three pins.
The oscillator frequency is divided by four before it clocks the

decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000 counts),
reference de-integrate (0 to 2000 counts) and auto-zero (1000

8

FN3084.5

ICL7126

a

b

LCD PHASE DRIVER

a

b

f

g

c

e

d

BACKPLANE

21

TYPICAL SEGMENT OUTPUT

INTERNAL DIGITAL GROUND

THREE INVERTERS.

†

ONE INVERTER SHOWN FOR CLARITY.

0.5mA

2mA

V+

SEGMENT

OUTPUT

FROM COMPARATOR OUTPUT

TO SWITCH DRIVERS

CLOCK

†

40 39 38

OSC 1

OSC 2

FIGURE 8. DIGITAL SECTION

7

SEGMENT

DECODE

LATCH

1000’s 100’s 10’s 1’s

COUNTER COUNTER COUNTER COUNTER

÷4

INTERNAL

DIGITAL

GROUND

OSC 3

7

SEGMENT

DECODE

LOGIC CONTROL

1

HLDR

7

SEGMENT

DECODE

VTH = 1V

÷200

6.2V

500Ω

35

V+

TEST

37

26

V-

INTERNAL TO PART

40 39

TEST ICL7126

FIGURE 9A. EXTERNAL SIGNAL

INTERNAL TO PART

÷4

38

CLOCK

40 39

÷4

38

R

C

CLOCK

FIGURE 9B. RC OSCILLATOR

FIGURE 9. CLOCK CIRCUITS

9

FN3084.5

Component Value Selection

Integrating Resistor

Both the buffer amplifier and the integrator have a class A
output stage with 6µA of quiescent current. They can
supply ~1µA of drive current with negligible nonlinearity.
The integrating resistor should be large enough to remain
in this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2V full-scale, 1.8MΩ is near
optimum and similarly a 180kΩ for a 200mV scale.

Integrating Capacitor

The integrating capacitor should be selected to giv e the
maximum voltage s win g th at ensures tole r ance b ui ld-up will
not saturate the integrator swing (approximately. 0.3V from
either supply). When the analog COMMON is used as a
reference, a nominal ±2V full-scale integrator swing is fine. F or
three readings/second (48kHz clock) nominal values for C
are 0.047µF, for 1/s (16kHz) 0.15µF. Of course, if different
oscillator frequencies are used, these values should be
changed in inverse proportion to maintain the same
output swing.

The integrating capacitor should have a low dielectric
absorption to prevent roll-over errors. While other types may
be adequate for this application, polypropylene capacitors
give undetectable errors at reasonable cost.

At three readings/sec, a 750Ω resistor should be placed in
series with the integrating capacitor, to compensate for
comparator delay.

Auto-Zero Capacitor

The size of the auto-zero capacitor has some influence on
the noise of the system. For 200mV full-scale where noise is
very important, a 0.32µF capacitor is recommended. On the
2V scale, a 0.33µF capacitor increases the speed of
recovery from overload and is adequate for noise on this
scale.

Reference Capacitor

A 0.1µF capacitor gives good results in most applications.
However, where a large common mode voltage exists (i.e.,
the REF LO pin is not at analog COMMON) and a 200mV
scale is used, a larger value is required to prevent roll-over
error. Generally 1µF will hold the roll-over error to 0.5 count
in this instance.

lNT

ICL7126

V

should equal 100mV and 1V, respectively. How e ver, in

REF

many applications where the A/D is connected to a transducer,
there will exist a scale factor other than unity between the input
voltage and the digital reading. For instance, in a weighing
system, the designer might like to have a full-scale reading
when the voltage from the transducer is 0.682V. Instead of
dividing the input down to 200mV, the designer should use the
input voltage directly and select V

= 0.341V . Suitable v alues

REF

for integrating resistor 330kΩ. This makes the system slightly
quieter and also avoids a divider network on the input. Another
advantage of this system occurs when a digital reading of zero
is desired for V

≠ 0. Temperature and weighing systems with

IN

a variable fare are e xamples . This offset reading can be
conveniently generated by connecting the v oltage transducer
between IN HI and COMMON and the variable (or fixed) offset
voltage between COMMON and IN LO.

Typical Applications

The ICL7126 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility
of these A/D converters.

The following application notes contain very useful
information on understanding and applying this part and are
available from Intersil Corporation.

Application Notes

NOTE # DESCRIPTION

AN016 “Selecting A/D Converters”
AN017 “The Integrating A/D Converter”
AN018 “Do’s and Don’ts of Applying A/D Converters”
AN023 “Low Cost Digital Panel Meter Designs”
AN032 “Understanding the Auto-Zero and Common Mode

Performance of the ICL7136/7/9 Family”

AN046 “Building a Battery-Operated Auto Ranging DVM with

the ICL7106”

AN052 “Tips for Using Single-Chip 3

1

/2 Digit A/D Converters”

Oscillator Components

For all ranges of frequency a 50pF capacitor is recommended
and the resistor is selected from the approxi mation equ ation

0.45

-----------

f

RC

For 48kHz clock (3 readings/sec), R = 180kΩ•∼

Reference Voltage

The analog input required to generate full-scale output (2000
counts) is: V

lN

= 2V

. Thus, for the 200mV and 2V scale,

REF

10

FN3084.5

Typical Applications

g

OSC 1

40

OSC 2

39

OSC 3

38

TEST

37

REF HI

36

V+

35

C

34

REF

33

C

REF

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

32
31
30
29
28
27
26
25
24
23
22
21

750kΩ

TO DISPLAY

COMMON

BP/GND

180kΩ

50pF

0.1µF

0.33µF
180kΩ

TO BACKPLANE

10kΩ 220kΩ

0.047µF

SET V
= 100mV

1MΩ

0.01µF

REF

+

IN

-

+

9V

-

ICL7126

OSC 1
OSC 2
OSC 3

TEST

REF HI

V+

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

BP/GND

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

560kΩ

50pF

0.1µF

0.33µF
180kΩ

0.15µF

TO DISPLAY

20kΩ

SET V
= 100mV

1MΩ

0.01µF

REF

V+

27kΩ200kΩ

+

IN

-

V-

Values shown are for 200mV full scale, 3 readings/sec., floatin
supply voltage (9V battery).

FIGURE 10. ICL7126 USING THE INTERNAL REFERENCE

OSC 1
OSC 2
OSC 3

TEST

REF HI

V+

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V

G2

C3
A3

G3

BP/GND

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

­25
24
23
22
21

180kΩ

50pF

0.1µF

0.22µF

1.8MΩ

0.047µF750Ω

TO DISPLAY

TO BACK PLANE

250kΩ

0.01µF

SET V
= 1.000V

240kΩ

1MΩ

REF

V +

+

IN

-

V

IN LO is tied to COMMON, thus establishing the correct common
mode voltage. COMMON acts as a pre-regulator for the refe rence.
Values shown are for 1 reading/sec.

FIGURE 11. ICL7126 WITH AN EXTERNAL BAND-GAP

REFERENCE (1.2V TYPE)

OSC 1

40

OSC 2

39

OSC 3

38

TEST

37

REF HI

36

V+

35

C

34

REF

33

C

REF

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

32
31
30
29
28
27
26
25
24
23
22
21

COMMON

-

BP/GND

100kΩ

100pF

0.1µF

0.47µF
47kΩ

0.22µF

TO DISPLAY

SET V
= 100mV

1kΩ 10kΩ

1.2V (ICL8069)
1MΩ

0.01µF

REF

+5V

15kΩ

+

IN

-

3 reading/s. For 1 reading/sec., delete 750Ω resistor, change C
R

to values of Figure 11.

OSC

INT

FIGURE 12. RECOMMENDED COMPONENT V ALUES FOR 2.0V

FULL SCALE

11

,

Since low TC zeners have breakdown voltages ~6.8V, diode must be
placed across the total supply (10V). As in the case of Figure 12, IN
LO may be tied to COMMON.

FIGURE 13. ICL7126 WITH ZENER DIODE REFERENCE

FN3084.5

Typical Applications (Continued)

r

OSC 1
OSC 2
OSC 3

TEST

REF HI

V+

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

GND

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

†

50pF

20kΩ 100kΩ

0.1µF

0.01µF

0.33µF
180kΩ

†

TO DISPLAY

TO BACK PLANE

SET V

REF

= 100mV

27kΩ

1.2V (ICL8069)
1MΩ

+5V

+

IN

-

ICL7126

OSC 1
OSC 2
OSC 3

TEST

REF HI

V+

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

GND

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

†

50pF

0.1µF

0.33µF

R

INT

†

TO DISPLAY

V+

TO BACK PLANE

An external reference must be used in this application, since the
voltage between V+ and V- is insufficient for correct operation of the
internal reference.

† indicates values depend on clock frequency.

FIGURE 14. ICL7126 OPERATED FROM SINGLE +5V SUPPLY

OSC 1
OSC 2
OSC 3

TEST

REF HI

V+

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

BP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

†

50pF

0.1µF

0.01µF

0.33µF

†

TO DISPLAY

he resistor values within the bridge are determined by the desired

ensitivity. † indicates values depend on clock frequency.

FIGURE 15. ICL7126 MEASURING RATIOMETRIC V ALUES OF

SCALE
FACTOR
ADJUST

100kΩ 1MΩ
200kΩ 470kΩ

ZERO
ADJUST

390kΩ

TO BACKPLANE

QUAD LOAD CELL

100kΩ

SILICON NPN
MPS 3704 OR
SIMILAR

+

9V

-

silicon diode-connected transistor has a temperature coefficient of about -2mV/oC. Calibration is achieved by placing the sensing transistor in

ce water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-facto

otentiometer adjusted for a 100.0 reading.

FIGURE 16. ICL7126 USED AS A DIGITAL CENTIGRADE THERMOMETER

12

FN3084.5

Typical Applications (Continued)

O /RANGE

/RANGE

U

V+

TO LOGIC

V

CC

ICL7126

1

V+
D1

2

C1

3

B1

4

A1

5

F1

6

G1

7

E1

8

D2

9

C2

10

B2

11

A2

12

F2

13

E2

14

D3

15

B3

16

F3

17

E3

18

AB4

19

POL

20

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

G2
C3
A3
G3
BP

40
39
38
37
36
35

TO

LOGIC

34

GND

33
32
31
30
29
28
27
26

V-

V­25
24
23
22
21

CD4023 OR

74C10

CD4077

FIGURE 17. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM ICL7126 OUTPUTS

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V
G2
C3
A3
G3

BP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

­25
24
23
22
21

TO PIN 1

180kΩ

50pF

0.22µF

750Ω

TO DISPLAY

10kΩ 220kΩ

0.1µF

180kΩ

0.047µF

TO BACKPLANE

10µF

10µF

SCALE FACTOR ADJUST
(V

= 100mV FOR AC TO RMS)

REF

470kΩ

1µF

4.3kΩ

+

9V

-

100pF

(FOR OPTIMUM

BANDWIDTH)

10kΩ

1N914

1µF

10kΩ

5µF

1µF

0.22µF

ICL7611

+

2.2MΩ

Test is used as a common-mode reference level to ensure compatibility with most op amps.

-

100kΩ

AC IN

13

FIGURE 18. AC TO DC CONVERTER WITH ICL7126

FN3084.5

Die Characteristics

ICL7126

DIE DIMENSIONS:

127 mils x 149 mils

METALLIZATION:

Type: Al
Thickness: 10k

Å ±1kÅ

Metallization Mask Layout

(15)

D

3

B

(16)

3

F

(17)

3

(18)

E

3

AB

(19)

4

E

(14)

PASSIVATION:

Type: PSG Nitride
Thickness: 15kÅ ±3kÅ

WORST CASE CURRENT DENSITY:

4

9.1 x 10

ICL7126

G

E

D

C

A

(12)

B

2

2

(11)

(10)

2

2

(9)

(8)

1

1

(7)

F

2

2

(13)

A/cm

F

1

(6)

2

A

1

(5)

(4) B

1

(3) C

1

(2) D

1

(1) V+

POL (20)

BP/GND (21)

G

(22)

3

(23)

A

3

(24)

C

3

(25)

G

2

V- (26)

(27)
INT

(28)

BUFF

(29)

A/Z

(30)

IN LO

(31)

IN HI

(32)

COMM

C

(33)

REF-

C

(34)

REF+

(35)

LO HI

REF

(40) OSC 1

(39) OSC 2

(38) OSC 3

(37) TEST

(36)

REF

14

FN3084.5

Dual-In-Line Plastic Packages (PDIP)

-

.

ICL7126

N

D1

-C-

E1

-B-

A1

A2

A

L

e

C

S

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1
B1

12 3 N/2

-A­D

e

B

0.010 (0.25) C AMB

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be per-

7. e

e

pendicular to datum .

A

and eC are measured at the lead tips with the leads uncon-

B

strained. e

must be zero or greater.

C

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dam
bar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm)

E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.250 - 6.35 4

E

A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 -

C

L

e

A

C

e

B

B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 ­D 1.980 2.095 50.3 53.2 5

D1 0.005 - 0.13 - 5

E 0.600 0.625 15.24 15.87 6

E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.600 BSC 15.24 BSC 6

- 0.700 - 17.78 7

L 0.115 0.200 2.93 5.08 4

N40 409

NOTESMIN MAX MIN MAX

Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

15

FN3084.5