intersil ICL7112 DATA SHEET
查询ICL7112供应商
January 1998
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ICL7112
12-Bit, High-Speed,
CMOS µP-Compatible A/D Converter
Features
• 12-Bit Resolution and Accuracy
• No Missing Codes
• Microprocessor Compatible Byte-Organized Buffered
Outputs
• Auto-Zeroed Comparator for Low Offset Voltage
• Low Linearity and Gain Errors
• Low Power Consumption (60mW)
• No Gain or Offset Adjustment Necessary
• Provides 3% Usable Overrange
• Fast Conversion (40µs)
Description
The ICL7112 is a monolithic 12-bit resolution, fast
successive approximation A/D converter. It uses thin film
resistors and CMOS circuitry combined with an on-chip
PROM calibration table to achieve 12-bit linearity without
laser trimming. Special design techniques used in the DAC
and comparator result in high speed operation, while the
fully static silicon-gate CMOS circuitry keeps the power
dissipation very low.
Microprocessor bus interfacing is eased by the use of
standard memory WRite
signals, combined with Chip
digital output pins are byte-organized and three-state gated
for bus interface to 8-bit and 16-bit systems.
The lCL7112 provides separate Analog and Digital grounds
for increased system accuracy. Operating with ±5V supplies,
the lCL7112 accepts 0V to +10V input with a -10V reference
or 0V to -10V input with a +10V reference.
and ReaD cycle timing and control
Select and Address pins. The
Ordering Information
RESOLUTION WITH NO MISSION
PART NO. TEMP. RANGE (oC) PACKAGE
ICL7112JCDL 0 to 70 40 Ld CERDIP 11-Bit
CODES
ICL7112KCDL 0 to 70 40 Ld CERDIP 12-Bit
ICL7112LCDL 0 to 70 40 Ld CERDIP 12-Bit (Note)±
ICL7112JIDL -25 to 85 40 Ld CERDIP 11-Bit
ICL7112KIDL -25 to 85 40 Ld CERDIP 12-Bit
ICL7112LIDL -25 to 85 40 Ld CERDIP 12-Bit (Note)±
ICL7112JMDL -55 to 125 40 Ld CERDIP 11-Bit
ICL7112KMDL -55 to 125 40 Ld CERDIP 12-Bit
ICL7112LMDL -55 to 125 40 Ld CERDIP 12-Bit (Note)±
NOTE: Over operating temperature range.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-71 43
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
6-1
File Number 3639.1
Pinout
AGNDf
DGND
(MSB) D
(LSB) D
NC
CS
RD
A
BUS
D
D
D
D
D
D
D
D
D
D
NC
ICL7112
ICL7112
TOP VIEW
1
2
3
4
5
0
6
7
8
11
9
10
10
9
11
8
12
7
13
6
14
5
15
4
16
3
17
2
18
1
19
0
20
ICL7112
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
AGNDs
V
REF
V
IN
COMP
-
V
C
AZ
WR
TEST
OSC2
OSC1
TEST
PROG
+
V
OVR
EOC
NC
NC
NC
NC
Functional Block Diagram
V
REF
AGND
Y
DGND
+
-
V
DAC
R-1.85R
PROM
LATCH
V
IN
R
IN
COMP
+
C
AZ
-
CONTROL LOGIC
ADDER
ACCCUM
SAR
OSC1 OSC2
LATCH
WR
EOC
THREE-STATE
OUTPUTS
CSRD
0
OVR
D
(MSB)
11
D
(LSB)
0
BUSA
6-2
ICL7112
Absolute Maximum Ratings T
Supply Voltage (V+ to DGND) . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Supply Voltage (V
V
, VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
REF
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1V to -1V
V
, VIN, AGND Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
REF
Digital I/O Pin Voltages. . . . . . . . . . . . . . . . . . . . . -0.3V to V+ +0.3V
PROG to DGND Voltage . . . . . . . . . . . . . . . . . . . . V
-
to DGND). . . . . . . . . . . . . . . . . . . +0.3V to -6.5V
=25oC Thermal Information
A
Thermal Resistance (Typical, Note 1) θ
CERDIP Package . . . . . . . . . . . . . . . . ___ ___
Maximum Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . 500mW
Derate above 70
o
C at 10mW/oC
Maximum Junction Temperature (Ceramic Package) . . . . . . . . 175
-
to (V+ +0.3V)
Maximum Storage Temperature Range . . . . . . . . . . -65
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
(oC/W) θJC (oC/W)
JA
o
C to 150oC
o
o
Operating Conditions
ICL7112XCXX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70
ICL7112XIXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 to 70
ICL7112XMXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 125
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
is measured with the component mounted on an evaluation PC board in free air.
1. θ
JA
2. All voltages with respect to DGND, unless otherwise noted.
3. Assumes all leads soldered or welded to printed circuit board.
Electrical Specifications Test Conditions: V+ = +5V, V- = -5V, V
PARAMETER SYMBOL
ACCURACY
Resolution RES 12 Bits
Resolution with No
Missing Codes
Integral Linearity
Error
Unadjusted Full
Scale Error
RES
Notes 4, 5, 6 R
(NMC)
I
LE
Notes 4, 5 R
FSE Adjust-
able to
Zero
Zero Error ZE Notes 4, 5 R
ANALOG INPUT
Analog Input
Range
Input Resistance R
Temperature
Coefficient of R
V
IN
IN
Notes 5, 8 4 - 9 4 - 9 4 - 9 kΩ
TC (RIN)T
IN
REFERENCE INPUT
Analog Reference V
Reference
Resistance
R
REF
REF
POWER SUPPLY SENSITIVITY
Power Supply
PSRR V
+
Rejection Ration
LOGIC INPUT
Low State
V
IL
Input Voltage
TEST
CONDITIONS
T
-T
MIN
MAX
T
-T
MIN
MAX
CR
T
MIN TMAX
IR
T
-T
MIN
MAX
MR
T
-T
MIN
MAX
T
-T
MIN
MAX
-T
MIN
MAX
, V- = 4.5 -5.5V RM
T
-T
MIN
MAX
T
-T
MIN
MAX
11
M
10
--±0.024
M
--±0.10
M
--±0.10
M
--±0.10
M
--±1
M
0 -10.30-10.30-10.3V
- -300 - - -300 - - -300 - ppm/oC
- -10.0 - - -10.0 - - -10.0 - V
-5 - -5--5-kΩ
- ±0.5 ±1
--0.8--0.8--0.8V
= -10V, TA = 25oC, f
REF
= 500kHz, Unless Otherwise Noted
CLK
JKL
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
--1211--1212--
±0.030
±0.12
±0.13
±0.14
±1.5
±2
--±0.012
±0.020
--±0.08
±0.10
--±0.08
±0.11
--±0.08
±0.12
--±1
±1.5
- ±0.5 ±1
±2
--±0.012
±0.020
--±0.08
±0.10
--±0.08
±0.11
--±0.08
±0.12
--±1
±1.5
- ±0.5 ±1±2LSB
Bits
%FSR
%FSR
C
C
6-3
ICL7112
Electrical Specifications Test Conditions: V+ = +5V, V- = -5V, V
TEST
PARAMETER SYMBOL
High State
V
IH
CONDITIONS
T
MIN
-T
MAX
2.4 - - 2.4 - - 2.4 - - V
= -10V, TA = 25oC, f
REF
JKL
Input Voltage
Logic Input
I
LIH
0 < VIN < V
+
- 110-110-110µA
Current
Logic Input
C
IN
- 15 - -15 - -15 - pF
Capacitance
LOGIC OUTPUT
Low State Output
Voltage
High State Output
Voltage
Three-State Output
Current
Logic Output
Capacitance
V
V
I
C
OL
OH
OX
OUT
= 1.6mA
OUT
I
OUT
0 < V
= -200µA
< V
OUT
T
T
+
MIN
MIN
-T
-T
MAX
MAX
Three-State - 15 - - 15 - - 15 - pF
--0.4--0.4--0.4V
2.8 - - 2.8 - - 2.8 - - V
-1 - -1--1-µA
I
POWER REQUIREMENTS
Supply Voltage
Range
Supply Current,
I+, I-
V
SUPPLY
I
SUPPLY
Functional Operation Only ±4.5 - ±6.0 ±4.5 - ±6.0 ±4.5 - ±6.0 V
T
MIN
-T
R
MAX
-246-246-246mA
M
NOTES:
4. Full scale range (FSR) is 10V (reference adjusted).
5. Assume all leads are soldered or welded to printed circuit board.
6. “J” and “K” versions not production tested. Guaranteed by Integral Linearity Test.
7. Typical values are not tested, for reference only.
8. Not production tested. Guaranteed by design.
= 500kHz, Unless Otherwise Noted
CLK
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
AC Electrical Specifications Test Conditions V + = +5V, V- = -5V, T
derived from extensive characterization testing. Parameters are not production tested
PARAMETER SYMBOL
READ CYCLE TIMING
Propagation Delay CS
Propagation Delay A0 to Data t
Propagation Delay RD
Propagation Delay Data to Three-State t
Propagation Delay EOC High to Data t
to Date t
to Data t
cd
ad
rd
rx
ed
WRITE CYCLE TIMING
WR
Low Time t
Propagation Delay WR Low to EOC Low t
EOC High Time t
Conversion Time t
Clock Frequency Range f
wr
we
eo
conv
CLK
NOTE:
9. All typical values have been characterized, but are not tested.
RD Low, A0 Valid - - 200
CS Low, RD Low - - 200
CS Low, A0 Valid - - 200
Wait Mode 1 - 2
Free Run Mode 0.5 - 1.5 1/f
Functional Operation Only - 500 - kHz
TEST
CONDITIONS MIN TYP MAX UNITS
= 25oC, f
A
= 500kHz, unless otherwise noted. Data
CLK
--150
--200
150 - - ns
--20
ns
CLK
6-4
ICL7112
Pin Descriptions
PIN NO. NAME DESCRIPTION
1 No connection.
2AGND
3CS
4RD
5A
0
6 BUS Bus select (low = outputs enabled by A
7 DGND Digital GrouND return.
8D
9D
10 D
11 D
12 D
13 D
14 D
15 D
16 D
17 D
18 D
11
10
9
8
7
6
5
4
3
2
1
19 D0 Bit 0 (least significant bit).
20 No connection.
21 No connection.
22 No connection.
23 No connection.
24 No connection.
25 EOC End of conversion flag (low = busy, high = conversion complete).
26 OVR OVerRange flag (valid at end of conversion when output code exceeds full-scale;
27 V
+
28 PROG Used for programming only. Must tie to V
29 TEST Used for programming only. Must tie to V
30 OSC1 Oscillator inverter input.
31 OSC2 Oscillator inverter output.
32 TEST Must tie to V
33 WR
34 C
35 V
AZ
-
36 COMP Used in test, tie to V
37 V
38 V
IN
REF
39 AGND
40 No connection
NOTE: The voltage of CAZ is driven; NEVER connect directly to ground.
FORCE input for analog ground.
f
Chip Select enables reading and writing (active low).
ReaD (active low).
Byte select (low = D0 -D7, high = D8 -D11, OVR).
Bit 11 (most significant bit).
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
three-state output enabled with high byte).
Positive power supply input.
+
for normal operation.
WRite pulse input (low starts new conversion).
Auto-zero capacitor connection (Note).
Negative power supply input.
SENSE line for input voltage.
SENSE line for reference input.
SENSE line for analog ground.
s
, high = all outputs enabled together).
0
High Byte
Output
Data
Bits
(High =True)
Low Byte
+
for normal operation.
+
for normal operation.
-
.
6-5
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