intersil ICL7104 DATA SHEET

查询ICL7104供应商

August 1997

ICL8052/ICL7104,

ICL8068/ICL7104

14-Bit/16-Bit, Microprocessor-

Compatible, 2-Chip, A/D Converter

Features

• 16-Bit/14-Bit Binary Three-State Latched Outputs Plus
Polarity and Overrange

• Ideally Suited for Interface to UARTs and
Microprocessors

• Conversion on Demand or Continuously

• Guaranteed Zero Reading for 0V Input

• True Polarity at Zero Count for Precise Null Detection

• Single Reference Voltage for True Ratiometric
Operation

• Onboard Clock and Reference

• Auto-Zero, Auto-Polarity

• Accuracy Guaranteed to 1 Count

• All Outputs TTL Compatible

• ±4V Analog Input Range

• Status Signal Available for External Sync, A/Z in
Preamp, Etc.

Description

The ICL7104, combined with the ICL8052 or ICL8068,
forms a member of Intersil’ high performance A/D converter
family. The ICL7104-16, performs the analog switching and
digital function for a 16-bit binary A/D converter, with full
three-state output, UART handshake capability, and other
outputs for easy interfacing. The ICL7014-14 is a 14-bit
version. The analog section, as with all Intersil’ integrating
converters, provides fully precise Auto-Zero, Auto-Polarity
(including ±0 null indication), single reference operation,
very high input impedance, true input integration over a
constant period for maximum EMI rejection, fully
rationmetric operation, over-range indication, and a
medium quality built-in reference. The chip pair also offers
optional input buffer gain for high sensitivity applications, a
built-in clock oscillator, and output signals for providing an
external Auto-Zero capability in preconditioning circuitry,
synchronizing external multiplexers, etc.

Ordering Information

TEMP.

PART NUMBER

ICL8052CPD 0 to 70 14 Ld PDIP E14.3

lCL8052CDD 0 to 70 14 Ld CERDIP F14.3

RANGE (oC) PACKAGE

PKG.

NO.

lCL8052ACPD 0 to 70 14 Ld PDIP E14.3

ICL8052ACDD 0 to 70 14 Ld CERDIP F14.3

ICL8068CDD 0 to 70 14 Ld CERDIP F14.3

ICL8068ACDD 0 to 70 14 Ld CERDIP F14.3

lCL8068ACJD 0 to 70 14 Ld CERDIP F14.3

ICL7104-14CPL 0 to 70 40 Ld PDIP E40.6

lCL7104-16CPL 0 to 70 40 Ld PDIP E40.6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

5-6

File Number 3091.1

Pinouts

ICL8052/ICL7104, ICL8068/ICL7104

COMP OUT

REF CAP

REF BYPASS

GND

REF OUT

REF SUPPLY

ICL8052/ICL8068

(CERDIP, PDIP)

TOP VIEW

V-

1
2
3
4
5
6
7

(OUTLINE DWGS DD, JD, PD)

V

REF

-1.2V

ICL8052/
ICL8068

INT OUT

14

+BUFF IN

13

+INT IN

12

-INT IN

11

-BUFF IN

10

BUFF OUT

9

V++

8

V++

DIG GND

STTS

POL

OR
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10

BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2

ICL7104

(PDIP)

TOP VIEW

ICL7104-14ICL7104-16 ICL7104-14 ICL7104-16

DIG GND

BIT 14
BIT 13
BIT 12
BIT 11
BIT 10

V++

STTS

POL

OR

BIT 9

NC

NC
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2

1
2
3
4
5
6
7
8
9

10

ICL7104-14

(OUTLINE DWGS DL,

11
12
13
14
15
16
17
18
19
20

JL, PL)

40

V-

39

COMP IN

38

REFCAP 1

37

V
AZ

36

ANALOG

35

GND
REFCAP 2

34

BUF IN

33

ANALOG I/P

32

V+

31

CE/LD

30

SEN

29

R/

28

MODE

27

CLK 2

26

CLK 1

25

CLK 3

24

HBEN

23

LBEN

22

BIT 1

21

REF

H

HBEN
MBEN

Functional Block Diagram

-15V

+15V

BUF OUT

A1

8052/8068

SW9

34

REF CAP (2)REF CAP (1)

5kΩ

10µF

ANALOG

INPUT

ANALOG

GND

V

REF
OUT

300pF

REF

10kΩ

-BUF IN
10

1

78

6

INT.

3

REF.

+BUF IN5

+BUF IN AZ

SW3

37

SW5

SW4

32

35

SW7

BUFFER

13

SW6

SW8 SW2

38

C

REF

-

+

FIGURE 1. ICL8052A (8068A)/ICL7104 16-BIT/14-BIT A/D CONVERTER FUNCTIONAL DIAGRAM

R

INT

C

INTEG.

-

A2

+

12+INT IN

SW1

INT

C

-1.2V

AZ

INT OUT-INT IN
14119

COMP.

-

A3

+

COMP IN

CROSSING

DETECTOR

2

50kΩ

ZERO

COMP
OUT

7104

+5V

-15V

300kΩ

393633

+15V31+5V

BITS

14 1316 15 10 912 11 6 587 2143OR POL

8 96 7 12 1310 11 16 1714 15 20 2118 195 4

THREE-STATE OUTPUTS

LATCHES

COUNTER

CONTROL LOGIC

40

21

CLOCK

-15V

25

26

CLOCK

(2)(1)

STTS

24

23 MBEN

22

30 CE/LD

29

27

28

3

HBEN

LBEN

SEN

MODE

R/

H

5-7

ICL8052/ICL7104, ICL8068/ICL7104

Pin Descriptions

PIN NO. SYMBOL OPTION DESCRIPTION

1 V++ Positive Supply Voltage: Nominally +15V.

2 GND Digital Ground: 0V, ground return.

3 STTS Status Output: HI during integrate and deintegrate until data is latched. LO when analog section

is in auto-zero configuration.

4 POL Polarity: Three-state output. HI for positive input.

5 OR Over Range: Three-state output.

6 BIT 16

BIT 14

7 BIT 15

BIT 13

8 BIT 14

BIT 12

9 BIT 13

BIT 11

10 BIT 12

BIT 10

11 BIT 11

BIT 9

12 BIT 10

NC

13 BIT 9

NC

14 BIT 8

15 BIT 7

16 BIT 6

-16

-14 Most Significant Bit (MSB).

-16

-14

-16

-14

-16

-14

-16

-14

-16

-14

-16

-14

-16

-14

DATA Bits: Three-state outputs. See Table 3 for format of ENABLES and bytes. HIGH = true.

17 BIT 5

18 BIT 4

19 BIT 3

20 BIT 2

21 BIT 1 Least Significant Bit (LSB).

22 LBEN LOW BYTE ENABLE: If not in handshake mode (see pin 27) when LO (with CE/LD, pin 30)

activates low-order byte outputs, BITS 1-8. When in handshake mode (see pin 27), serves as a
low byte flag output. See Figures 11, 12, 13.

23 MBEN -16 MID BYTE ENABLE: Activates Bits 9-16, see LBEN (pin 22)

HBEN -14 HIGH BYTE ENABLE: Activates Bits 9-14, POL, OR, see LBEN (pin 22)

24 HBEN -16 HIGH BYTE ENABLE: Activates POL, OR, see LBEN (pin 22).

CLOCK3 -14 RC oscillator pin: Can be used as clock output.

5-8

ICL8052/ICL7104, ICL8068/ICL7104

Pin Descriptions (Continued)

PIN NO. SYMBOL OPTION DESCRIPTION

25 CLOCK 1 Clock Input: External clock or ocsillator.

26 CLOCK 2 Clock Output: Crystal or RC oscillator.

27 MODE INPUT LO: Direct output mode where CE/LD, HBEN, MBEN and LBEN act as inputs directly

controlling byte outputs. If pulsed HI causes immediate entry into handshake mode (see Figure

13). If HI, enables CE/LD, HBEN, MBEN and LBEN as outputs. Handshake mode will be entered
and data output as in Figures 11 and 12 at conversion completion.

28 R/H RUN/HOLD: Input HI conversions continuously performed every 217(-16) or 215(-14) clock

pulses. Input LO conversion in progress completed, converter will stop in Auto-Zero 7 counts
before input integrate.

29 SEN SEND ENABLE: Input controls timing of byte transmission in handshake mode. HI indicates

‘send’.

30 CE/LD CHIP ENABLE/ LOAD: WITH MODE (PIN 27) LO, CE/LD serves as a master output enable;

when HI, the bit outputs and POL, OR are disabled. With MODE HI, pin serves as a LOAD strobe
(-ve going) used in handshake mode. See Figures 11 and 12.

31 V+ Positive Logic Supply Voltage: Nominally +5V.

32 AN I/P Analog Input: High Side.

33 BUF IN Buffer Input: Buffer Analog to analog chip (ICL8052 or ICL8086).

34 REFCAP2 Reference Capacitor: Negative Side.

35 AN. GND Analog Ground: Input low side and reference low side.

36 A-Z Auto-Zero node.

37 V

38 REFCAP1 Reference Capacitor: Positive side.

39 COMP-IN Comparator Input: From 8052/8068.

40 V- Negative Supply Voltage: Nominally -15V.

REF

Voltage Reference: Input (positive side).

5-9

ICL8052/ICL7104, ICL8068/ICL7104

Absolute Maximum Ratings Thermal Information

ICL8052, ICL8068

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V

Differential Input Voltage

(8068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30V

(8052) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6V

Input Voltage (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V

Output Short Circuit Duration All Outputs (Note 3). . . . . . . Indefinite

ICL7104

V+ Supply (GND to V+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V

V++ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32V

Positive Supply Voltage (GND to V++) . . . . . . . . . . . . . . . . . . . . 17V

Negative Supply Voltage (GND to V-). . . . . . . . . . . . . . . . . . . . .-17V

Analog Input Voltage (Pins 32 - 39)(Note 4). . . . . . . . . . . . V++ to V-

Digital Input Voltage

(Pins 2 - 30) (Note 5) . . . . . . . . . . . . (GND - 0.3V) to (V+ + 0.3V)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

2. For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.

3. Short circuit may be to ground or either supply. Rating applies to 70oC ambient temperature.

4. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.

5. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. For this
reason it is recommended that the power supply to the ICL7104 be established before any inputs from sources not on that supply are
applied.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

14 Ld PDIP Package. . . . . . . . . . . . . . 100 N/A

40 Ld PDIP Package. . . . . . . . . . . . . . 60 N/A

14 Ld CERDIP Package . . . . . . . . . . . 75 20

Maximum Junction Temperature (Ceramic Package). . . . . . . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . .300oC

ICL7104 Electrical Specifications V+ = +5V, V++ = +15V, V- = -15V, T

TEST

PARAMETER SYMBOL

Clock Input, CLK 1 I
Comparator I/P, COMP IN (Note 6) I
Inputs with Pulldown, MODE I

Inputs with Pullups
SEN, R/

H

LBEN, MBEN, HBEN, CE/LD (Note 7)
Input High Voltage, All Digital Inputs V
Input Low Voltage, All Digital Inputs V
Digital Outputs Three-Stated On,

LBEN, MBEN (16 Only), HBEN, CE/LD
BIT n, POL, OR (Note 8)

Digital Outputs Three-Stated Off
Bit n, POL, OR

Non Three-State Digital Output

STTS V

Clock 2 V

Clock 3 (-14 Only) V

IN
IN
IH

I

IL

I

IH

I

IL

IH
IL

V

OL

V

OH

V

OH

I

OL

OL

V

OH

OL

V

OH

OL

V

OH

CONDITIONS MIN TYP MAX UNITS

VIN = +5V to 0V ±2 ±7 ±30 µA
VIN = 0V to +5V -10 ±0.001 10 µA
VIN = +5V 1 5 30 µA
VIN = 0V -10 ±0.01 10 µA
VIN = +5V -10 ±0.01 10 µA
VIN = 0V -30 -5 -1 µA

IOL= 1.6mA - 0.27 0.4 V
IOH= -10µA - 4.5 - V
IOH= -240µA 2.4 3.5 - V
0 ≤ V

≤ V+ -10 ±0.001 +10 µA

OUT

IOL= 3.2mA - 0.3 0.4 V
IOH= -400µA 2.4 3.3 - V
IOL= 320µA - 0.5 - V
IOH = -320µA - 4.5 - V
IOL= 1.6mA - 0.27 0.4 V
IOH= -320µA 2.4 3.5 - V

= 25oC, f

A

= 200kHz

CLOCK

2.5 2.0 - V

- 1.5 1.0 V

5-10

ICL8052/ICL7104, ICL8068/ICL7104

ICL7104 Electrical Specifications V+ = +5V, V++ = +15V, V- = -15V, T

= 25oC, f

A

= 200kHz (Continued)

CLOCK

TEST

PARAMETER SYMBOL

CONDITIONS MIN TYP MAX UNITS

Switch

Switch 1 r
Switches 2, 3 r
Switches 4, 5, 6, 7, 8, 9 r
Switch Leakage I

Clock Frequency (Note 9) f

DS(ON)
DS(ON)
DS(ON)
D(OFF)
CLOCK

- 25k - Ω

- 4k 20k Ω

- 2k 10k Ω

-15- pA

DC 200 400 kHz

Supply Currents

+5V Supply Current

I+ Frequency = 200kHz - 200 600 µA

All outputs high impedance
+5V Supply Current I++ Frequency = 200kHz - 0.3 1.0 mA

-5V Supply Current I- Frequency = 200kHz - 25 200 µA

Supply Voltage Range

Logic Supply V+ Note 10 4 - 11 V
Positive Supply V++ 10 - 16 V
Negative Supply V- -16 - -10 V

NOTES:

6. This specification applies when not in Auto-Zero phase.

7. Apply only when these pins are inputs, i.e., the mode pin is low, and the 7104 is not in handshake mode.

8. Apply only when these pins are outputs, i.e., the mode pin is high, or the 7104 is in handshake mode.

9. Clock circuit shown in Figures 14 and 15.

10. V+ must not be more positive than V++.

ICL8068 Electrical Specifications V

PARAMETER SYMBOL

= ±15V, Unless Otherwise Specified

SUPPLY

TEST

CONDITIONS

ICL8068 ICL8068A

UNITSMIN TYP MAX MIN TYP MAX

EACH OPERATIONAL AMPLIFIER

Input Offset Voltage V
Input Current (Either Input) (Note 11) I

OS
IN

VCM = 0V - 20 65 - 20 65 mV

VCM = 0V - 175 250 - 80 150 pA
Common-Mode Rejection Ratio CMRR VCM = ±10V 70 90 - 70 90 - dB
Non-Linear Component of Common-

VCM = ±2V - 110 - - 110 - dB
Mode Rejection Ratio (Note 12)

Large Signal Voltage Gain A

RL = 50kΩ 20,000 - - 20,000 - - V/V

V

Slew Rate SR - 6 - - 6 - V/µs
Unity Gain Bandwidth GBW - 2 - - 2 - MHz
Output Short-Circuit Current I

SC

-5--5-mA

COMPARATOR AMPLIFIER

Small-Signal Voltage Gain A
Positive Output Voltage Swing +V
Negative Output Voltage Swing -V

VOL

RL= 30kΩ - 4000 - - - - V/V

O

O

12 13 - 12 13 - V

-2.0 -2.6 - -2.0 -2.6 - V

VOLTAGE REFERENCE

Output Voltage V
Output Resistance R

O
O

1.5 1.75 2.0 1.60 1.75 1.90 V

-5--5-Ω

5-11

ICL8052/ICL7104, ICL8068/ICL7104

ICL8068 Electrical Specifications V

PARAMETER SYMBOL

= ±15V, Unless Otherwise Specified (Continued)

SUPPLY

TEST

ICL8068 ICL8068A

CONDITIONS

UNITSMIN TYP MAX MIN TYP MAX

Temperature Coefficient TC - 50 - - 40 - ppm/oC
Supply Voltage Range V
Supply Current Total I

SUPPLY

SUPPLY

ICL8052 Electrical Specifications V

= ±15V, Unless Otherwise Specified

SUPPLY

±10 - ±16 ±10 - ±16 V

- - 14 - 8 14 mA

ICL8052 ICL8052A

TEST

PARAMETER SYMBOL

CONDITIONS

UNITSMIN TYP MAX MIN TYP MAX

EACH OPERATIONAL AMPLIFIER

Input Offset Voltage V
Input Current (Either Input) (Note 11) I

OS

IN

VCM = 0V - 20 75 - 20 75 mV

VCM = 0V - 5 50 - 2 10 pA
Common-Mode Rejection Ratio CMRR VCM = ±10V 70 90 - 70 90 - dB
Non-Linear Component of Common-

VCM = ±2V - 110 - - 110 - dB
Mode Rejection Ratio (Note 12)

Large Signal Voltage Gain A

RL = 50kΩ 20,000 - - 20,000 - - V/V

V

Slew Rate SR - 6 - - 6 - V/µs
Unity Gain Bandwidth GBW - 1 - - 1 - MHz
Output Short-Circuit Current I

SC

-20- -20-mA

COMPARATOR AMPLIFIER

Small-Signal Voltage Gain A
Positive Output Voltage Swing +V
Negative Output Voltage Swing -V

VOL

RL= 30kΩ - 4000 - - - - V/V

O

O

12 13 - 12 13 - V

-2.0 -2.6 - -2.0 -2.6 - V

VOLTAGE REFERENCE

Output Voltage V
Output Resistance R

O

O

1.5 1.75 2.0 1.60 1.75 1.90 V

-5--5-Ω
Temperature Coefficient TC - 50 - - 40 - ppm/oC
Supply Voltage Range V
Supply Current Total I

SUPPLY

SUPPLY

±10 - ±16 ±10 - ±16 V

- 6 12 - 6 12 mA

NOTES:

11. The input bias currents are junction leakage currents which approximately double for every 10oC increase in the junction temperature,
TJ. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation
the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. TJ = TA + R
R

is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.

θJA

θJAPD

where

12. This is the only component that causes error in dual-slope converter.

5-12