®
www.BDTIC.com/Intersil
ICL3225, ICL3245
Data Sheet February 27, 2006
1 Microamp, +3V to +5.5V, 1Mbps, RS-232
Transceivers with Enhanced Automatic
Powerdown
The Intersil ICL32XX devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at V
applications are PDAs, Palmtops, and notebook and laptop
computers where the low operational, and even lower
standby, power consumption is critical. Efficient on-chip
charge pumps, coupled with manual and enhanced
automatic powerdown functions, reduce the standby supply
current to a 1µA trickle. Small footprint packaging, and the
use of small, low value capacitors ensure board space
savings as well. Data rates greater than 1Mbps are
guaranteed at worst case load conditions. This family is fully
compatible with 3.3V only systems, mixed 3.3V and 5.0V
systems, and 5.0V only systems.
The ICL3245 is a 3 driver, 5 receiver device that provides a
complete serial port suitable for laptop or notebook
computers. It also includes a noninverting always-active
receiver for “wake-up” capability.
These devices, feature an enhanced automatic
powerdown function which powers down the on-chip powersupply and driver circuits. This occurs when all receiver and
transmitter inputs detect no signal transitions for a period of
30s. These devices power back up, automatically, whenever
they sense a transition on any transmitter or receiver input.
Table 1 summarizes the features of the device represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XX 3V family.
= 3.0V. Targeted
CC
FN4878.8
Features
• ±15kV ESD Protected (Human Body Model)
• Manual and Enhanced Automatic Powerdown Features
• Drop in Replacements for MAX3225, MAX3245
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Fre e
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Guaranteed Mouse Driveability (ICL3245)
• “Ready to Transmit” Indicator Output (ICL3225)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . . 1Mbps
• Low Skew at Transmitter/Receiver Input Trip Points . . . 10ns
• Guaranteed Minimum Slew Rate. . . . . . . . . . . . . . 24V/µs
• Wide Power Supply Range. . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
Related Literature
• Techni cal Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
TABLE 1. SUMMARY OF FEATURES
NO. OF
PART
NUMBER
ICL3225 2 2 0 1000 No Yes Yes Yes
ICL3245 3 5 1 1000 No No Yes Yes
NO. OF
Tx.
NO. OF
Rx.
1
MONITOR Rx.
)
(R
OUTB
DATA
RATE
(kbps)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
Rx. ENABLE
FUNCTION?
Copyright © Intersil Americas Inc. 2000, 2001, 2003-2006. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
READY
OUTPUT?
MANUAL
POWER-
DOWN?
ENHANCED
AUTOMATIC
POWERDOWN
FUNCTION?
Ordering Information
www.BDTIC.com/Intersil
ICL3225, ICL3245
PART NO.
PART
MARKING
TEMP.
RANGE (°C) PACKAGE PKG. DWG. #
ICL3225CA ICL3225CA 0 to 70 20 Ld SSOP M20.209
ICL3225CA-T ICL3225CA 0 to 70 20 Ld SSOP Tape and Reel M20.209
ICL3225CAZ (Note) ICL3225CAZ 0 to 70 20 Ld SSOP (Pb-free) M20.209
ICL3225CAZ-T (Note) ICL3225CAZ 0 to 70 20 Ld SSOP Tape and Reel (Pb-free) M20.209
ICL3225CP ICL3225CP 0 to 70 20 Ld PDIP E20.3
ICL3225CPZ (Note) ICL3225CPZ 0 to 70 20 Ld PDIP* (Pb-free) E20.3
ICL3225IA ICL3225IA -40 to 85 20 Ld SSOP M20.209
ICL3225IA-T ICL3225IA -40 to 85 20 Ld SSOP Tape and Reel M20.209
ICL3225IAZ (Note) ICL3225IAZ -40 to 85 20 Ld SSOP (Pb-free) M20.209
ICL3225IAZ-T (Note) ICL3225IAZ -40 to 85 20 Ld SSOP Tape and Reel (Pb-free) M20.209
ICL3245CA ICL3245CA 0 to 70 28 Ld SSOP M28.209
ICL3245CA-T ICL3245CA 0 to 70 28 Ld SSOP Tape and Reel M28.209
ICL3245IV ICL3245IV -40 to 85 28 Ld TSSOP M28.173
ICL3245IV-T ICL3245IV -40 to 85 28 Ld TSSOP Tape and Reel M28.173
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
READY
C1+
V+
C1-
C2+
C2-
T2
OUT
R2
R2
OUT
ICL3225 (PDIP, SSOP)
TOP VIEW
1
2
3
4
5
6
V-
7
8
9
IN
10
FORCEOFF
20
V
19
CC
GND
18
T1
17
R1
16
R1
15
FORCEON
14
T1
13
12
T2
INVALID
11
OUT
IN
OUT
IN
IN
ICL3245 (SSOP, TSSOP)
TOP VIEW
C2+
1
C2-
2
3
V-
R1
4
IN
R2
5
IN
R3
6
IN
R4
7
IN
R5
8
IN
T1
9
OUT
10
T2
OUT
T3
11
OUT
T3
12
IN
T2
13
IN
T1
14
IN
28
C1+
V+
27
V
26
CC
GND
25
C1-
24
FORCEON
23
FORCEOFF
22
INVALID
21
20
R2
R1
19
R2
18
R3
17
16
R4
R5
15
OUTB
OUT
OUT
OUT
OUT
OUT
2
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
Pin Descriptions
PIN FUNCTION
V
CC
System power supply input (3.0V to 5.5V).
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
T
T
OUT
R
R
OUT
R
OUTB
INVALID
TTL/CMOS compatible transmitter Inputs.
IN
RS-232 level (nominally ±5.5V) transmitter outputs.
RS-232 compatible receiver inputs.
IN
TTL/CMOS level receiver outputs.
TTL/CMOS level, noninverting, always enabled receiver outputs.
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
READY Active high output that indicates when the ICL32XXE is ready to transmit (i.e., V- ≤ -4V)
FORCEOFF
Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF
must be high).
Typical Operating Circuits
TTL/CMOS
LOGIC LEVELS
+3.3V
0.1µF
0.1µF
R1
R2
C
C
T1
T2
OUT
OUT
ICL3225
+
0.1µF
2
+
4
5
+
6
13
12
15
1
14
C1+
C1-
C2+
C2-
READY
FORCEON
1
2
IN
IN
19
V
CC
T
1
T
2
R
1
R
2
FORCEOFF
GND
18
V+
V-
5kΩ
5kΩ
INVALID
3
C
3
+
0.1µF
7
C
4
0.1µF
+
17
T1
8
T2
16
R1
910
R2
20
V
CC
11
TO POWER
CONTROL LOGIC
OUT
OUT
IN
IN
RS-232
LEVELS
3
FN4878.8
February 27, 2006
Typical Operating Circuits (Continued)
www.BDTIC.com/Intersil
ICL3225, ICL3245
ICL3245
+3.3V
TTL/CMOS
LOGIC LEVELS
CONTROL LOGIC
+
0.1µF
TO POWER
0.1µF
0.1µF
R2
R1
R2
R3
R4
R5
V
28
C
1
C
2
T1
T2
T3
OUTB
OUT
OUT
OUT
OUT
OUT
CC
IN
IN
IN
C1+
+
24
C1-
1
C2+
+
2
C2-
14
13
12 11
20
19
23
FORCEON
22
FORCEOFF
21
INVALID
V
R
1
R
2
R
3
R
4
R
5
GND
CC
26
27
C
3
V+
V-
T
1
T
2
T
3
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
25
+
0.1µF
3
C
4
0.1µF
+
9
T1
OUT
10
T2
T3
4
R1
518
R2
617
R3
716
R4
815
R5
OUT
OUT
IN
IN
IN
IN
IN
RS-232
LEVELS
RS-232
LEVELS
4
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
, FORCEOFF, FORCEON. . . . . . . . . . . . . . . . . . . -0.3V to 6V
T
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
R
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
T
OUT
, INVALID, READY. . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
R
OUT
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Thermal Resistance (Typical, Note 1)
20 Ld PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . 80
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 135
28 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 100
28 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 125
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SSOP, TSSOP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
θ
JA
(°C/W)
Operating Conditions
Temperature Range
ICL32XXC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
Supply Current, Powerdown FORCEOFF
Supply Current,
Automatic Powerdown Disabled
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low T
Input Logic Threshold High T
Transmitter Input Hysteresis 25 - 0.5 - V
Input Leakage Current T
Output Leakage Current FORCEOFF
Output Voltage Low I
Output Voltage High I
RECEIVER INPUTS
Input Voltage Range Full -25 - 25 V
Input Threshold Low V
Input Threshold High V
Input Hysteresis 25 - 0.5 - V
Input Resistance 25 3 5 7 kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Output Resistance V
Output Short-Circuit Current Full - ±35 ±60 mA
Open, FORCEON = GND, FORCEOFF = V
All R
IN
All Outputs Unloaded,
FORCEON = FORCEOFF
, FORCEON, FORCEOFF Full - - 0.8 V
IN
, FORCEON, FORCEOFF VCC = 3.3V Full 2.0 - - V
IN
, FORCEON, FORCEOFF Full - ±0.01 ±1.0 µA
IN
= 1.6mA Full - - 0.4 V
OUT
= -1.0mA Full V
OUT
= 3.3V 25 0.6 1.2 - V
CC
= 5.0V 25 0.8 1.5 - V
V
CC
= 3.3V 25 - 1.5 2.4 V
CC
= 5.0V 25 - 1.8 2.4 V
V
CC
= V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
CC
= 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
CC
= 25°C
A
TEMP
(°C) MIN TYP MAX UNITS
CC
= GND 25 - 1.0 10 µA
ICL3245, VCC = 3.0V 25 - 0.3 1.0 mA
= V
CC
ICL322X, V
= 5.0V Full 2.4 - - V
V
CC
= GND Full - ±0.05 ±10 µA
= 3.15V 25 - 0.3 1.0 mA
CC
25 - 1.0 10 µA
CC
-0.6 V
-0.1 - V
CC
5
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
Output Leakage Current V
MOUSE DRIVEABILITY
Transmitter Output Voltage
(See Figure 11)
ENHANCED AUTOMATIC POWERDOWN (FORCEON = GND, FORCEOFF
Receiver Input Thresholds to
INVALID
Receiver Input Thresholds to
INVALID
INVALID
Low
INVALID
High
Receiver Positive or Negative
Threshold to INVALID
(t
Receiver Positive or Negative
Threshold to INVALID
(t
Receiver or Transmitter Edge to
Transmitters Enabled Delay (t
Receiver or Transmitter Edge to
Transmitters Disabled Delay
(t
TIMING CHARACTERISTICS
Maximum Data Rate R
Receiver Propagation Delay Receiv e r I n put to Rec e i ver Out pu t ,
Receiver Output Enable Time Normal Operation 25 - 200 - ns
Receiver Output Disable Time Normal Operation 25 - 200 - ns
Transmitter Skew t
Receiver Skew t
Transition Region Slew Rate V
ESD PERFORMANCE
RS-232 Pins (T
All Other Pins Human Body Model 25 - ±2.5 - kV
NOTES:
High
Low
, READY Output Voltage
, READY Output Voltage
High Delay
)
INVH
Low Delay
)
INVL
)
WU
AUTOPWDN
2. An “edge” is defined as a transition through the transmitter or receiver input thresholds.
3. Skews are measured at the receiver input switching points (1.4V).
)
, RIN) Human Body Model 25 - ±15 - kV
OUT
= ±12V, VCC = 0V or 3V to 5.5V
OUT
Automatic Powerdown or FORCEOFF
T1
= T2IN = GND, T3IN = VCC, T3
IN
and T2
T1
OUT
See Figure 6 Full -2.7 - 2.7 V
See Figure 6 Full -0.3 - 0.3 V
I
= 1.6mA Full - - 0.4 V
OUT
I
= -1.0mA Full VCC-0.6 - - V
OUT
Note 2 25 - 100 - µs
Note 2 Full 15 30 60 sec
= 3kΩ, One Transmitter
L
Switching
C
= 150pF
L
- t
PHL
PLH
- t
PHL
PLH
= 3.3V, RL = 3kΩ to 7kΩ, Measured from 3V to -3V or -3V to
CC
= 150pF to 1000pF
3V, C
L
IEC61000-4-2 Contact Discharge 25 - ±8-kV
IEC61000-4-2 Air Gap Discharge 25 - >±8-kV
= 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
CC
= 25°C (Continued)
A
TEMP
(°C) MIN TYP MAX UNITS
Full - - ±25 µA
= GND
Loaded with 3kΩ to GND,
Loaded with 2.5mA Each
OUT
(Note 3) 25 - 25 - ns
(Note 3) 25 - 50 - ns
OUT
= VCC)
CL = 1000pF Full 250 - - kbps
= 3V to 4.5V, CL = 250pF Full 1000 - - kbps
V
CC
= 4.5V to 5.5V,
V
CC
= 1000pF
C
L
t
PHL
t
PLH
Full ±5--V
25 - 1 - µs
25 - 30 - µs
Full 1000 - - kbps
25 - 0.15 - µs
25 - 0.15 - µs
25 24 - 150 V/µs
6
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
Detailed Description
These ICL32XX interface ICs operate from a single +3V to
+5.5V supply, guarantee a 1Mbps minimum data rate,
require only four small external 0.1µF capacitors, f eat ure lo w
power consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
Charge-Pump
Intersil’s new ICL32XX family utiliz es regu l a te d on -ch i p d ua l
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a V
low as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inver ter functions at V
the “Capacitor Selection” section, and Table 3 for capacitor
recommendations for other operating conditions. The cha rge
pumps operate discontinuously (i.e., they turn off as soon as
the V+ and V- supplies are pumped up to the nominal
values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies, these
transmitters deliver true RS-232 levels over a wide range of
single supply system voltages.
Transmitter outputs disable and assume a high impedance
state when the device enters the powerdown mode (see
Table 2). These outputs may be driven to ±12V when
disabled.
supply as
CC
= 3.3V. See
CC
Schmitt trigger input stage uses hysteresis to increase noise
immunity and decrease errors due to slow input signal
transitions.
The ICL3245 inverting receivers disable during forced
(manual) powerdown, but not during automatic powerdown
(see Table 2). Conversely, the monitor receiver remains
active even during manual powerdown making it extremely
useful for Ring Indicator monitoring. Standard receivers
driving powered down peripherals must be disabled to
prevent current flow through the peripheral’s protection
diodes (see Figures 2 and 3). This renders them useless for
wake up functions, but the corresponding monitor receiver
can be dedicated to this task as shown in Figure 3.
V
CC
R
XIN
V
CC
V
OUT = VCC
SHDN
5kΩ
= GND
-25V ≤ V
FIGURE 1. INVERTING RECEIVER CONNECTIONS
POWERED
DOWN
UART
GND
≤ +25V
RIN
GND
V
CC
Rx
Tx
R
XOUT
GND ≤ V
V
CC
CURRENT
FLOW
OLD
RS-232 CHIP
ROUT
≤ V
CC
All devices guarantee a 1Mbps data rate for full load
conditions (3kΩ and 250pF), V
≥ 3.0V, with one
CC
transmitter operating at full speed. Under more typical
conditions of V
≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
CC
transmitter easily operates at 1.4Mbps. Transmitter skew is
extremely low on these devices, and is specified at the
receiver input trip points (1.4V), rather than the arbitrary 0V
crossing point typical of other RS-232 families.
Transmitter inputs float if left unconnected, and may cause
I
increases. Connect unused inputs to GND for the best
CC
performance.
Receivers
All the ICL32XX devices contain standard inverting
receivers, but only the ICL3245 receivers can three-state, via
the FORCEOFF
includes a noninverting (monitor) receiver (denoted by the
R
label) that is always active, regardless of the state of
OUTB
any control lines. Both receiver types convert RS-232 signals
to CMOS output levels and accept inputs up to ±25V while
presenting the required 3kΩ to 7kΩ input impedance (see
Figure 1) even if the power is off (V
control line. Additionally, the ICL3245
= 0V). The receivers’
CC
7
FIGURE 2. POWER DRAIN THROUGH PO WERED DO WN
PERIPHERAL
V
CC
TRANSITION
DETECTOR
TO
WAKE-UP
LOGIC
V
CC
R
X
POWERED
DOWN
UART
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
T
X
FORCEOFF = GND
V
OUT =
R2
OUTB
R2
HI-Z
OUT
T1
IN
ICL3245
R2
IN
T1
OUT
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
TABLE 2. POWERDOWN LOGIC TRUTH TABLE
RS-232
RCVR OR
XMTR
EDGE
WITHIN
30s?
ICL3225
NO H H Active Active N.A. No L Normal Operation (Enhanced
NO H H Active Active N.A. Yes H
YES H L Active Active N.A. No L Normal Operation (Enhanced
YES H L Active Active N.A. Yes H
NO H L High-Z Active N.A. No L Powerdown Due to Enhanced
NO H L High-Z Active N.A. Yes H
X L X High-Z Active N.A. No L Manual Powerdown
X L X High-Z Active N.A. Yes H
ICL322X - INVALID
X NOTE 5 NOTE 5 Active Active N.A. Yes H Normal Operation
X NOTE 5 NOTE 5 High-Z Active N.A. No L Forced Auto Powerdown
ICL3245
NO H H Active Active Active No L Normal Operation (Enhanced
NO H H Active Active Active Yes H
YES H L Active Active Active No L Normal Operation (Enhanced
YES H L Active Active Active Yes H
NO H L High-Z Active Active No L Powerdown Due to Enhanced
NO H L High-Z Active Active Yes H
X L X High-Z High-Z Active No L Manual Powerdown
X L X High-Z High-Z Active Yes H
ICL3245 - INVALID
X NOTE 5 NOTE 5 Active Active Active Yes H Normal Operation
X NOTE 5 NOTE 5 High-Z High-Z Active No L Forced Auto Powerdown
NOTES:
4. Applies only to the ICL3245.
5. Input is connected to INVALID
FORCEOFF
INPUT
DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
FORCEON
INPUT
Output.
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
(NOTE 4)
R
OUTB
OUTPUTS
LEVEL
PRESENT
AT
RECEIVER
INPUT?
INVALID
OUTPUT MODE OF OPERATION
Auto Powerdown Disabled)
Auto Powerdown Enabled)
Auto Powerdown Logic
Auto Powerdown Disabled)
Auto Powerdown Enabled)
Auto Powerdown Logic
Po werdown Functionality
This 3V family of RS-232 interface devices requires a
nominal supply current of 0.3mA during normal operation
(not in powerdown mode). This is considerably less than the
5mA to 11mA current required of 5V RS-232 devices. The
already low current requirement drops significantly when the
device enters powerdown mode. In powerdown, supply
current drops to 1µA, because the on-chip charge pump
turns off (V+ collapses to V
the transmitter outputs three-state. Inverting receiver outputs
may or may not disable in powerdown; refer to Table 2 for
details. This micro-power mode makes these devices ideal
for battery powered and portable applications.
Software Controlled (Manual) Powerdown
These three devices allow the user to force the IC into the
, V- collapses to GND), and
CC
where the FORCEON and FORCEOFF
IC’s mode. For always enabled operation, FORCEON and
FORCEOFF
are both strapped high. To switch between
active and powerdown modes, under logic or software
control, only the FORCEOFF
FORCEON state isn’t critical, as FORCEOFF
over FORCEON. Nev ertheless, if strictly manual control over
powerdown is desired, the user must strap FORCEON high
to disable the enhanced automatic powerdown circuitry.
ICL3245 inverting (standard) receiver outputs also disable
when the device is in powerdown, thereby eliminating the
possible current path through a shutdown peripheral’s input
protection diode (see Figures 2 and 3).
Connecting FORCEOFF
the enhanced automatic powerdown feature, enabling them
to function as a manual SHUTDOWN
low power, standby state, and utilize a two pin approach
8
inputs determine the
input need be driven. The
dominates
and FORCEON together disables
input (see Figure 4).
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
FORCEOFF
PWR
MGT
LOGIC
CPU
FIGURE 4. CONNECTIONS FOR MANUAL PO WERDO WN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
FORCEON
INVALID
ICL32XX
I/O
UART
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100µs.
When using both manual and enhanced automatic powerdown
(FORCEON = 0), the ICL32XX won’t power up from manual
powerdown until both FORCEOFF
and FORCEON are driven
high, or until a transition occurs on a receiver or transmitter
input. Figure 5 illustrates a circuit for ensuring that the ICL32XX
powers up as soon as FORCEOFF
switches high. The rising
edge of the Master Powe rdown signal forces the device to
power up, and the ICL32XX returns to enhanced automatic
powerdown mode an RC time constant after this rising edge.
The time constant isn’t critical, because the ICL32XX remains
powered up for 30 seconds after the FORCEON falling edge,
even if there are no signal transitions. This gives slow-to-w ak e
systems (e.g., a mouse) plenty of time to start transmitting, and
as long as it starts transmitting within 30 seconds both systems
remain enabled.
POWER
MANAGEMENT
UNIT
FIGURE 5. CIRCUIT TO ENSURE IMMEDIA TE PO WER UP
WHEN EXITING FORCED POWERDOWN
MASTER POWERDOWN LINE
0.1µF
FORCEOFF FORCEON
ICL32XX
1MΩ
INVALID Output
The INVALID output alwa ys indicates (see Table 2) whether or
not 30µs have elapsed with inv alid RS-232 signals (see Figures
6 and 8) persisting on all of the receiver inputs, giving the user
an easy way to determine when the interface block should
power down. Inv alid receiv er le v els occur whene ver the driving
peripheral’s outputs are shut off (powered down) or when the
RS-232 interface cable is disconnected. In the case of a
disconnected interface cable where all the receiver inputs are
floating (but pulled to GND by the internal receiver pull down
resistors), the INV ALID
logic detects the invalid lev els and
drives the output low. The pow er management logic then uses
this indicator to power down the interface b loc k. Reconnecting
the cable restores valid lev els at the receiv er inputs, INVALID
switches high, and the power management logic wakes up the
interface block. INVALID
can also be used to indicate the DTR
or RING INDICATOR signal, as long as the other receiver
inputs are floating, or driv en to GND ( as in the case of a
powered down driver).
2.7V
0.3V
-0.3V
-2.7V
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
VALID RS-232 LEVEL - INVALID
INDETERMINATE
INVALID LEVEL - INVALID
INDETERMINATE
VALID RS-232 LEVEL - INVALID
= 0
= 1
= 1
Enhanced Automatic Powerdown
Even greater power savings is available by using these
devices which feature an enhanced automatic powerdown
function. When the enhanced powerdown logic determines
that no transitions have occurred on any of the transmitter
nor receiver inputs for 30 seconds, the charge pump and
transmitters powerdown, thereby reducing supply current to
1µA. The ICL32XX automatically powers back up whenever
it detects a transition on one of these inputs. This automatic
powerdown feature provides additional system po wer
savings without changes to the existing operating system.
Enhanced automatic powerdown operates when the
FORCEON input is low, and the FORCEOFF
Tying FORCEON high disables automatic powerdown, but
manual powerdown is always available via the overriding
FORCEOFF
input. Table 2 summarizes the enhanced
automatic powerdown functionality.
FORCEOFF
T_IN
R_IN
FIGURE 7. ENHANCED AUTOMATIC POWERDOWN LOGIC
EDGE
DETECT
EDGE
DETECT
FORCEON
S
30s
TIMER
R
input is high.
AUTOSHDN
9
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
RECEIVER
INPUTS
TRANSMITTER
INPUTS
TRANSMITTER
OUTPUTS
INVALID
OUTPUT
READY
OUTPUT
V+
V
CC
t
INVL
0
V-
FIGURE 8. ENHANCED AUTOMATIC POWERDOWN, INVALID AND READY TIMING DIAGRAMS
t
INVH
t
AUTOPWDN
Figure 7 illustrates the enhanced powerdown control logic.
Note that once the ICL32XX enters powerdown (manually or
automatically), the 30 second timer remains timed out (set),
keeping the ICL32XX powered down until FORCEON
transitions high, or until a transition occurs on a receiver or
transmitter input.
INVALID
}
REGION
t
t
WU
AUTOPWDN
t
WU
another computer via a detachable cable. Detaching the
cable allows the internal receiver pull-down resistors to pull
the inputs to GND (an invalid RS-232 level), causing the
30µs timer to time-out and drive the IC into powerdown.
Reconnecting the cable
restores valid levels, causing the IC
to power back up.
The INVALID
output signal switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30µs (see Figure 8), but this has no direct effect
on the state of the ICL32XX (see the next sections for
methods of utilizing INVALID
INVALID
switches high 1µs after detecting a valid RS-232
level on a receiver input. INVALID
to power down the device).
operates in all modes
(forced or automatic powerdown, or forced on), so it is also
useful for systems employing manual powerdown circuitry.
The time to recover from automatic powerdown mode is
typically 100µs.
Emulating Standard Automatic Powerdown
If enhanced automatic powerdown isn’t desired, the user can
implement the standard automatic powerdown feature
(mimics the function on the ICL3221/ICL3223/ICL3243) by
connecting the INVALID
FORCEOFF
inputs, as shown in Figure 9. After 30µs of
invalid receiver levels, INVALID
ICL32XX into a forced powerdown condition. INVALID
switches high as soon as a receiver input senses a valid RS232 level, forcing the ICL32XX to power on. See the
“INVALID
DRIVING FORCEON AND FORCEOFF” section
of Table 2 for an operational summary. This operational
mode is perfect for handheld devices that communicate with
output to the FORCEON and
switches low and drives the
INVALID
ICL32XX
I/O
CPU
FIGURE 9. CONNECTIONS FOR AUT OMA TIC PO WERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
UART
FORCEOFF
FORCEON
Hybrid Automatic Powerdown Options
For devices which communicate only through a detachable
cable, connecting INVA LID
= 0) may be a desirable configuration. While the cable is
attached INVALID
and FORCEOFF remain high, so the
enhanced automatic powerdown logic powers down the RS232 device whenever there is 30 seconds of inactivity on the
to FORCEOFF (with FORCEON
10
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
receiver and transmitter inputs. Detaching the cable allows
the receiver inputs to drop to an invalid level (GND), so
INVALID
switches low and forces the RS-232 device to
power down. The ICL32XX remains powered down until the
cable is reconnected (INV ALID
= FORCEOFF = 1) and a
transition occurs on a receiver or transmitter input (see
Figure 7). For immediate power up when the cable is
reattached, connect FORCEON to FORCEOFF
through a
network similar to that shown in Figure 5.
Ready Output (ICL3225 Only)
The Ready output indicates that the ICL322X is ready to
transmit. Ready switches low whenever the device enters
powerdown, and switches back high during power-up when
V- reaches -4V or lower.
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and sligh tly
reduces power consumption. C
increased without increasing C
increase C
without also increasing C2, C3, and C4 to
1
maintain the proper ratios (C
, C3, and C4 can be
2
’s value, however, do not
1
to the other capacitors).
1
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
TABLE 3. REQUIRED CAPACITOR VALUES
V
(V) C1 (µF) C2, C3, C4 (µF)
CC
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 0.47
Po wer Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple V
capacitor of the same value as the charge-p ump capacitor C
to ground with a
CC
1
Connect the bypass capacitor as close as possible to the IC.
Operation Down to 2.7V
ICL32XXE transmitter outputs meet RS-562 levels (±3.7V),
at full data rate, with V
typically ensure inter operability with RS-232 devices.
as low as 2.7V. RS-562 levels
CC
Transmitter Outputs when Exiting
Powerdown
Figure 10 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
5V/DIV.
2V/DIV
5V/DIV.
FIGURE 10. TRANSMITTER OUTPUTS WHEN EXITING
FORCEOFF
T1
VCC = +3.3V
C1 - C4 = 0.1µF
T2
READY
TIME (20µs/DIV.)
POWERDOWN
Mouse Driveability
The ICL3245 is specifically designed to power a serial mouse
while operating from low voltage supplies. Figure 11 shows the
transmitter output voltages under increasing load current. The
on-chip switching regulator ensures the transmitters will supply
at least
±5V during worst case conditions (15mA for paralleled
V+ transmitters, 7.3mA for single V- transmitter).
6
5
4
3
2
1
0
-1
-2
.
-3
-4
-5
TRANSMITTER OUTPUT VOLTAGE (V)
-6
0246810
FIGURE 11. TRANSMITTER OUTPUT VOLTAGE vs LO AD
V
= 3.0V
CC
T1
V
+
OUT
T2
V
T3
CC
13579
LOAD CURRENT PER TRANSMITTER (mA)
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL V
ICL3245
-
V
OUT
V
OUT+
V
OUT
OUT
+
-
CURRENT)
11
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
High Data Rates
The ICL32XX maintain the RS-232 ±5V minimum transmitter
output voltages even at high data rates. Figure 12 details a
transmitter loopback test circuit, and Figure 13 illustrates the
loopback test result at 250kbps. For this test, all transmitters
were simultaneously driving RS-232 loads in parallel with
1000pF, at 250kbps. Figure 14 shows the loopback results
for a single transmitter driving 250pF and an RS-232 load at
1Mbps. The static transmitters were also loaded with an
RS-232 receiver.
V
CC
0.1µF
+
C
1
+
C
2
V
CC
FIGURE 12. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV.
T1
IN
T1
OUT
+
C1+
C1-
C2+
C2-
T
IN
R
OUT
FORCEON
FORCEOFF
V
CC
ICL32XX
T
OUT
V+
V-
R
IN
5K
+
C
3
C
4
+
C
L
5V/DIV.
T1
IN
T1
OUT
R1
OUT
VCC = +3.3V
C1 - C4 = 0.1µF
0.5µs/DIV.
FIGURE 14. LOOPBACK TEST AT 1Mbps (CL = 250pF)
Interconnection with 3V and 5V Logic
The ICL32XXE directly interfaces with 5V CMOS and TTL
logic families. Nevertheless, with the ICL32XX at 3.3V, and
the logic supply at 5V, AC, HC, and CD4000 outputs can
drive ICL32XX inputs, but ICL32XX outputs do not reach the
minimum V
information.
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SYSTEM
POWER-SUPPLY
VOLTAGE
for these logic families. See Table 4 for more
IH
SUPPLY VOLTAGES
V
CC
SUPPLY
VOLTAGE
(V)
(V) COMPATIBILITY
3.3 3.3 Compatible with all CMOS
families.
5 5 Compatible with all TTL and
CMOS logic families.
5 3.3 Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
R1
OUT
VCC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV.
FIGURE 13. LOOPBACK TEST AT 250kbps (C
= 1000pF)
L
12
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
Typical Performance Curves V
6
4
2
1 TRANSMITTER AT 1Mbps
OTHER TRANSMITTERS AT 30kbps
0
-2
-4
TRANSMITTER OUTPUT VOLTAGE (V)
-6
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
= 3.3V, TA = 25°C
CC
V
+
OUT
V
-
OUT
FIGURE 15. TRANSMITTER OUTPUT VOLTA GE vs LO AD
CAPACITANCE
90
ICL3225
80
70
1Mbps
110
90
+SLEW
70
50
-SLEW
SLEW RATE (V/µs)
30
10
0
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
FIGURE 16. SLEW RATE vs LOAD CAPACITANCE
90
ICL3245
80
70
1Mbps
60
50
40
30
SUPPLY CURRENT (mA)
20
10
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
250kbps
120kbps
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
60
50
3000
250kbps
120kbps
4000
40
30
SUPPLY CURRENT (mA)
20
10
0
1000
2000
LOAD CAPACITANCE (pF)
FIGURE 18. SUPPLY CURRENT vs LOAD CAPACIT ANCE
WHEN TRANSMITTING DATA
5000
13
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
Typical Performance Curves V
3.5
3.0
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 19. SUPPLY CURRENT vs SUPPLY VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP)
GND
= 3.3V, TA = 25°C (Continued)
CC
SUPPLY VOLTAGE (V)
NO LOAD
ALL OUTPUTS STATIC
TRANSISTOR COUNT
ICL3225: 937
ICL3245: 1109
PROCESS
Si Gate CMOS
14
FN4878.8
February 27, 2006
Dual-In-Line Plastic Packages (PDIP)
www.BDTIC.com/Intersil
ICL3225, ICL3245
N
D1
-C-
E1
-B-
A1
A2
E
A
L
e
C
C
L
e
A
C
e
B
INDEX
AREA
BASE
PLANE
SEATING
PLANE
D1
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendicular to datum .
7. e
strained. e
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
12 3 N/2
-A-
B1
B
e
A
and eC are measured at the lead tips with the leads uncon-
B
D
e
0.010 (0.25) C AM BS
-C-
must be zero or greater.
C
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 B1 0.045 0.070 1.55 1.77 8
C 0.008 0.014 0.204 0.355 D 0.980 1.060 24.89 26.9 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC e
A
e
B
L 0.115 0.150 2.93 3.81 4
N20 209
0.300 BSC 7.62 BSC 6
- 0.430 - 10.92 7
NOTESMIN MAX MIN MAX
Rev. 0 12/93
15
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
Shrink Small Outline Plastic Packages (SSOP)
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) B
H
α
e
B
0.25(0.010) C AMB
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
M
A1
0.10(0.004)
S
GAUGE
PLANE
M
0.25
0.010
A2
M
L
M20.209 (JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.068 0.078 1.73 1.99
A1 0.002 0.008’ 0.05 0.21
A2 0.066 0.070’ 1.68 1.78
B 0.010’ 0.015 0.25 0.38 9
C 0.004 0.008 0.09 0.20’
D 0.278 0.289 7.07 7.33 3
E 0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
C
H 0.301 0.311 7.65 7.90’
L 0.025 0.037 0.63 0.95 6
N20 207
α
0 deg. 8 deg. 0 deg. 8 deg.
NOTESMIN MAX MIN MAX
Rev. 3 11/02
16
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX
AREA
123
0.05(0.002)
-AD
e
b
0.10(0.004) C AM BS
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
E1
-B-
SEATING PLANE
A
-C-
M
0.25(0.010) BM M
E
α
A1
0.10(0.004)
GAUGE
PLANE
0.25
0.010
A2
L
c
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.047 - 1.20 A1 0.002 0.006 0.05 0.15 A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.378 0.386 9.60 9.80 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N28 287
o
α
0
o
8
o
0
o
8
Rev. 0 6/98
NOTESMIN MAX MIN MAX
-
17
FN4878.8
February 27, 2006
ICL3225, ICL3245
www.BDTIC.com/Intersil
Shrink Small Outline Plastic Packages (SSOP)
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
GAUGE
PLANE
0.25
0.010
L
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M
A1
0.10(0.004)
A2
C
M28.209 (JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.390 0.413 9.90 10.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N28 287
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 2 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN4878.8
February 27, 2006
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