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ICL3224E
DATA SHEET
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intersil ICL3224E, ICL3226E, ICL3244E DATA SHEET

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ICL3224E, ICL3226E, ICL3244E
Data Sheet February 27, 2006
+/-15kV ESD Protected, +3V to +5.5V, 1Microamp, 250kbps, RS-232 Transceivers with Enhanced Automatic Powerdown
The ICL3244E is a 3 driver, 5 receiver de vice that provides a complete serial port suitable for laptop or notebook computers. It also includes a noninverting always-active receiver for “wake-up” capability.
These devices, feature an enhanced automatic powerdown function which powers down the on-chip power­supply and driver circuits. This occurs when all receiver and transmitter inputs detect no signal transitions for a period of 30 seconds. These devices power back up, automatically, whenever they sense a transition on any transmitter or receiver input.
Table 1 summarizes the features of the devices represented by this data sheet, while Application Note AN9863 summarizes the features of each device comprising the ICL32XXE 3V family.
±15kV ESD protection (IEC61000-4-2 Air Gap
= 3.0V. Additionally,
CC
FN4899.6
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
• ESD Protection for RS-232 I/O Pins to
• Manual and Enhanced Automatic Powerdown Features
• Drop in Replacements for MAX3224E, MAX3226E, MAX3244E
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• RS-232 Compatible with VCC = 2.7V
• Latch-Up Fre e
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Guaranteed Mouse Driveability (ICL3244E)
• “Ready to Transmit” Indicator Output (ICL3224E/26E)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Guaranteed Minimum Slew Rate. . . . . . . . . . . . . . . 6V/µs
• Wide Power Supply Range. . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
±15kV (IEC61000)
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
Related Literature
• Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER
ICL3224E 2 2 0 250 No Yes Yes Yes ICL3226E 1 1 0 250 No Yes Yes Yes ICL3244E 3 5 1 250 No No Yes Yes
NO. OF
Tx.
NO. OF
Rx.
1
NO. OF
MONITOR Rx.
)
(R
OUTB
DATA RATE
(kbps)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774
Rx. ENABLE FUNCTION?
Copyright Intersil Americas Inc. 2000, 2001, 2003-2006. All Rights Reserved.
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
READY
OUTPUT?
MANUAL
POWER-
DOWN?
ENHANCED
AUTOMATIC
POWERDOWN
FUNCTION?
ICL3224E, ICL3226E, ICL3244E
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Ordering Information
PART NO. PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
ICL3224ECAZ (Note) 3224ECAZ 0 to 70 20 Ld SSOP (Pb-free) M20.209 ICL3224ECAZ-T (Note) 3224ECAZ 0 to 70 20 Ld SSOP Tape and Reel (Pb-free) M20.209 ICL3224EIA ICL3224EIA -40 to 85 20 Ld SSOP M20.209 ICL3224EIA-T ICL3224EIA -40 to 85 20 Ld SSOP Tape and Reel M20.209 ICL3224EIAZ (Note) 3224EIAZ -40 to 85 20 Ld SSOP (Pb-free) M20.209 ICL3224EIAZ-T (Note) 3224EIAZ -40 to 85 20 Ld SSOP Tape and Reel (Pb-free) M20.209 ICL3226ECA ICL3226ECA 0 to 70 16 Ld SSOP M16.209 ICL3226ECA-T ICL3226ECA 0 to 70 16 Ld SSOP Tape and Reel M16.209 ICL3226ECAZ (Note) 3226ECAZ 0 to 70 16 Ld SSOP (Pb-free) M16.209 ICL3226ECAZ-T 3226ECAZ 0 to 70 16 Ld SSOP Tape and Reel (Pb-free) M16.209 ICL3226EIA ICL3226EIA -40 to 85 16 Ld SSOP M16.209 ICL3226EIA-T ICL3226EIA -40 to 85 16 Ld SSOP Tape and Reel M16.209 ICL3226EIAZ 3226EIAZ -40 to 85 16 Ld SSOP (Pb-free) M16.209 ICL3226EIAZ-T 3226EIAZ -40 to 85 16 Ld SSOP Tape and Reel (Pb-free) M16.209 ICL3244ECA ICL3244ECA 0 to 70 28 Ld SSOP M28.209 ICL3244ECA-T ICL3244ECA 0 to 70 28 Ld SSOP Tape and Reel M28.209 ICL3244ECAZ (Note) ICL3244ECAZ 0 to 70 28 Ld SSOP (Pb-free) M28.209 ICL3244ECAZ-T (Note) ICL3244ECAZ 0 to 70 28 Ld SSOP Tape and Reel (Pb-free) M28.209 ICL3244EIA ICL3244EIA -40 to 85 28 Ld SSOP M28.209 ICL3244EIA-T ICL3244EIA -40 to 85 28 Ld SSOP Tape and Reel M28.209 ICL3244EIAZ (Note) ICL3244EIAZ -40 to 85 28 Ld SSOP (Pb-free) M28.209 ICL3244EIAZ-T (Note) ICL3244EIAZ -40 to 85 28 Ld SSOP Tape and Reel (Pb-free) M28.209 ICL3244EIB ICL3244EIB -40 to 85 28 Ld SOIC M28.3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
ICL3224E (SSOP)
TOP VIEW
FORCEOFF
READY
C1+
V+ C1-
C2+
C2-
T2
OUT
R2
R2
OUT
1 2 3 4 5 6
V-
7 8 9
IN
10
20
V
19
GND
18 17
T1 R1
16
R1
15
FORCEON
14
T1
13 12
T2 INVALID
11
READY
CC
OUT
IN OUT
IN IN
2
R1
ICL3226E (SSOP)
1
C1+
2 3
V+ C1-
4
C2+
5
C2-
6
V-
7 8
IN
TOP VIEW
16
FORCEOFF V
15
CC
GND
14 13
T1 FORCEON
12
T1
11
INVALID
10
R1
9
OUT
IN
OUT
Pinouts (Continued)
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Pin Descriptions
ICL3224E, ICL3226E, ICL3244E
ICL3244E (SOIC, SSOP)
TOP VIEW
C1+
28
V+
27
V
26
CC
GND
25
C1-
24
FORCEON
23
FORCEOFF
22
INVALID
21 20
R2 R1
19
R2
18
R3
17 16
R4 R5
15
OUTB OUT OUT OUT OUT OUT
T1 T2 T3
C2+
R1 R2 R3 R4 R5
OUT OUT OUT
T3 T2 T1
C2-
V-
1 2 3 4
IN
5
IN
6
IN
7
IN
8
IN
9 10 11 12
IN
13
IN
14
IN
PIN FUNCTION
V
CC
System power supply input (3.0V to 5.5V).
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
TTL/CMOS compatible transmitter Input s.
±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs. ±15kV ESD Protected, RS-232 compatible receiver inputs.
TTL/CMOS level receiver outputs. TTL/CMOS level, noninverting, always enabled receiver outputs.
T
R
R
T
IN
OUT
R
IN
OUT
OUTB
INVALID Active low output that indicates if no valid RS-232 levels are present on any receiver input.
READY Active high output that indicates when the ICL32XXE is ready to transmit (i.e., V- ≤ -4V)
FORCEOFF
Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
3
Typical Operating Circuits
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TTL/CMOS
LOGIC LEVELS
ICL3224E, ICL3226E, ICL3244E
ICL3224E
+3.3V
C
0.1µF C
0.1µF
T1
T2
R1
R2
1
2
OUT
OUT
+
0.1µF
2
C1+
+
4
C1-
5
C2+
+
6
C2-
13
IN
12
IN
15
1
READY
14
FORCEON
19
V
CC
T
1
T
2
R
1
R
2
FORCEOFF
GND
18
5kΩ
5kΩ
INVALID
V+
V-
3
7
17
8
16
910
20
11
C
3
+
0.1µF
C
4
0.1µF
+
T1
OUT
T2
OUT
RS-232
CC
LEVELS
IN
IN
R1
R2
V
TO POWER CONTROL LOGIC
+3.3V
TTL/CMOS
LOGIC LEVELS
+
0.1µF
0.1µF
0.1µF
R1
T1
OUT
ICL3226E
2
C
C
C1+
1
+
4
C1-
5
2
C2+
+
6
C2-
11
IN
1
READY
12
FORCEON
15
V
CC
T
1
R
1
FORCEOFF
GND
14
V+
V-
5kΩ
INVALID
3
C
+
0.1µF
7
C
0.1µF
+
13
T1
89
R1
16
V
10
TO POWER CONTROL LOGIC
3
4
CC
OUT
IN
RS-232 LEVELS
4
ICL3224E, ICL3226E, ICL3244E
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Typical Operating Circuits (Continued)
+3.3V
C
0.1µF C
0.1µF
T1
T2
T3
R2
OUTB
TTL/CMOS
LOGIC LEVELS
R1
R2
R3
R4
R5
OUT
OUT
OUT
OUT
OUT
ICL3244E
+
0.1µF
28
1
2
C1+
+
24
C1-
1
C2+
+
2
C2-
14
IN
13
IN
12 11
IN
20
19
23
FORCEON
26
V
CC
T
1
T
2
T
3
R
1
R
2
R
3
R
4
R
5
V+
V-
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
27
C
3
+
0.1µF
3
C
4
0.1µF
+
9
T1
OUT
10
T2
T3
4
R1
518
R2
617
R3
716
R4
815
R5
OUT
OUT
IN
IN
IN
IN
IN
RS-232 LEVELS
RS-232 LEVELS
V
CC
TO POWER
CONTROL LOGIC
22
FORCEOFF
21
INVALID
GND
25
5
ICL3224E, ICL3226E, ICL3244E
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m
Absolute Maximum Ratings Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
, FORCEOFF, FORCEON. . . . . . . . . . . . . . . . . . . -0.3V to 6V
T
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
R
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
T
OUT
, INVALID, READY. . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
R
OUT
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Operating Conditions
Temperature Range
ICL32XXEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXEI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied .
NOTE:
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
1. θ
JA
Thermal Resistance (Typical, Note 1)
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 140
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 125
28 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
θ
JA
(°C/W)
Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
DC CHARACTERISTICS
Supply Current, Automatic Powerdown
Supply Current, Powerdown FORCEOFF Supply Current,
Automatic Powerdown Disabled
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low T Input Logic Threshold High T
Transmitter Input Hysteresis 25 - 0.5 - V Input Leakage Current T Output Leakage Current FORCEOFF Output Voltage Low I Output Voltage High I
RECEIVER INPUTS
Open, FORCEON = GND, FORCEOFF =V
All R
IN
All Outputs Unloaded, FORCEON = FORCEOFF
, FORCEON, FORCEOFF Full - - 0.8 V
IN
, FORCEON, FORCEOFF VCC = 3.3V Full 2.0 - - V
IN
, FORCEON, FORCEOFF Full - ±0.01 ±1.0 µA
IN
= 1.6mA Full - - 0.4 V
OUT
= -1.0mA Full V
OUT
= 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
CC
= 25°C
A
TEMP
(°C) MIN TYP MAX UNITS
CC
= GND 25 - 1.0 10 µA
=V
CC
= 5.0V Full 2.4 - - V
V
CC
= GND, ICL3244E Only Full - ±0.05 ±10 µA
25 - 1.0 10 µA
25 - 0.3 1.0 mA
CC
-0.6 V
-0.1 - V
CC
Input Voltage Range Full -25 - 25 V Input Threshold Low V
= 3.3V 25 0.6 1.2 - V
CC
= 5.0V 25 0.8 1.5 - V
V
CC
6
ICL3224E, ICL3226E, ICL3244E
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Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
Input Threshold High VCC = 3.3V 25 - 1.5 2.4 V
= 5.0V 25 - 1.8 2.4 V
V
CC
Input Hysteresis 25 - 0.5 - V Input Resistance 25 3 5 7 kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V Output Resistance V Output Short-Circuit Current Full - ±35 ±60 mA Output Leakage Current V
MOUSE DRIVEABILITY (ICL3244E Only) Transmitter Output Voltage
(See Figure 11) ENHANCED AUTOMATIC POWERDOWN (FORCEON = GND, FORCEOFF
= V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
CC
= ±12V, VCC= 0V or 3V to 5.5V
OUT
Automatic Powerdown or FORCEOFF
=T2IN=GND, T3IN=VCC, T3
T1
IN
to GND, T1
OUT
= 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
CC
= 25°C (Continued)
A
TEMP
(°C) MIN TYP MAX UNITS
Full - - ±25 µA
Full ±5--V
and T2
=GND
Loaded with 3kΩ
Loaded with 2.5mA Each
OUT
OUT
= VCC)
Receiver Input Thresholds to INVALID
Receiver Input Thresholds to INVALID
INVALID Low
INVALID High
Receiver Positive or Negative Threshold to INVALID (t
Receiver Positive or Negative Threshold to INVALID (t
Receiver or Transmitter Edge to Transmitters Enabled Delay (t
Receiver or Transmitter Edge to Transmitters Disabled Delay (t
TIMING CHARACTERISTICS
Maximum Data Rate R Receiver Propagation Delay Receiver Input to Receiver
Receiver Output Enable Time Normal Operation (ICL3244E Only) 25 - 200 - ns
High
Low , READY Output Voltage
, READY Output Voltage
INVH)
INVL)
AUTOPWDN
)
High Delay
Low Delay
See F i g u re 6 Full -2.7 - 2.7 V
See Figure 6 Full -0.3 - 0.3 V
I
= 1.6mA Full - - 0.4 V
OUT
I
= -1.0mA Full VCC-0.6 - - V
OUT
25 - 1 - µs
25 - 30 - µs
Note 2 25 - 100 - µs
)
WU
Note 2 Full 15 30 60 sec
=3kΩ, CL= 1000pF, One Transmitter Switching Full 250 500 - kbps
L
Output, C
= 150pF
L
t
PHL
t
PLH
25 - 0.15 - µs 25 - 0.15 - µs
Receiver Output Disable Time Normal Operation (ICL3244E Only) 25 - 200 - ns Transmitter Skew t
PHL
- t
PLH
7
25 - 100 - ns
ICL3224E, ICL3226E, ICL3244E
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Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
Receiver Skew t Transition Region Slew Rate V
ESD PERFORMANCE
RS-232 Pins (T
All Other Pins Human Body Model 25 - ±3-kV
NOTE:
2. An “edge” is defined as a transition through the transmitter or receiver input thresholds.
, RIN) Human Body Model 25 - ±15 - kV
OUT
- t
PHL
PLH
=3.3V,
CC
R
=3kΩ to 7kΩ,
L
Measured From 3V to -3V or -3V to 3V
IEC61000-4-2 Contact Discharge 25 - ±8-kV IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV
Detailed Description
These ICL32XXE interface ICs operate from a single +3V to +5.5V supply, guarantee a 250kbps minimum data rate, require only four small external 0.1µF capacitors, f eat ure lo w power consumption, and meet all ElA RS-232C and V.28 specifications. The circuit is divided into three sections: The charge pump, the transmitters, and the receivers.
Charge-Pump
Intersil’s new ICL32XXE family utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate ±5.5V transmitter supplies from a V supply as low as 3.0V. This allows these devices to maintain RS-232 compliant output levels over the ±10% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1µF capacitors for the voltage doubler and inverter functions at V See the “Capacitor Selection” section, and Table 3 for capacitor recommendations for other operating conditions. The char ge pumps operate discontinuously (i.e., the y turn off as soon as the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings.
= 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
CC
= 25°C (Continued)
A
TEMP
(°C) MIN TYP MAX UNITS
25 - 50 - ns
= 150pF to 1000pF 25 6 - 30 V/µs
C
L
= 150pF to 2500pF 25 4 8 30 V/µs
C
L
All devices guarantee a 250kbps data rate for full load conditions (3kΩ and 1000pF), V transmitter operating at full speed. Under more typical conditions of V
≥ 3.3V, RL=3kΩ, and CL= 250pF, one
CC
transmitter easily operates at 1Mbps. Transmitter inputs float if left uncon nected, and may cause
I
increases. Connect unused inputs to GND for the best
CC
performance.
Receivers
All the ICL32XXE devices contain standard inverting
CC
CC
=3.3V.
receivers, but only the ICL3244E receivers can three-state, via the FORCEOFF
control line. Additionally, the ICL3244E includes a noninverting (monitor) receiver (denoted by the R
label) that is always active , regardless of the state of
OUTB
any control lines. Both receiver types convert RS-232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3kΩ to 7kΩ input impedance (see Figure 1) even if the power is off (V Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions.
≥ 3.0V, with one
CC
= 0V). The receivers’
CC
Transmitters
The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232 output levels. Coupled with the on-chip ±5.5V supplies, these
-25V ≤ V
transmitters deliver true RS-232 levels over a wide range of single supply system voltages.
FIGURE 1. INVERTING RECEIVER CONNECTIONS
Transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (see Table 2). These outputs may be driven to ±12V when disabled.
8
R
RIN
GND
V
CC
XIN
≤ +25V
5kΩ
R
GND ≤ V
XOUT
ROUT
≤ V
CC
ICL3224E, ICL3226E, ICL3244E
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The ICL3244E inverting receivers disable during forced (manual) powerdown, but not during automatic powerdown (see Table 2). Conversely, the monitor receiver remains active even during manual powerdown making it extremely useful for Ring Indicator monitoring. Standard receivers
TABLE 2. POWERDOWN LOGIC TRUTH TABLE
RCVR OR
XMTR EDGE
WITHIN 30
SEC?
ICL3224E, ICL3226E
NO H H Active Active N.A. NO L Normal Operation (Enhanced
NO H H Active Active N.A. YES H YES H L Active Active N.A. NO L Normal Operation (Enhanced YES H L Active Active N.A. YES H
NO H L High-Z Active N.A. NO L Powerdown Due to Enhanced
NO H L High-Z Active N.A. YES H
X L X High-Z Active N.A. NO L Manual Powerdown X L X High-Z Active N.A. YES H
ICL322XE - INVALID
X NOTE 4 NOTE 4 Active Active N.A. YES H Normal Operation X NOTE 4 NOTE 4 High-Z Active N.A. NO L Forced Auto Powerdown
ICL3244E
NO H H Active Active Active NO L Normal Operation (Enhanced
NO H H Active Active Active YES H YES H L Active Active Active NO L Normal Operation (Enhanced YES H L Active Active Active YES H
NO H L High-Z Active Active NO L Powerdown Due to Enhanced
NO H L High-Z Active Active YES H
X L X High-Z High-Z Active NO L Manual Powerdown X L X High-Z High-Z Active YES H
ICL3244E - INVALID
X NOTE 4 NOTE 4 Active Active Active YES H Normal Operation X NOTE 4 NOTE 4 High-Z High-Z Active NO L Forced Auto Powerdown
NOTES:
3. Applies only to the ICL3244E.
4. Input is connected to INVALID
FORCEOFF
INPUT
FORCEON
INPUT
DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
Output.
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
driving powered down peripherals must be disabled to prevent current flow through the peripheral’s protection diodes (see Figures 2 and 3). This renders them useless for wake up functions, but the corresponding monitor receiver can be dedicated to this task as shown in Figure 3.
RS-232
LEVEL
PRESENT
(NOTE 3)
R
OUTB
OUTPUTS
AT
RECEIVER
INPUT?
INVALID
OUTPUT MODE OF OPERATION
Auto Powerdown Disabled)
Auto Powerdown Enabled)
Auto Powerdown Logic
Auto Powerdown Disabled)
Auto Powerdown Enabled)
Auto Powerdown Logic
9
ICL3224E, ICL3226E, ICL3244E
www.BDTIC.com/Intersil
V
CC
V
CC
V
OUT = VCC
Rx
POWERED
DOWN
UART
Tx
= GND
GND
FIGURE 2. POWER DRAIN THROUGH PO WERED DO WN
PERIPHERAL
TO
WAKE-UP
LOGIC
V
CC
R
X
POWERED
DOWN
UART
T
X
FORCEOFF = GND
SHDN
TRANSITION
DETECTOR
R2
V
OUT =
V
OUTB
R2
T1
CC
HI-Z
OUT
IN
V
CC
CURRENT FLOW
OLD
RS-232 CHIP
ICL3244E
R2
T1
IN
OUT
active and powerdown modes, under logic or software control, only the FORCEOFF FORCEON state isn’t critical, as FORCEOFF
input need be driven. The
dominates over FORCEON. Nev ertheless, if strictly manual control over powerdown is desired, the user must strap FORCEON high to disable the enhanced automatic powerdown circuitry. ICL3244E inverting (standard) receiver outputs also disable when the device is in powerdown, thereby eliminating the possible current path through a shutdown peripheral’s input protection diode (see Figures 2 and 3).
Connecting FORCEOFF
and FORCEON together disables the enhanced automatic powerdown feature, enabling them to function as a manual SHUTDOWN
FORCEOFF
PWR MGT
LOGIC
CPU
FIGURE 4. CONNECTIONS FOR MANUAL POWERDO WN
WHEN NO VALID RECEIVER SIGNALS ARE PRESENT
I/O
UART
FORCEON
INVALID
input (see Figure 4).
ICL32XXE
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
Po werdown Functionality
This 3V family of RS-232 interface devices requires a nominal supply current of 0.3mA during normal operation (not in powerdown mode). This is considerably less than the 5mA to 11mA current required of 5V RS-232 devices. The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to 1µA, because the on-chip charge pump turns off (V+ collapses to V the transmitter outputs three-state. Inverting receiver outputs may or may not disable in powerdown; refer to Table 2 for details. This micro-power mode makes these devices ideal for battery powered and portable applications.
Software Controlled (Manual) Powerdown
These devices allow the user to force the IC into the low power, standby state, and utilize a two pin approach where the FORCEON and FORCEOFF mode. For always enabled operation, FORCEON and FORCEOFF
are both strapped high. To switch between
, V- collapses to GND), and
CC
inputs determine the IC’s
With any of the above control schemes, the time required to exit powerdown, and resume transmission is only 100µs.
When using both manual and enhanced automatic powerdown (FORCEON = 0), the ICL32XXE won’t power up from manual powerdown until both FORCEOFF
and FORCEON are driven high, or until a transition occurs on a receiver or transmitter input. Figure 5 illustrates a circuit for ensuring that the ICL32XXE powers up as soon as FORCEOFF
switches high. The rising edge of the Master Powerdown signal forces the device to power up, and the ICL32XXE returns to enhanced automatic powerdown mode an RC time constant after this rising edge. The time constant isn’t critical, because the ICL32XXE remains powered up for 30 seconds after the FORCEON falling edge, even if there are no signal transitions. This gives slow-to-wake systems (e.g., a mouse) plenty of time to start transmitting, and as long as it starts transmitting within 30 seconds both systems remain enabled.
10
ICL3224E, ICL3226E, ICL3244E
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POWER
MANAGEMENT
UNIT
FIGURE 5. CIRCUIT TO ENSURE IMMEDIA TE PO WER UP
WHEN EXITING FORCED POWERDOWN
INVALID Output
The INVALID output always indicates (see Table 2) whether or not 30µs have elapsed with invalid RS-232 signals (see Figures 6 and 8) persisting on all of the receiver inputs, giving the user an easy way to determine when the interface block should power down. Invalid receiver levels occur whenever the driving peripheral’s outputs are shut off (powered down) or when the RS-232 interface cable is disconnected. In the case of a disconnected interface cable where all the receiver inpu ts are fl oa ti n g (but pulled to GND by the internal receiver pull down resistors), the INVALID logic detects the invalid levels and drives the output low . The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, INVALID and the power management logic wakes up the interface block. INVALID RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to GND (as in the case of a powered down driver).
2.7V
0.3V INVALID LEVEL - INVALID
-0.3V
MASTER POWERDOWN LINE
0.1µF
FORCEOFF FORCEON
ICL32XXE
1MΩ
switches high,
can also be used to indicate the DTR or
VALID RS-232 LEVEL - INVALID
INDETERMINATE
= 0
INDETERMINATE
= 1
whenever it detects a transition on one of these inputs. This automatic powerdown feature provides additional system power savings without changes to the existing operating system.
Enhanced automatic powerdown operates when the FORCEON input is low, and the FORCEOFF
input is high. Tying FORCEON high disables automatic powerdown, but manual powerdown is always available via the overriding FORCEOFF
input. Table 2 summarizes the enhanced
automatic powerdown functionality. Figure 7 illustrates the enhanced powerdown control logic.
Note that once the ICL32XXE enters powerdown (manually or automatically), the 30 second timer remains timed out (set), keeping the ICL32XXE powered down until FORCEON transitions high, or until a transition occurs on a receiver or transmitter input.
FORCEOFF
T_IN
R_IN
FIGURE 7. ENHANCED AUTOMATIC POWERDOWN LOGIC
The INVALID
EDGE
DETECT
EDGE
DETECT
FORCEON
S
30s
TIMER
R
output signal switches low to indicate that
AUTOSHDN
invalid levels have persisted on all of the receiver inputs for more than 30µs (see Figure 8), but this has no direct effect on the state of the ICL32XXE (see the next sections for methods of utilizing INVALID INVALID
switches high 1µs after detecting a valid RS-232
level on a receiver input. INVALID
to power down the device).
operates in all modes (forced or automatic powerdown, or forced on), so it is also useful for systems employing manual powerdown circuitry.
The time to recover from automatic powerdown mode is typically 100µs.
-2.7V VALID RS-232 LEVEL - INVALID
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
= 1
Enhanced Automatic Powerdown
Even greater power savings is available by using these devices which feature an enhanced automatic powerdown function. When the enhanced powerdown logic determines that no transitions have occurred on any of the transmitter nor receiver inputs for 30 seconds, the charge pump and transmitters powerdown, thereby reducing supply current to 1µA. The ICL32XXE automatically powers back up
Emulating Standard Automatic Powerdown
If enhanced automatic powerdown isn’t desired, the user can implement the standard automatic powerdown feature (mimics the function on the ICL3221E/23E/43E) by connecting the INVALID FORCEOFF invalid receiver levels, INVAL ID ICL32XXE into a forced powerdown condition. INVALID switches high as soon as a receiver input senses a valid RS-232 level, forcing the ICL32XXE to power on. See the “INVALID of Table 2 for an operational summary. This operational mode is perfect for handheld devices that communicate with
inputs, as shown in Figure 9. After 30µs of
DRIVING FORCEON AND FORCEOFF” section
11
output to the FORCEON and
switches low and drives the
ICL3224E, ICL3226E, ICL3244E
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RECEIVER
INPUTS
TRANSMITTER
INPUTS
TRANSMITTER
OUTPUTS
INVALID
OUTPUT
READY
OUTPUT
V+
V
CC
t
INVL
0
V-
FIGURE 8. ENHANCED AUTOMATIC POWERDOWN, INVALID AND READY TIMING DIAGRAMS
t
INVH
t
AUTOPWDN
another computer via a detachable cable. Detaching the cable allows the internal receiver pull-down resistors to pull the inputs to GND (an invalid RS-232 level), causing the 30µs timer to time-out and drive the IC into powerdown. Reconnecting the cable restores valid levels, causing the IC to power back up.
t
WU
t
AUTOPWDN
t
WU
INVALID
ICL32XXE
FORCEOFF
FORCEON
INVALID
}
REGION
Hybrid Automatic Powerdown Options
For devices which communicate only through a detachable cable, connecting INVALID FORCEON = 0) may be a desirable configuration. While the cable is attached INVALID the enhanced automatic powerdown logic powers down the RS-232 device whenever there is 30 seconds of inactivity on the receiver and transmitter inputs. Detaching the cable allows the receiver inputs to drop to an invalid level (GND), so INVALID
switches low and forces the RS-232 device to power down. The ICL32XXE remains powered down until the cable is reconnected (INV ALID transition occurs on a receiver or transmitter input (see Figure 7). For immediate power up when the cable is reattached, connect FORCEON to FORCEOFF network similar to that shown in Figure 5.
to FORCEOFF (with
and FORCEOFF remain high, so
= FORCEOFF = 1) and a
through a
I/O
CPU
FIGURE 9. CONNECTIONS FOR AUTOMATIC POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE PRESENT
UART
Ready Output (ICL3224E and ICL3226E only)
The Ready output indicates that the ICL322XE is ready to transmit. Ready switches low whenever the de vice enters powerdown, and switches back high during power-up when V- reaches -4V or lower.
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V operation. For other supply voltages refer to Table 3 for capacitor values. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C increased without increasing C increase C
without also increasing C2, C3, and C4 to
1
maintain the proper ratios (C
, C3, and C4 can be
2
’s value, however, do not
1
to the other capacitors).
1
12
ICL3224E, ICL3226E, ICL3244E
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When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-.
TABLE 3. REQUIRED CAPACITOR VALUES
V
(V)
CC
C
(µF)
1
C
2
, C3, C
(µF)
4
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 0.47
Po wer Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple V capacitor of the same value as the charge-p ump capacitor C
to ground with a
CC
1
Connect the bypass capacitor as close as possible to the IC.
Operation Down to 2.7V
ICL32XXE transmitter outputs meet RS-562 levels (±3.7V), at full data rate, with V typically ensure inter operability with RS-232 devices.
as low as 2.7V. RS-562 levels
CC
Mouse Driveability
The ICL3244E is specifically designed to power a serial mouse while operating from low voltage supplies. Figure 11 shows the transmitter output voltages under increasing load current. The on-chip switching regulator ensures the transmitters will supply at least conditions (15mA for paralleled V+ transmitters, 7.3mA for single V- transmitter).
6 5 4 3 2 1 0
-1
-2
-3
.
-4
-5
TRANSMITTER OUTPUT VOLTAGE (V)
-6 0246810
FIGURE 11. TRANSMITTER OUTPUT VOL TAGE vs LOAD
V
= 3.0V
CC
T1
V
T2
V
T3
CC
13579
LOAD CURRENT PER TRANSMITTER (mA)
ICL3244E V
CURRENT (PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS FOR TOTAL V
±5V during worst case
+
OUT
-
OUT
V
OUT+
V
OUT
OUT
+
-
CURRENT)
Transmitter Outputs when Exiting Powerdown
Figure 10 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V.
5V/DIV.
2V/DIV.
5V/DIV.
FIGURE 10. TRANSMITTER OUTPUTS WHEN EXITING
FORCEOFF
T1
VCC = +3.3V C1 - C4 = 0.1µF
T2
READY
TIME (20µs/DIV.)
POWERDOWN
High Data Rates
The ICL32XXE maintain the RS-232 ±5V minimum transmitter output voltages ev en at high data rates. Figure 12 details a transmitter loopback test circuit, and Figure 13 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF, at 120kbps. Figure 14 shows the loopback results for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an RS-232 receiver.
V
CC
0.1µF
+
C
1
+
C
2
V
CC
+
C1+
C1-
ICL32XXE
C2+
C2-
T
IN
R
OUT
FORCEON
FORCEOFF
V
CC
T
OUT
V+
V-
R
IN
5K
+
C
3
C
4
+
1000pF
FIGURE 12. TRANSMITTER LOOPBACK TEST CIRCUIT
13
ICL3224E, ICL3226E, ICL3244E
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5V/DIV.
T1
T1
OUT
R1
OUT
5V/DIV.
T1
T1
OUT
IN
VCC = +3.3V C1 - C4 = 0.1µF
5µs/DIV.
FIGURE 13. LOOPBACK TEST AT 120kbps
IN
±15kV ESD Protection
All pins on ICL32XX devices include ESD protection structures, but the ICL32XXE family incorporates advanced structures which allow the RS-232 pins (transmitter outputs and receiver inputs) to survive ESD events up to ±15kV. The RS-232 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and don’t interfere with RS-232 signals as large as ±25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge through a 1.5kΩ current limiting resistor, making the test less severe than the IEC61000 test which utilizes a 330Ω limiting resistor. The HBM method determines an ICs ability to withstand the ESD transients typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested with respect to all other pins. The RS-232 pins on “E” family devices can withstand HBM ESD events to ±15kV.
R1
OUT
VCC = +3.3V C1 - C4 = 0.1µF
2µs/DIV.
FIGURE 14. LOOPBACK TEST AT 250kbps
Interconnection with 3V and 5V Logic
The ICL32XXE directly interfaces with 5V CMOS and TTL logic families. Nev ertheless, with the ICL32XX at 3.3V, and the logic supply at 5V, AC, HC, and CD4000 outputs can drive ICL32XX inputs, but ICL32XX outputs do not reach the minimum V information.
T ABLE 4. LOGIC F AMILY COMP ATIBILITY WITH VARIOUS
SYSTEM
POWER-SUPPLY
VOLTAGE
for these logic families. See Table 4 for more
IH
SUPPLY VOLTAGES
V
CC
SUPPLY
VOLTAGE
(V)
3.3 3.3 Compatible with all CMOS
5 5 Compatible with all TTL and
5 3.3 Compatible with ACT and HCT
(V) COMPATIBILITY
families.
CMOS logic families.
CMOS, and with TTL. ICL32XX outputs are incompatible with AC, HC, and CD4000 CMOS inputs.
IEC61000-4-2 Testing
The IEC 61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD ev ent are those that are e xposed to the outside world (the RS-232 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The e xtra ESD protection built into this device’s RS-232 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The “E” device RS-232 pins withstand ±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing de vices at voltages higher than ±8kV. All “E” family devices survive ±8kV contact discharges on the RS-232 pins.
14
ICL3224E, ICL3226E, ICL3244E
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Typical Performance Curves V
6
4
2
1 TRANSMITTER AT 250kbps OTHER TRANSMITTERS AT 30kbps
0
-2
-4
TRANSMITTER OUTPUT VOLTAGE (V)
-6 1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
= 3.3V, TA = 25°C
CC
V
+
OUT
V
-
OUT
FIGURE 15. TRANSMITTER OUTPUT VOL TAGE vs LOAD
CAPACITANCE
40
ICL3224E
35
30
250kbps
25
20
15
SLEW RATE (V/µs)
10
5
0 1000 2000 3000 4000 5000
-SLEW
+SLEW
LOAD CAPACITANCE (pF)
FIGURE 16. SLEW RATE vs LOAD CAPACITANCE
35
ICL3226E
30
25
250kbps
25
20
15
SUPPLY CURRENT (mA)
10
5
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
120kbps
20kbps
FIGURE 17. SUPPL Y CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
45
ICL3244E
40
250kbps
3000
120kbps
20kbps
4000
SUPPLY CURRENT (mA)
35
30
25
20
15
10
0
1000
2000
LOAD CAPACITANCE (pF)
5000
20
15
10
SUPPLY CURRENT (mA)
5
0
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
120kbps
20kbps
FIGURE 18. SUPPL Y CURRENT vs LO AD CAPACITANCE
WHEN TRANSMITTING DATA
3.5
3.0
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V)
NO LOAD ALL OUTPUTS STATIC
FIGURE 19. SUPPL Y CURRENT vs LOAD CAPACITANCE
FIGURE 20. SUPPLY CURRENT vs SUPPLY VOLTAGE
WHEN TRANSMITTING DATA
15
Die Characteristics
www.BDTIC.com/Intersil
SUBSTRATE POTENTIAL (P OWERED UP)
GND
TRANSISTOR COUNT
ICL3224E: 937 ICL3226E: 825 ICL3244E: 1109
PROCESS
Si Gate CMOS
ICL3224E, ICL3226E, ICL3244E
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Shrink Small Outline Plastic Packages (SSOP)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) B
H
α
e
B
0.25(0.010) C AMB
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.
M
A1
0.10(0.004)
S
GAUGE
PLANE
M
0.25
0.010
A2
M
L
M20.209 (JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.068 0.078 1.73 1.99 A1 0.002 0.008’ 0.05 0.21 A2 0.066 0.070’ 1.68 1.78
B 0.010’ 0.015 0.25 0.38 9
C 0.004 0.008 0.09 0.20’
D 0.278 0.289 7.07 7.33 3
E 0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
C
H 0.301 0.311 7.65 7.90’
L 0.025 0.037 0.63 0.95 6
N20 207
α
0 deg. 8 deg. 0 deg. 8 deg.
NOTESMIN MAX MIN MAX
Rev. 3 11/02
17
ICL3224E, ICL3226E, ICL3244E
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Small Outline Plastic Packages (SSOP)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
GAUGE PLANE
0.25
0.010
L
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen­sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
M
A1
0.10(0.004)
A2
C
M16.209 (JEDEC MO-150-AC ISSUE B)
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.233 0.255 5.90 6.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N16 167
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 3 6/05
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ICL3224E, ICL3226E, ICL3244E
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Shrink Small Outline Plastic Packages (SSOP)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
GAUGE PLANE
0.25
0.010
L
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
M
A1
0.10(0.004)
A2
C
M28.209 (JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.390 0.413 9.90 10.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N28 287
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 2 6/05
19
ICL3224E, ICL3226E, ICL3244E
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Small Outline Plastic Packages (SOIC)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
L
h x 45
o
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.
M
A1
0.10(0.004)
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 ­D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 -
C
h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N28 287
o
α
0
o
8
o
0
o
8
Rev. 0 12/93
NOTESMIN MAX MIN MAX
-
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted b y implica tion or ot herw ise un der any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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