®
www.BDTIC.com/Intersil
ICL3224, ICL3226, ICL3238, ICL3244
Data Sheet March 1, 2006
1 Microamp, +3V to +5.5V, 250kbps,
RS-232 Transceivers with Enhanced
Automatic Powerdown
The Intersil ICL32XX devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at V
applications are PDAs, Palmtops, and notebook and laptop
computers where the low operational, and even lower
standby, power consumption is critical. Efficient on-chip
charge pumps, coupled with manual and enhanced
automatic powerdown functions, reduce the standby supply
current to a 1µA trickle. Small footprint packaging, and the
use of small, low value capacitors ensure board space
savings as well. Data rates greater than 250kbps are
guaranteed at worst case load conditions. This family is fully
compatible with 3.3V only systems, mixed 3.3V and 5.0V
systems, and 5.0V only systems.
The ICL3244 is a 3 driver, 5 receiver device that provides a
complete serial port suitable for laptop or notebook
computers. The ICL3244/38 also include a noninverting
always-active receiver for RING INDICATOR monitoring.
These devices feature an enhanced automatic
powerdown function which powers down the on-chip powersupply and driver circuits. This occurs when all receiver and
transmitter inputs detect no signal transitions for a period of
30sec. These devices power back up, automatically,
whenever they sense a transition on any transmitter or
receiver input.
Table 1 summarizes the features of the devices represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XX 3V family.
= 3.0V. Targeted
CC
FN4876.10
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
•
±15kV ESD Protected (Human Body Model)
• Manual and Enhanced Automatic Powerdown Features
• Drop in Replacements for MAX3224, MAX3226,
MAX3238, MAX3244
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• RS-232 Compatible with V
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Flow-Through Pinout (ICL3238)
• Guaranteed Mouse Driveability (ICL3244)
• “Ready to Transmit” Indicator Output (ICL3224/26)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 6V/µs
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
CC
= 2.7V
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
- Data Cradles
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• AN9863, “3V to +5.5V, 250k-1Mbps, RS-232
Transmitters/Receivers”
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER
ICL3224 2 2 0 250 NO YES YES YES
ICL3226 1 1 0 250 NO YES YES YES
ICL3238 5 3 1 250 NO NO YES YES
ICL3244 3 5 1 250 NO NO YES YES
NO. OF
Tx.
NO. OF
Rx.
1
NO. OF
MONITOR Rx.
)
(R
OUTB
DATA
RATE
(kbps)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
Rx. ENABLE
FUNCTION?
Copyright © Intersil Americas Inc. 2001, 2002, 2004-2006. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
READY
OUTPUT?
MANUAL
POWER-
DOWN?
ENHANCED
AUTOMATIC
POWERDOWN
www.BDTIC.com/Intersil
Ordering Information
ICL3224, ICL3226, ICL3238, ICL3244
Ordering Information (Continued)
TEMP.
PART
NUMBER
*
PART
MARKING
RANGE
(°C) PACKAGE
PKG.
DWG. #
ICL3224CA ICL3224CA 0 to 70 20 Ld SSOP M20.209
ICL3224CAZ
(Note)
3224CAZ 0 to 70 20 Ld SSOP
(Pb-free)
M20.209
ICL3224IA ICL3224IA -40 to 85 20 Ld SSOP M20.209
ICL3224IAZ
(Note)
3224IAZ -40 to 85 20 Ld SSOP
(Pb-free)
M20.209
ICL3226CA ICL3226CA 0 to 70 16 Ld SSOP M16.209
ICL3226CAZ
(Note)
ICL3226CAZ 0 to 70 16 Ld SSOP
(Pb-free)
M16.209
ICL3226IA ICL3226IA -40 to 85 16 Ld SSOP M16.209
ICL3226IAZ
(Note)
ICL3226IAZ -40 to 85 16 Ld SSOP
(Pb-free)
M16.209
ICL3238CA ICL3238CA 0 to 70 28 Ld SSOP M28.209
Pinouts
ICL3224 (SSOP)
TOP VIEW
TEMP.
PART
NUMBER
*
ICL3238CAZ
(Note)
PART
MARKING
ICL3238CAZ 0 to 70 28 Ld SSOP
RANGE
(°C) PACKAGE
(Pb-free)
PKG.
DWG. #
M28.209
ICL3238IA ICL3238IA -40 to 85 28 Ld SSOP M28.209
ICL3238IAZ
(Note)
ICL3238IAZ -40 to 85 28 Ld SSOP
(Pb-free)
M28.209
ICL3244CA ICL3244CA 0 to 70 28 Ld SSOP M28.209
ICL3244IA ICL3244IA -40 to 85 28 Ld SSOP M28.209
*Most surface mount devices are available on tape and reel; add “-T”
to suffix.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
ICL3226 (SSOP)
TOP VIEW
READY
C1+
V+
C1-
C2+
C2-
T2
OUT
R2
R2
OUT
FORCEOFF
1
2
3
4
5
6
V-
7
8
9
IN
10
20
V
19
GND
18
17
T1
R1
16
R1
15
FORCEON
14
T1
13
12
T2
INVALID
11
CC
OUT
IN
OUT
IN
IN
READY
C1+
V+
C1-
C2+
C2-
R1
16
1
2
3
4
5
6
V-
7
8
IN
FORCEOFF
V
15
CC
GND
14
13
T1
FORCEON
12
T1
11
INVALID
10
R1
9
OUT
IN
OUT
2
FN4876.10
March 1, 2006
Pinouts (Continued)
www.BDTIC.com/Intersil
C2+
1
GND
2
3
C2-
V-
4
T1
5
OUT
T2
6
OUT
T3
7
OUT
R1
8
IN
R2
9
IN
10
T4
OUT
R3
11
IN
T5
12
OUT
FORCEON
FORCEOFF
13
14
ICL3238 (SSOP)
TOP VIEW
ICL3224, ICL3226, ICL3238, ICL3244
C1+
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V+
V
CC
C1T1
IN
T2
IN
T3
IN
R1
OUT
R2
OUT
T4
IN
R3
OUT
T5
IN
R1
OUTB
INVALID
T1
T2
T3
C2+
R1
R2
R3
R4
R5
OUT
OUT
OUT
T3
T2
T1
C2-
V-
IN
IN
IN
IN
IN
IN
IN
IN
ICL3244 (SSOP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
C1+
V+
27
V
26
CC
GND
25
C1-
24
FORCEON
23
FORCEOFF
22
INVALID
21
20
R2
R1
19
R2
18
R3
17
16
R4
R5
15
OUTB
OUT
OUT
OUT
OUT
OUT
3
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Pin Descriptions
PIN FUNCTION
V
CC
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
T
T
OUT
R
R
OUT
R
OUTB
INVALID
READY Active high output that indicates when the ICL32XX is ready to transmit (i.e., V- ≤ -4V)
FORCEOFF
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF
System power supply input (3.0V to 5.5V).
TTL/CMOS compatible transmitter Input s.
IN
RS-232 level (nominally ±5.5V) transmitter outputs.
RS-232 compatible receiver inputs.
IN
TTL/CMOS level receiver outputs.
TTL/CMOS level, noninverting, always enabled receiver outputs.
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).
must be high).
Typical Operating Circuits
ICL3224 ICL3226
+3.3V
TTL/CMOS
LOGIC
LEVELS
C
0.1µF
C
0.1µF
+
0.1µF
2
T2
R1
T1
IN
IN
OUT
OUT
+
4
5
+
6
13
12
15
1
14
C1+
C1-
C2+
C2-
READY
FORCEON
1
2
R2
19
V
CC
T
1
T
2
R
1
R
2
FORCEOFF
GND
18
INVALID
V+
V-
5kΩ
5kΩ
3
7
17
T1
8
T2
16
R1
910
R2
20
11
C
3
+
0.1µF
C
4
0.1µF
+
OUT
OUT
RS-232
LEVELS
IN
IN
V
CC
TO POWER
CONTROL
LOGIC
+3.3V
TTL/CMOS
LOGIC
LEVELS
C
0.1µF
C
0.1µF
R1
+
0.1µF
2
C1+
1
+
4
C1-
5
2
C2+
+
6
C2-
11
T1
IN
OUT
1
READY
12
FORCEON
15
V
CC
T
1
R
1
FORCEOFF
GND
14
V+
V-
5kΩ
INVALID
3
7
13
T1
89
R1
16
10
C
3
+
0.1µF
C
4
0.1µF
+
OUT
RS-232
LEVELS
IN
V
CC
TO POWER
CONTROL
LOGIC
4
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Typical Operating Circuits (Continued)
ICL3238
C3 (OPTIONAL
+3.3V
NOTE 3
TTL/CMOS
LOGIC
LEVELS
TO POWER
CONTROL
C
0.1µF
C
0.1µF
R1
V
CC
LOGIC
+
0.1µF
28
1
2
C1+
+
25
C1-
1
C2+
+
3
C2-
24
T1
IN
23
T2
IN
22 7
T3
IN
19 10
T4
IN
17 12
T5
IN
26
V
CC
T
1
T
2
T
3
T
3
T
4
16
OUTB
21
R1
R2
R3
OUT
OUT
OUT
13
FORCEON
14
FORCEOFF
15
INVALID
R
1
R
2
R
3
GND
CONNECTION, NOTE 2)
V+
V-
5kΩ
5kΩ
5kΩ
2
27
4
5
6
8
920
1118
T1
T2
T3
T4
T5
R1
R2
R3
+
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
+
+
C
3
0.1µF
C
4
0.1µF
NOTE 3
RS-232
LEVELS
RS-232
LEVELS
+3.3V
C
0.1µF
C
0.1µF
R2
TTL/CMOS
R1
LOGIC
LEVELS
R2
R3
R4
R5
V
CC
TO POWER
CONTROL LOGIC
ICL3244
+
0.1µF
28
1
2
C1+
+
24
C1-
1
C2+
+
2
C2-
14
T1
IN
13
T2
IN
12 11
T3
IN
20
OUTB
19
OUT
OUT
OUT
OUT
OUT
23
FORCEON
22
FORCEOFF
21
INVALID
V
R
1
R
2
R
3
R
4
R
5
GND
CC
26
T
1
T
2
T
3
25
V+
V-
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
27
C
3
+
0.1µF
3
C
4
0.1µF
+
9
T1
OUT
10
T2
T3
OUT
OUT
RS-232
LEVELS
4
R1
IN
518
R2
IN
617
R3
RS-232
LEVELS
IN
716
R4
IN
815
R5
IN
NOTES:
1. THE NEGATIVE TERMINAL OF C
OR GND.
V
CC
2. FOR V
= 3.15V (3.3V -5%), USE C1 - C4 = 0.1µF OR GREATER. FOR
CC
= 3.0V (3.3V -10%), USE C1 - C4 = 0.22µF.
V
CC
CAN BE CONNECTED TO EITHER
3
5
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
, FORCEOFF, FORCEON . . . . . . . . . . . . . . . . . . -0.3V to 6V
T
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
R
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
T
OUT
, INVALID, READY . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
R
OUT
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. θ
JA
Thermal Resistance (Typical, Note 4) θ
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 140
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 125
28 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300°C
(Lead Tips Only)
(°C/W)
JA
Operating Conditions
Temperature Range
ICL32XXC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Electrical Specifications Test Conditions: V
Otherwise Specified. Typicals are at T
PARAMETER TEST CONDITIONS
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
Supply Current, Powerdown FORCEOFF
Supply Current,
Automatic Powerdown Disabled
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low T
Input Logic Threshold High T
Transmitter Input Hysteresis 25 - 0.5 - V
Input Leakage Current T
Output Leakage Current FORCEOFF
Output Voltage Low I
Output Voltage High I
RECEIVER INPUTS
Input Voltage Range Full -25 - 25 V
Input Threshold Low V
Input Threshold High V
Input Hysteresis 25 - 0.5 - V
Input Resistance 25357kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Output Resistance V
Output Short-Circuit Current Full - ±35 ±60 mA
Output Leakage Current V
All R
Open, FORCEON = GND, FORCEOFF = V
IN
All Outputs Unloaded, FORCEON
= FORCEOFF
, FORCEON, FORCEOFF Full - - 0.8 V
IN
, FORCEON, FORCEOFF VCC = 3.3V Full 2.0 - - V
IN
, FORCEON, FORCEOFF Full - ±0.01 ±1.0 µA
IN
= 1.6mA Full - - 0.4 V
OUT
= -1.0mA Full V
OUT
= 3.3V 25 0.6 1.2 - V
CC
V
= 5.0V 25 0.8 1.5 - V
CC
= 3.3V 25 - 1.5 2.4 V
CC
= 5.0V 25 - 1.8 2.4 V
V
CC
= V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
CC
= ±12V, VCC = 0V or 3V to 5.5V,
OUT
Automatic Powerdown or FORCEOFF
= 3V to 5.5V, C1 - C4 = 0.1µF (ICL3238: C1 - C4 = 0.22µF @ VCC = 3V); Unless
CC
= GND 25 - 1.0 10 µA
= V
CC
= GND Full - ±0.05 ±10 µA
= 25°C
A
TEMP
(°C) MIN TYP MAX UNITS
CC
ICL3244, VCC = 3V 25 - 0.3 1.0 mA
All Others, V
V
= 5.0V Full 2.4 - - V
CC
= GND
= 3.15V 25 - 0.3 1.0 mA
CC
25 - 1.0 10 µA
-0.6 V
CC
Full - - ±25 µA
-0.1 - V
CC
6
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Electrical Specifications Test Conditions: V
Otherwise Specified. Typicals are at T
PARAMETER TEST CONDITIONS
MOUSE DRIVEABILITY (ICL3244 Only)
Transmitter Output Voltage
(See Figure 11)
ENHANCED AUTOMATIC POWERDOWN (FORCEON = GND, FORCEOFF
Receiver Input Thresholds to
INVALID
Receiver Input Thresholds to
INVALID
INVALID
Low
INVALID
High
Receiver Positive or Negative
Threshold to INVALID
(t
Receiver Positive or Negative
Threshold to INVALID
(t
Receiver or Transmitter Edge to
Transmitters Enabled Delay (t
Receiver or Transmitter Edge to
Transmitters Disabled Delay
(t
TIMING CHARACTERISTICS
Maximum Data Rate R
Receiver Propagation Delay Receiver Input to Receiver
Receiver Output Enable Time Normal Operation (ICL3238/44 Only) 25 - 200 - ns
Receiver Output Disable Time Normal Operation (ICL3238/44 Only) 25 - 200 - ns
Transmitter Skew t
Receiver Skew t
Transition Region Slew Rate V
ESD PERFORMANCE
RS-232 Pins (T
All Other Pins Human Body Model 25 - ±2.5 - kV
NOTE:
High
Low
, READY Output Voltage
, READY Output Voltage
High Delay
)
INVH
)
INVL
AUTOPWDN
4. An “edge” is defined as a transition through the transmitter or receiver input thresholds.
)
Low Delay
WU
, RIN) Human Body Model 25 - ±15 - kV
OUT
= T2IN = GND, T3IN = VCC, T3
T1
IN
GND, T1
See F i g ure 6 Full -2.7 - 2.7 V
See Figure 6 Full -0.3 - 0.3 V
I
I
ICL3238 25 - 0.1 - µs
All Others 25 - 1 - µs
ICL3238
All Others 25 - 30 - µs
ICL3238, Note 5 25 - 25 - µs
)
All Others, Note 5 25 - 100 - µs
Note 5 Full153060sec
Output, C
R
Measured From 3V to -3V or -3V
to 3V
IEC61000-4-2 Contact Discharge 25 - ±8-kV
IEC61000-4-2 Air Gap Discharge 25 - ±10 - kV
OUT
= 1.6mA Full - - 0.4 V
OUT
= -1.0mA Full VCC-0.6 - - V
OUT
= 3kΩ, CL = 1000pF, One Transmitter Switching Full 250 500 - kbps
L
= 150pF
L
- t
PHL
PLH
- t
PHL
PLH
= 3.3V,
CC
= 3kΩ to 7kΩ,
L
= 3V to 5.5V, C1 - C4 = 0.1µF (ICL3238: C1 - C4 = 0.22µF @ VCC = 3V); Unless
CC
and T2
Loaded with 2.5mA Each
OUT
= 25°C (Continued)
A
TEMP
(°C) MIN TYP MAX UNITS
Loaded with 3kΩ to
OUT
= VCC)
t
PHL
t
PLH
= 150pF to 1000pF 25 6 - 30 V/µs
C
L
= 150pF to 2500pF 25 4 8 30 V/µs
C
L
Full ±5- -V
25 - 50 - µs
25 - 0.15 - µs
25 - 0.15 - µs
25 - 100 - ns
25 - 50 - ns
7
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Detailed Description
These ICL32XX interface ICs operate from a single +3V to
+5.5V supply, guarantee a 250kbps mini mu m da ta rate,
require only four small external 0.1µF capacitors, feature low
power consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
Charge-Pump
Intersil’s new ICL32XX family utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a V
low as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions at V
the “Capacitor Selection” section, and Table 3 for capacitor
recommendations for other operating conditions. The charge
pumps operate discontinuously (i.e., they turn off as soon as
the V+ and V- supplies are pumped up to the nominal
values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-232 levels over a wide
range of single supply system voltages.
Transmitter outputs disable and assume a high impedance
state when the device enters the powerdown mode (see
Table 2). These outputs may be driven to ±12V when
disabled.
supply as
CC
= 3.3V. See
CC
The ICL3238 and ICL3244 inverting receivers disable during
forced (manual) powerdown, but not during automatic
powerdown (see Table 2). Conversely, the monitor receiver
remains active even during manual powerdown making it
extremely useful for Ring Indicator monitoring. Standard
receivers driving powered down peripherals must be
disabled to prevent current flow through the peripheral’s
protection diodes (see Figures 2 and 3). This renders them
useless for wake up functions, but the corresponding
monitor receiver can be dedicated to this task as shown in
Figure 3.
V
CC
R
XIN
V
CC
SHDN
5kΩ
V
OUT = VCC
= GND
-25V ≤ V
FIGURE 1. INVERTING RECEIVER CONNECTIONS
POWERED
DOWN
V
UART
GND
CC
RIN
≤ +25V
GND
Rx
Tx
R
XOUT
GND ≤ V
V
CC
CURRENT
FLOW
OLD
RS-232 CHIP
ROUT
≤ V
CC
All devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), V
≥ 3.0V, with one
CC
transmitter operating at full speed. Under more typical
conditions of V
≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
CC
transmitter easily operates at 1Mbps.
Transmitter inputs float if left unconnected, and may cause
I
increases. Connect unused inputs to GND for the best
CC
performance.
Receivers
All the ICL32XX devices contain standard inverting
receivers, but only the ICL3238 and ICL3244 receivers can
tristate, via the FORCEOFF
ICL3238 and ICL3244 include a noninverting (monitor)
receiver (denoted by the R
regardless of the state of any control lines. Both receiver
types convert RS-232 signals to CMOS output levels and
accept inputs up to ±25V while presenting the required 3kΩ
to 7kΩ input impedance (see Figure 1) even if the power is
off (V
= 0V). The receivers’ Schmitt trigger input stage
CC
uses hysteresis to increase noise immunity and decrease
errors due to slow input signal transitions.
control line. Additionally, the
label) that is always active,
OUTB
8
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
V
CC
TRANSITION
DETECTOR
TO
WAKE-UP
LOGIC
V
CC
R
X
POWERED
DOWN
UART
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
T
X
FORCEOFF = GND
V
OUT =
R2
OUTB
R2
HI-Z
OUT
T1
IN
ICL3238/44
R2
IN
T1
OUT
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
TABLE 2. POWERDOWN LOGIC TRUTH TABLE
RS-232
RCVR OR
XMTR
EDGE
WITHIN 30
SEC?
ICL3224, ICL3226
NO H H Active Active N.A. NO L Normal Operation (Enhanced
NO H H Active Active N.A. YES H
YES H L Active Active N.A. NO L Normal Operation (Enhanced
YES H L Active Active N.A. YES H
NO H L High-Z Active N.A. NO L Powerdown Due to Enhanced
NO H L High-Z Active N.A. YES H
X L X High-Z Active N.A. NO L Manual Powerdown
X L X High-Z Active N.A. YES H
ICL322X - INVALID
X NOTE 7 NOTE 7 Active Active N.A. YES H Normal Operation
X NOTE 7 NOTE 7 High-Z Active N.A. NO L Forced Auto Powerdown
ICL3238, ICL3244
NO H H Active Active Active NO L Normal Operation (Enhanced
NO H H Active Active Active YES H
YES H L Active Active Active NO L Normal Operation (Enhanced
YES H L Active Active Active YES H
NO H L High-Z Active Active NO L Powerdown Due to Enhanced
NO H L High-Z Active Active YES H
X L X High-Z High-Z Active NO L Manual Powerdown
X L X High-Z High-Z Active YES H
ICL3238, ICL3244 - INVALID
X NOTE 7 NOTE 7 Active Active Active YES H Normal Operation
X NOTE 7 NOTE 7 High-Z High-Z Active NO L Forced Auto Powerdown
NOTES:
5. Applies only to the ICL3238 and ICL3244.
6. Input is connected to INVALID
FORCEOFF
INPUT
DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
FORCEON
INPUT
DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
Output.
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
(NOTE 6)
R
OUTB
OUTPUTS
LEVEL
PRESENT
AT
RECEIVER
INPUT?
INVALID
OUTPUT MODE OF OPERATION
Auto Powerdown Disabled)
Auto Powerdown Enabled)
Auto Powerdown Logic
Auto Powerdown Disabled)
Auto Powerdown Enabled)
Auto Powerdown Logic
Powerdown Functionality
This 3V family of RS-232 interface devices requires a
nominal supply current of 0.3mA during normal operation
(not in powerdown mode). This is considerably less than the
5mA to 11mA current required of 5V RS-232 devices. The
already low current requirement drops significantly when the
device enters powerdown mode. In powerdown, supply
current drops to 1µA, because the on-chip charge pump
turns off (V+ collapses to V
the transmitter outputs tristate. Inverting receiver outputs
may or may not disable in powerdown; refer to Table 2 for
details. This micro-power mode makes these devices ideal
for battery powered and portable applications.
Software Controlled (Manual) Powerdown
These devices allow the user to force the IC into the low
power, standby state, and utilize a two pin approach where
, V- collapses to GND), and
CC
the FORCEON and FORCEOFF
mode. For always enabled operation, FORCEON and
FORCEOFF
are both strapped high. To switch between
active and powerdown modes, under logic or software
control, only the FORCEOFF
FORCEON state isn’t critical, as FORCEOFF
over FORCEON. Nevertheless, if strictly manual control over
powerdown is desired, the user must strap FORCEON high
to disable the enhanced automatic powerdown circuitry.
ICL3238 and ICL3244 inverting (standard) receiver outputs
also disable when the device is in powerdown, thereby
eliminating the possible current path through a shutdown
peripheral’s input protection diode (see Figures 2 and 3).
Connecting FORCEOFF
the enhanced automatic powerdown feature, enabling them
to function as a manual SHUTDOWN
9
inputs determine the IC’s
input need be driven. The
dominates
and FORCEON together disables
input (see Figure 4).
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100µs.
FORCEOFF
PWR
MGT
LOGIC
CPU
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
FORCEON
INVALID
ICL32XX
I/O
UART
When using both manual and enhanced automatic powerdown
(FORCEON = 0), the ICL32XX won’t power up from manual
powerdown until both FORCEOFF
and FORCEON are driven
high, or until a transition occurs on a receiver or transmitter
input. Figure 5 illustrates a circuit for ensuring that the ICL32XX
powers up as soon as FORCEOFF
switches high. The rising
edge of the Master Powerdown signal forces the device to
power up, and the ICL32XX returns to enhanced automatic
powerdown mode an RC time constant after this rising edge.
The time constant isn’t critical, because the ICL32XX remains
powered up for 30 seconds after the FORCEON falling edge,
even if there are no signal transitions. This gives slow-to-wake
systems (e.g., a mouse) plenty of time to start transmitting, and
as long as it starts transmitting within 30 seconds both systems
remain enabled.
are floating (but pulled to GND by the internal receiver pull
down resistors), the INVALID
logic detects the invalid levels
and drives the output low. The power management logic then
uses this indicator to power down the interface block.
Reconnecting the cable restores valid levels at the receiver
inputs, INVALID
logic wakes up the interface block. INVALID
switches high, and the power management
can also be used
to indicate the DTR or RING INDICATOR signal, as long as
the other receiver inputs are floating, or driven to GND (as in
the case of a powered down driver).
2.7V
0.3V
-0.3V
-2.7V
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
VALID RS-232 LEVEL - INVALID
INDETERMINATE
INVALID LEVEL - INVALID
INDETERMINATE
VALID RS-232 LEVEL - INVALID
= 0
= 1
= 1
Enhanced Automatic Powerdown
Even greater power savings is available by using these
devices which feature an enhanced automatic powerdown
function. When the enhanced powerdown logic determines
that no transitions have occurred on any of the transmitter
nor receiver inputs for 30 seconds, the charge pump and
transmitters powerdown, thereby reducing supply current to
1µA. The ICL32XX automatically powers back up whenever
it detects a transition on one of these inputs. This automatic
powerdown feature provides additional system power
savings without changes to the existing operating system.
POWER
MANAGEMENT
UNIT
MASTER POWERDOWN LINE
0.1µF
1MΩ
Enhanced automatic powerdown operates when the
FORCEON input is low, and the FORCEOFF
Tying FORCEON high disables automatic powerdown, but
manual powerdown is always available via the overriding
FORCEOFF FORCEON
ICL32XX
FIGURE 5. CIRCUIT TO ENSURE IMMEDIATE POWER UP
WHEN EXITING FORCED POWERDOWN
FORCEOFF
automatic powerdown functionality.
T_IN
input. Table 2 summarizes the enhanced
EDGE
DETECT
INVALID Output
The INVALID output always indicates (see Table 2) whether
or not 30µs have elapsed with invalid RS-232 signals (see
Figures 6 and 8) persisting on all of the receiver inputs, giving
the user an easy way to determine when the interface block
R_IN
EDGE
DETECT
should power down. Invalid receiver levels occur whenever
the driving peripheral’s outputs are shut off (powered down) or
when the RS-232 interface cable is disconnected. In the case
of a disconnected interface cable where all the receiver inputs
FIGURE 7. ENHANCED AUTOMATIC POWERDOWN LOGIC
10
FORCEON
FORCEOFF
S
30sec
TIMER
R
input is high.
AUTOSHDN
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Figure 7 illustrates the enhanced powerdown control logic.
Note that once the ICL32XX enters powerdown (manually or
automatically), the 30 second timer remains timed out (set),
keeping the ICL32XX powered down until FORCEON
transitions high, or until a transition occurs on a receiver or
transmitter input.
The INVALID
output signal switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30µs (see Figure 8), but this has no direct effect
on the state of the ICL32XX (see the next sections for
methods of utilizing INVALID
INVALID
switches high 1µs after detecting a valid RS-232
level on a receiver input. INVALID
to power down the device).
operates in all modes
(forced or automatic powerdown, or forced on), so it is also
useful for systems employing manual powerdown circuitry.
The time to recover from automatic powerdown mode is
typically 100µs.
Emulating Standard Automatic Powerdown
If enhanced automatic powerdown isn’t desired, the user can
implement the standard automatic powerdown feature
(mimics the function on the ICL3221/23/43) by connecting
the INVALID
inputs, as shown in Figure 9. After 30µs of invalid receiver
levels, INVALID
forced powerdown condition. INVALID
soon as a receiver input senses a valid RS-232 level, forcing
the ICL32XX to power on. See the “INVALID
FORCEON AND FORCEOFF
operational summary. This operational mode is perfect for
handheld devices that communicate with another computer
via a detachable cable. Detaching the cable allows the
internal receiver pull-down resistors to pull the inputs to GND
output to the FORCEON and FORCEOFF
switches low and drives the ICL32XX into a
switches high as
DRIVING
” section of Table 2 for an
(an invalid RS-232 level), causing the 30µs timer to time-out
and drive the IC into powerdown. Reconnecting the cable
restores valid levels, causing the IC to power back up.
INVALID
ICL32XX
I/O
CPU
FIGURE 9. CONNECTIONS FOR AUTOMATIC POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
UART
FORCEON
FORCEOFF
Hybrid Automatic Powerdown Options
For devices which communicate only through a detachable
cable, connecting INVALID
= 0) may be a desirable configuration. While the cable is
attached INVALID
and FORCEOFF remain high, so the
enhanced automatic powerdown logic powers down the RS232 device whenever there is 30 seconds of inactivity on the
receiver and transmitter inputs. Detaching the cable allows
the receiver inputs to drop to an invalid level (GND), so
INVALID
switches low and forces the RS-232 device to
power down. The ICL32XX remains powered down until the
cable is reconnected (INVALID
to FORCEOFF (with FORCEON
= FORCEOFF = 1) and a
RECEIVER
INPUTS
TRANSMITTER
INPUTS
TRANSMITTER
OUTPUTS
INVALID
OUTPUT
READY
OUTPUT
V+
V
CC
t
INVH
t
INVL
t
t
AUTOPWDN
0
V-
FIGURE 8. ENHANCED AUTOMATIC POWERDOWN, INVALID AND READY TIMING DIAGRAMS
WU
t
AUTOPWDN
11
t
WU
INVALID
}
REGION
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
transition occurs on a receiver or transmitter input (see
Figure 7). For immediate power up when the cable is
reattached, connect FORCEON to FORCEOFF
through a
network similar to that shown in Figure 5.
Ready Output (ICL3224 and ICL3226 only)
The Ready output indicates that the ICL322X is ready to
transmit. Ready switches low whenever the device enters
powerdown, and switches back high during power-up when
V- reaches -4V or lower.
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
reduces power consumption. C
increased without increasing C
increase C
without also increasing C2, C3, and C4 to
1
maintain the proper ratios (C
, C3, and C4 can be
2
’s value, however, do not
1
to the other capacitors).
1
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
TABLE 3. REQUIRED CAPACITOR VALUES (Note 8)
(V) C1 (µF) C2, C3, C4 (µF)
V
CC
3.0 to 3.6 (3.3V ±10%) 0.1 (0.22) 0.1 (0.22)
3.15 to 3.6 (3.3V ±5%) (0.1) (0.1)
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 (0.22) 0.47 (1.0)
NOTE:
7. Parenthesized values apply only to the ICL3238
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple V
capacitor of the same value as the charge-pump capacitor C
to ground with a
CC
1
Connect the bypass capacitor as close as possible to the IC.
Transmitter Outputs when Exiting
Powerdown
Figure 10 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
Operation Down to 2.7V
ICL32XX transmitter outputs meet RS-562 levels (±3.7V), at
the full data rate, with V
as low as 2.7V. RS-562 levels
CC
typically ensure interoperability with RS-232 devices.
Mouse Driveability
The ICL3244 is specifically designed to power a serial
mouse while operating from low voltage supplies. Figure 11
shows the transmitter output voltages under increasing load
current. The on-chip switching regulator ensures the
transmitters will supply at least
±5V during worst case
conditions (15mA for paralleled V+ transmitters, 7.3mA for
single V- transmitter).
5V/DIV
2V/DIV
5V/DIV
FIGURE 10. TRANSMITTER OUTPUTS WHEN EXITING
6
5
4
3
2
1
0
-1
-2
-3
-4
.
-5
TRANSMITTER OUTPUT VOLTAGE (V)
-6
FIGURE 11. TRANSMITTER OUTPUT VOLTAGE vs LOAD
FORCEOFF
T1
VCC = +3.3V
C1 - C4 = 0.1µF
T2
READY
TIME (20µs/DIV.)
POWERDOWN
V
+
OUT
V
= 3.0V
CC
T1
V
+
OUT
T2
V
T3
CC
13579
0246810
LOAD CURRENT PER TRANSMITTER (mA)
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL V
ICL3244
-
V
OUT
V
OUT+
OUT
-
CURRENT)
High Data Rates
The ICL32XX maintain the RS-232 ±5V minimum transmitter
output voltages even at high data rates. Figure 12 details a
transmitter loopback test circuit, and Figure 13 illustrates the
loopback test result at 120kbps. For this test, all transmitters
were simultaneously driving RS-232 loads in parallel with
12
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
1000pF, at 120kbps. Figure 14 shows the loopback results
for a single transmitter driving 1000pF and an RS-232 load
at 250kbps. The static transmitters were also loaded with an
RS-232 receiver.
V
CC
0.1µF
C
1
C
2
V
CC
FIGURE 12. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV.
T1
IN
T1
OUT
+
V
+
+
C1+
C1-
C2+
C2-
T
IN
R
OUT
FORCEON
FORCEOFF
CC
ICL32XX
T
OUT
V+
V-
R
IN
5K
+
C
3
C
4
+
1000pF
5V/DIV.
T1
IN
T1
OUT
R1
OUT
VCC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV.
FIGURE 14. LOOPBACK TEST AT 250kbps
Interconnection with 3V and 5V Logic
The ICL32XX directly interface with 5V CMOS and TTL logic
families. Nevertheless, with the ICL32XX at 3.3V, and the
logic supply at 5V, AC, HC, and CD4000 outputs can drive
ICL32XX inputs, but ICL32XX outputs do not reach the
minimum V
information.
TABLE 4. LOGIC FAM ILY COMPATIBILITY WITH VARIOUS
SYSTEM
POWER-SUPPLY
VOLTAGE (V)
for these logic families. See Table 4 for more
IH
SUPPLY VOLTAGES
V
CC
SUPPLY
VOLTAGE
(V) COMPATIBILITY
R1
OUT
VCC = +3.3V
C1 - C4 = 0.1µF
5µs/DIV.
FIGURE 13. LOOPBACK TEST AT 120kbps
3.3 3.3 Compatible with all CMOS families.
5 5 Compatible with all TTL and
CMOS logic families.
5 3.3 Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
13
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Typical Performance Curves V
6
4
ICL3224, ICL3226, ICL3244
2
1 TRANSMITTER AT 250kbps
OTHER TRANSMITTERS AT 30kbps
0
-2
-4
TRANSMITTER OUTPUT VOLTAGE (V)
-6
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
= 3.3V, TA = 25°C
CC
V
+
OUT
V
-
OUT
FIGURE 15. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
25
20
-SLEW
6
V
+
V
OUT
OUT
-
4
ICL3238
2
1 TRANSMITTER AT 250kbps
OTHER TRANSMITTERS AT 30kbps
0
-2
-4
TRANSMITTER OUTPUT VOLTAGE (V)
-6
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
FIGURE 16. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
40
ICL3224
35
30
250kbps
15
+SLEW
SLEW RATE (V/µs)
10
5
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
FIGURE 17. SLEW RATE vs LOAD CAPACITANCE
35
ICL3226
30
25
20
15
10
SUPPLY CURRENT (mA)
5
250kbps
120kbps
20kbps
25
20
15
SUPPLY CURRENT (mA)
10
5
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
120kbps
20kbps
FIGURE 18. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
55
ICL3238
50
45
40
35
30
SUPPLY CURRENT (mA)
25
250kbps
120kbps
20kbps
0
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
FIGURE 19. SUPPLY CURRENT vs LOAD CAPACITANCE
20
0
FIGURE 20. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
14
1000
2000
LOAD CAPACITANCE (pF)
3000
WHEN TRANSMITTING DATA
4000
5000
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Typical Performance Curves V
45
ICL3244
40
35
30
25
20
SUPPLY CURRENT (mA)
15
10
0
FIGURE 21. SUPPLY CURRENT vs LOAD CAPACITANCE
1000
WHEN TRANSMITTING DATA
2000
LOAD CAPACITANCE (pF)
250kbps
3000
= 3.3V, TA = 25°C (Continued)
CC
120kbps
20kbps
4000
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3224: 937
ICL3226: 825
ICL3238: 1235
ICL3244: 1109
5000
3.5
3.0
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
FIGURE 22. SUPPLY CURRENT vs SUPPLY VOLTAGE
NO LOAD
ALL OUTPUTS STATIC
PROCESS:
Si Gate CMOS
15
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Small Outline Plastic Packages (SSOP)
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
GAUGE
PLANE
0.25
0.010
L
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
M
A1
0.10(0.004)
A2
C
M16.209 (JEDEC MO-150-AC ISSUE B)
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.233 0.255 5.90 6.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N16 167
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 3 6/05
16
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Shrink Small Outline Plastic Packages (SSOP)
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) B
H
α
e
B
0.25(0.010) C AMB
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
M
A1
0.10(0.004)
S
GAUGE
PLANE
M
0.25
0.010
A2
M
L
M20.209 (JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.068 0.078 1.73 1.99
A1 0.002 0.008’ 0.05 0.21
A2 0.066 0.070’ 1.68 1.78
B 0.010’ 0.015 0.25 0.38 9
C 0.004 0.008 0.09 0.20’
D 0.278 0.289 7.07 7.33 3
E 0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
C
H 0.301 0.311 7.65 7.90’
L 0.025 0.037 0.63 0.95 6
N20 207
α
0 deg. 8 deg. 0 deg. 8 deg.
NOTESMIN MAX MIN MAX
Rev. 3 11/02
17
FN4876.10
March 1, 2006
ICL3224, ICL3226, ICL3238, ICL3244
www.BDTIC.com/Intersil
Shrink Small Outline Plastic Packages (SSOP)
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
GAUGE
PLANE
0.25
0.010
L
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M
A1
0.10(0.004)
A2
C
M28.209 (JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.390 0.413 9.90 10.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N28 287
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 2 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN4876.10
March 1, 2006
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