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ICL3222
DATA SHEET
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Datasheet
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intersil ICL3221, ICL3222, ICL3223, ICL3232, ICL3241 DATA SHEET

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ICL3221, ICL3222, ICL3223,
ICL3232, ICL3241, ICL3243
Data Sheet March 1, 2006
One Microamp Supply-Current, +3V to +5.5V, 250kbps, RS-232 Transmitters/Receivers
The Intersil ICL32XX devices are 3.0V to 5.5V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at V applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with manual and automatic powerdown functions (except for the ICL3232), reduce the standby supply current to a 1µA trickle. Small footprint packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions. This family is fully compatible with 3.3V only systems, mixed 3.3V and 5.0V systems, and 5.0V only systems.
The ICL324X are 3-driver, 5-receiver devices that provide a complete serial port suitable for laptop or notebook computers. Both devices also include noninverting always­active receivers for “wake-up” capability.
The ICL3221, ICL3223 and ICL3243, feature an automatic powerdown function which powers down the on-chip power-supply and driver circuits. This occurs when an attached peripheral device is shut off or the RS-232 cable is removed, conserving system power automatically without changes to the hardware or operating system. These devices power up again when a valid RS-232 voltage is applied to any receiver input.
Table 1 summarizes the features of the devices represented by this data sheet, while Application Note AN9863 summarizes the features of each device comprising the ICL32XX 3V family.
= 3.0V. Targeted
CC
FN4805.21
Features
• Pb-Free Plus Anneal Available as an Option (RoHS Compliant) (See Ordering Info)
• 15kV ESD Protected (Human Body Model)
• Drop in Replacements for MAX3221, MAX3222, MAX3223, MAX3232, MAX3241, MAX3243, SP3243
• ICL3221 is Low Power, Pin Compatible Upgrade for 5V MAX221
• ICL3222 is Low Power, Pin Compatible Upgrade for 5V MAX242, and SP312A
• ICL3232 is Low Power Upgrade for HIN232/ICL232 and Pin Compatible Competitor Devices
• RS-232 Compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Manual and Automatic Powerdown Features (Except ICL3232)
• Guaranteed Mouse Driveability (ICL324X Only)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 6V/µs
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
TABLE 1. SUMMARY OF FEATURES
NO. OF
PART NUMBER
NO. OF
ICL3221 1 1 0 250 Yes No Yes Yes
ICL3222 2 2 0 250 Yes No Yes No
ICL3223 2 2 0 250 Yes No Yes Yes
ICL3232 2 2 0 250 No No No No
ICL3241 3 5 2 250 Yes No Yes No
ICL3243 3 5 1 250 No No Yes Yes
Tx.
NO. OF
Rx.
1
MONITOR Rx.
(R
)
OUTB
DATA RATE
(kbps)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
Rx. ENABLE FUNCTION?
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
MANUAL
READY
OUTPUT?
Copyright Intersil Americas Inc. 1999-2006. All Rights Reserved
POWER-
DOWN?
AUTOMATIC
POWERDOWN
FUNCTION?
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Ordering Information
PAR T N U MBER (NOTE 1) PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
ICL3221CA ICL3221CA 0 to 70 16 Ld SSOP M16.209
ICL3221CAZ (Note 2) ICL3221CAZ 0 to 70 16 Ld SSOP (Pb-free) M16.209
ICL3221CV ICL3221CV 0 to 70 16 Ld TSSOP M16.173
ICL3221CVZ (Note 2) 3221CVZ 0 to 70 16 Ld TSSOP (Pb-free) M16.173
ICL3221IA ICL3221IA -40 to 85 16 Ld SSOP M16.209
ICL3221IAZ (Note 2) ICL3221IAZ -40 to 85 16 Ld SSOP (Pb-free) M16.209
ICL3222CA ICL3222CA 0 to 70 20 Ld SSOP M20.209
ICL3222CAZ (Note 2) ICL3222CAZ 0 to 70 20 Ld SSOP (Pb-free) M20.209
ICL3222CB ICL3222CB 0 to 70 18 Ld SOIC M18.3
ICL3222CBZ (Note 2) 3222CBZ 0 to 70 18 Ld SOIC (Pb-free) M18.3
ICL3222CP ICL3222CP 0 to 70 18 Ld PDIP E18.3
ICL3222CPZ (Note 2) ICL3222CPZ 0 to 70 18 Ld PDIP* (Pb-free) E18.3
ICL3222CV ICL3222CV 0 to 70 20 Ld TSSOP M20.173
ICL3222CVZ (Note 2) ICL3222CVZ 0 to 70 20 Ld TSSOP (Pb-free) M20.173
ICL3222IA ICL3222IA -40 to 85 20 Ld SSOP M20.209
ICL3222IAZ (Note 2) ICL3222IAZ -40 to 85 20 Ld SSOP (Pb-free) M20.209
ICL3222IB ICL3222IB -40 to 85 18 Ld SOIC M18.3
ICL3222IV ICL3222IV -40 to 85 20 Ld TSSOP M20.173
ICL3222IVZ (Note 2) ICL3222IVZ -40 to 85 20 Ld TSSOP (Pb-free) M20.173
ICL3223CA ICL3223CA 0 to 70 20 Ld SSOP M20.209
ICL3223CAZ (Note 2) ICL3223CAZ 0 to 70 20 Ld SSOP (Pb-free) M20.209
ICL3223CP ICL3223CP 0 to 70 20 Ld PDIP E20.3
ICL3223CPZ (Note 2) ICL3223CPZ 0 to 70 20 Ld PDIP* (Pb-free) E20.3
ICL3223CV ICL3223CV 0 to 70 20 Ld TSSOP M20.173
ICL3223IA ICL3223IA -40 to 85 20 Ld SSOP M20.209
ICL3223IAZ (Note 2) ICL3223IAZ -40 to 85 20 Ld SSOP (Pb-free) M20.209
ICL3223IV ICL3223IV -40 to 85 20 Ld TSSOP M20.173
ICL3223IVZ (Note 2) ICL3223IVZ -40 to 85 20 Ld TSSOP (Pb-free) M20.173
ICL3232CA ICL3232CA 0 to 70 16 Ld SSOP M16.209
ICL3232CAZ (Note 2) 3232CAZ 0 to 70 16 Ld SSOP (Pb-free) M16.209
ICL3232CB ICL3232CB 0 to 70 16 Ld SOIC M16.3
ICL3232CBZ (Note 2) 3232CBZ 0 to 70 16 Ld SOIC (Pb-free) M16.3
ICL3232CBN 3232CBN 0 to 70 16 Ld SOIC (N) M16.15
ICL3232CBNZ (Note 2) 3232CBNZ 0 to 70 16 Ld SOIC (N) (Pb-free) M16.15
ICL3232CP ICL3232CP 0 to 70 16 Ld PDIP E16.3
ICL3232CPZ (Note 2) ICL3232CPZ 0 to 70 16 Ld PDIP* (Pb-free) E16.3
ICL3232CV ICL3232CV 0 to 70 16 Ld TSSOP M16.173
2
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Ordering Information (Continued)
PAR T N U MBER (NOTE 1) PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
ICL3232CVZ (Note 2) 3232CVZ 0 to 70 16 Ld TSSOP (Pb-free) M16.173
ICL3232IA ICL3232IA -40 to 85 16 Ld SSOP M16.209
ICL3232IAZ (Note 2) 3232IAZ -40 to 85 16 Ld SSOP (Pb-free) M16.209
ICL3232IB ICL3232IB -40 to 85 16 Ld SOIC M16.3
ICL3232IBZ (Note 2) 3232IBZ -40 to 85 16 Ld SOIC (Pb-free) M16.3
ICL3232IBN 3232IBN -40 to 85 16 Ld SOIC (N) M16.15
ICL3232IBNZ (Note 2) 3232IBNZ -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ICL3232IV ICL3232IV -40 to 85 16 Ld TSSOP M16.173
ICL3232IVZ (Note 2) 3232IVZ -40 to 85 16 Ld TSSOP (Pb-free) M16.173
ICL3241CA ICL3241CA 0 to 70 28 Ld SSOP M28.209
ICL3241CAZ (Note 2) ICL3241CAZ 0 to 70 28 Ld SSOP (Pb-free) M28.209
ICL3241CB ICL3241CB 0 to 70 28 Ld SOIC M28.3
ICL3241CBZ (Note 2) ICL3241CBZ 0 to 70 28 Ld SOIC (Pb-free) M28.3
ICL3241CV ICL3241CV 0 to 70 28 Ld TSSOP M28.173
ICL3241CVZ (Note 2) ICL3241CVZ 0 to 70 28 Ld TSSOP (Pb-free) M28.173
ICL3241IA ICL3241IA -40 to 85 28 Ld SSOP M28.209
ICL3241IAZ (Note 2) ICL3241IAZ -40 to 85 28 Ld SSOP (Pb-free) M28.209
ICL3241IB ICL3241IB -40 to 85 28 Ld SOIC M28.3
ICL3241IBZ (Note 2) ICL3241IBZ -40 to 85 28 Ld SOIC (Pb-free) M28.3
ICL3241IV ICL3241IV -40 to 85 28 Ld TSSOP M28.173
ICL3241IVZ (Note 2) ICL3241IVZ -40 to 85 28 Ld TSSOP (Pb-free) M28.173
ICL3243CA ICL3243CA 0 to 70 28 Ld SSOP M28.209
ICL3243CAZ (Note 2) ICL3243CAZ 0 to 70 28 Ld SSOP (Pb-free) M28.209
ICL3243CB ICL3243CB 0 to 70 28 Ld SOIC M28.3
ICL3243CBZ (Note 2) ICL3243CBZ 0 to 70 28 Ld SOIC (Pb-free) M28.3
ICL3243CV ICL3243CV 0 to 70 28 Ld TSSOP M28.173
ICL3243CVZ (Note 2) ICL3243CVZ 0 to 70 28 Ld TSSOP (Pb-free) M28.173
ICL3243IA ICL3243IA -40 to 85 28 Ld SSOP M28.209
ICL3243IAZ (Note 2) ICL3243IAZ -40 to 85 28 Ld SSOP (Pb-free) M28.209
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTES:
1. Most surface mount devices are available on tape and reel; add “-T” to suffix.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3
FN4805.21
March 1, 2006
Pinouts
www.BDTIC.com/Intersil
ICL3221 (SSOP, TSSOP)
TOP VIEW
EN
1
C1+
2
3
V+
4
C1-
5
C2+
C2-
6
V-
7
R1
8
IN
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
ICL3222 (PDIP, SOIC)
TOP VIEW
EN
T2
C1+
C2+
OUT
R2
V+
C1-
C2-
1
2
3
4
5
6
V-
7
8
9
IN
FORCEOFF
16
V
15
CC
GND
14
T1
13
FORCEON
12
T1
11
INVALID
10
R1
9
OUT
IN
OUT
18
SHDN
V
17
CC
GND
16
15
T1
OUT
R1
14
IN
R1
13
OUT
T1
12
IN
T2
11
IN
10
R2
OUT
ICL3222 (SSOP, TSSOP)
TOP VIEW
SHDN
20
V
19
CC
GND
18
T1
17
OUT
R1
16
IN
R1
15
OUT
NC
14
T1
13
IN
12
T2
IN
NC
11
R2
T2
C1+
C2+
OUT
R2
OUT
EN
V+
C1-
C2-
1
2
3
4
5
6
V-
7
8
9
IN
10
ICL3232 (PDIP, SOIC, SSOP, TSSOP)
TOP VIEW
V
16
CC
GND
15
T1
14
OUT
R1
13
IN
R1
12
OUT
T1
11
IN
T2
10
IN
R2
9
OUT
T2
C1+
C1-
C2+
OUT
R2
V+
C2-
1
2
3
4
5
6
V-
7
8
IN
ICL3223 (PDIP, SSOP, TSSOP)
TOP VIEW
EN
1
C1+
2
3
V+
4
C1-
5
C2+
C2-
6
V-
7
T2
8
OUT
R2
9
IN
10
R2
OUT
ICL3241 (SOIC, SSOP, TSSOP)
TOP VIEW
C2+
1
C2-
2
3
V-
R1
4
IN
R2
5
IN
R3
6
IN
R4
7
IN
R5
8
IN
T1
9
OUT
10
T2
OUT
T3
11
OUT
T3
12
IN
T2
13
IN
T1
14
IN
FORCEOFF
20
V
19
CC
GND
18
T1
17
R1
16
R1
15
FORCEON
14
T1
13
12
T2
INVALID
11
C1+
28
V+
27
V
26
GND
25
C1-
24
EN
23
SHDN
22
R1
21
20
R2
R1
19
R2
18
R3
17
16
R4
R5
15
OUT
IN
OUT
IN
IN
CC
OUTB
OUTB
OUT
OUT
OUT
OUT
OUT
4
FN4805.21
March 1, 2006
Pinouts (Continued)
www.BDTIC.com/Intersil
Pin Descriptions
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
ICL3243 (SOIC, SSOP, TSSOP)
TOP VIEW
28
C1+
V+
27
V
26
CC
GND
25
C1-
24
FORCEON
23
FORCEOFF
22
INVALID
21
20
R2
R1
19
R2
18
R3
17
16
R4
R5
15
OUTB
OUT
OUT
OUT
OUT
OUT
T1
T2
T3
C2+
R1
R2
R3
R4
R5
OUT
OUT
OUT
T3
T2
T1
C2-
V-
1
2
3
4
IN
5
IN
6
IN
7
IN
8
IN
9
10
11
12
IN
13
IN
14
IN
PIN FUNCTION
V
CC
System power supply input (3.0V to 5.5V).
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
T
T
OUT
R
R
OUT
R
OUTB
INVALID
EN
SHDN
TTL/CMOS compatible transmitter Inputs.
IN
RS-232 level (nominally ±5.5V) transmitter outputs.
RS-232 compatible receiver inputs.
IN
TTL/CMOS level receiver outputs.
TTL/CMOS level, noninverting, always enabled receiver outputs.
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
Active low receiver enable control; doesn’t disable R
OUTB
outputs.
Active low input to shut down transmitters and on-board power supply, to place device in low power mode.
FORCEOFF
Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (See Table 2).
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF
5
must be high).
March 1, 2006
FN4805.21
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Typical Operating Circuits
ICL3221 ICL3222
C3 (OPTIONAL CONNECTION, NOTE)
+3.3V
TTL/CMOS
R1
LOGIC LEVELS
+
C
0.1µF
C
0.1µF
T1
OUT
0.1µF
2
C1+
1
+
4
C1-
5
2
C2+
+
6
C2-
11
IN
1
EN
12
FORCEON
15
V
CC
T
1
R
1
FORCEOFF
GND
14
NOTE: The negative terminal of C3 can be connected to either V
or GND
CC
V+
V-
5kΩ
INVALID
3
7
13
89
16
10
+
C
+
0.1µF
C
0.1µF
+
3
4
T1
OUT
R1
IN
V
CC
TO POWER CONTROL LOGIC
RS-232
LEVELS
TTL/CMOS
LOGIC LEVELS
+3.3V
0.1µF
0.1µF
R1
R2
C
C
T1
T2
OUT
OUT
C3 (OPTIONAL CONNECTION, NOTE)
+
0.1µF
2
1
2
IN
IN
C1+
+
4
C1-
5
C2+
+
6
C2-
12
11
13
10
1
EN
V
CC
R
1
R
2
GND
17
T
1
T
2
5kΩ
5kΩ
SHDN
16
V+
V-
+
3
C
3
+
0.1µF
7
C
4
0.1µF
+
15
T1
OUT
8
T2
OUT
14
R1
IN
9
R2
IN
18
V
CC
RS-232
LEVELS
NOTE: The negative terminal of C3 can be connected to either V
CC
or GND
ICL3223 ICL3232
+3.3V
TTL/CMOS
LOGIC LEVELS
C
0.1µF
C
0.1µF
T1
T2
R1
R2
1
2
OUT
OUT
+
0.1µF
2
C1+
+
4
C1-
5
C2+
+
6
C2-
13
IN
12
IN
15
1
EN
14
FORCEON
19
V
CC
T
1
T
2
R
1
R
2
FORCEOFF
GND
18
V+
V-
5kΩ
5kΩ
INVALID
3
C
3
+
0.1µF
7
C
4
0.1µF
+
17
T1
8
T2
16
R1
910
R2
20
V
CC
11
TO POWER CONTROL LOGIC
OUT
OUT
IN
IN
RS-232
LEVELS
+3.3V
TTL/CMOS
LOGIC LEVELS
C
0.1µF
C
0.1µF
R1
R2
1
2
T1
T2
OUT
OUT
+
0.1µF
1
C1+
+
3
C1-
4
C2+
+
5
C2-
11
IN
10
IN
12
9
C3 (OPTIONAL CONNECTION, NOTE)
V
CC
R
R
2
GND
16
T
1
T
2
5kΩ
1
5kΩ
15
V+
V-
+
2
C
3
+
0.1µF
6
C
4
0.1µF
+
14
T1
OUT
7
T2
OUT
13
R1
IN
8
R2
IN
RS-232
LEVELS
NOTE: The negative terminal of C3 can be connected to either V
CC
or GND
6
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Typical Operating Circuits (Continued)
ICL3241 ICL3243
TTL/CMOS
LOGIC LEVELS
+3.3V
0.1µF
0.1µF
R1
R2
R1
R2
R3
R4
R5
V
+
0.1µF
28
T1
T2
T3
C
1
C
2
IN
IN
IN
C1+
+
24
C1-
1
C2+
+
2
C2-
V
14
13
12 11
21
OUTB
20
OUTB
19
OUT
R
OUT
R
OUT
R
OUT
R
CC
OUT
23
EN
22
SHDN
R
GND
CC
2
3
4
5
+3.3V
26
27
C
3
V+
V-
T
1
T
2
T
3
+
0.1µF
3
C
4
0.1µF
+
9
T1
OUT
10
T2
OUT
RS-232
LEVELS
T3
OUT
C
0.1µF
C
0.1µF
T1
T2
T3
+
0.1µF
28
1
2
C1+
+
24
C1-
1
C2+
+
2
C2-
14
IN
13
IN
12 11
IN
26
V
CC
T
1
T
2
T
3
V+
V-
27
C
3
+
0.1µF
3
C
4
0.1µF
+
9
T1
OUT
10
T2
T3
OUT
OUT
RS-232
LEVELS
20
R2
OUTB
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
4
R1
IN
518
R2
IN
617
R3
IN
RS-232
LEVELS
716
R4
IN
815
R5
IN
4
R1
IN
5kΩ
1
518
R2
IN
TTL/CMOS
LOGIC LEVELS
R1
R2
5kΩ
5kΩ
617
R3
IN
RS-232
LEVELS
716
R4
IN
R3
R4
OUT
OUT
OUT
OUT
19
R
1
R
2
R
3
R
4
5kΩ
815
R5
5kΩ
IN
25
R5
OUT
23
FORCEON
22
V
CC
21
FORCEOFF
INVALID
TO POWER
R
5
GND
25
CONTROL LOGIC
7
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . -0.3V to 6V
T
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
R
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
T
OUT
, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
R
OUT
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Operating Conditions
Temperature Range
ICL32XXCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. θ
JA
Thermal Resistance (Typical, Note 3)
16 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 90
18 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 80
20 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 77
16 Ld Wide SOIC Package . . . . . . . . . . . . . . . . . . . 100
16 Ld Narrow SOIC Package. . . . . . . . . . . . . . . . . . 115
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 135
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 122
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 145
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 140
28 Ld SSOP and TSSOP Packages . . . . . . . . . . . . 100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC, SSOP, TSSOP - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
θ
JA
(°C/W)
Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C
TEMP
PARAMETER TEST CONDITIONS
DC CHARACTERISTICS
Supply Current, Automatic Powerdown
Supply Current, Powerdown FORCEOFF
Supply Current, Automatic Powerdown Disabled
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low T
Input Logic Threshold High T
Input Leakage Current T
Output Leakage Current (Except ICL3232)
Output Voltage Low I
Output Voltage High I
AUTOMATIC POWERDOWN (ICL3221, ICL3223, ICL3243 Only, FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to Enable Transmitters
Receiver Input Thresholds to Disable Transmitters
INVALID
INVALID
Output Voltage Low I
Output Voltage High I
Open, FORCEON = GND, FORCEOFF =V
All R
IN
(ICL3221, ICL3223, ICL3243 Only)
= SHDN = GND (Except ICL3232) 25 - 1.0 10 µA
All Outputs Unloaded, FORCEON = FORCEOFF
=V
SHDN
IN
IN
SHDN
IN
FORCEOFF
OUT
OUT
ICL32XX Powers Up (See Figure 6) Full -2.7 - 2.7 V
ICL32XX Powers Down (See Figure 6) Full -0.3 - 0.3 V
OUT
OUT
CC
, FORCEON, FORCEOFF, EN, SHDN Full - - 0.8 V
, FORCEON, FORCEOFF, EN,
, FORCEON, FORCEOFF, EN, SHDN Full - ±0.01 ±1.0 µA
=GND or EN=V
= 1.6mA Full - - 0.4 V
= -1.0mA Full V
= 1.6mA Full - - 0.4 V
= -1.0mA Full VCC-0.6 - - V
VCC = 3.15V, ICL3221-32
=
VCC = 3.0V, ICL3241-43 25 - 0.3 1.0 mA
VCC = 3.3V Full 2.0 - - V
= 5.0V Full 2.4 - - V
V
CC
CC
CC
(°C) MIN TYP MAX UNITS
25 - 1.0 10 µA
25 - 0.3 1.0 mA
Full - ±0.05 ±10 µA
-0.6 V
CC
-0.1 - V
CC
8
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C (Continued)
TEMP
PARAMETER TEST CONDITIONS
Receiver Threshold to Transmitters Enabled Delay (t
Receiver Positive or Negative Threshold to INVALID
)
(t
INVH
Receiver Positive or Negative Threshold to INVALID (t
)
INVL
RECEIVER INPUTS
Input Voltage Range Full -25 - 25 V
Input Threshold Low V
Input Threshold High V
Input Hysteresis 25 - 0.3 - V
Input Resistance 25 3 5 7 kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Output Resistance V
Output Short-Circuit Current Full - ±35 ±60 mA
Output Leakage Current V
MOUSE DRIVEABILITY (ICL324X Only)
Transmitter Output Voltage (See Figure 9)
TIMING CHARACTERISTICS
Maximum Data Rate R
Receiver Propagation Delay Receiver Input to Receiver
Receiver Output Enable Time Normal Operation (Except ICL3232) 25 - 200 - ns
Receiver Output Disable Time Normal Operation (Except ICL3232) 25 - 200 - ns
Transmitter Skew t
Receiver Skew t
Transition Region Slew Rate V
ESD PERFORMANCE
RS-232 Pins (T
All Other Pins Human Body Model ICL3221 - ICL3243 25 - ±2-kV
High Delay
Low Delay
, RIN) Human Body Model ICL3221 - ICL3243 25 - ±15 - kV
OUT
)
WU
= 3.3V 25 0.6 1.2 - V
CC
= 5.0V 25 0.8 1.5 - V
V
CC
= 3.3V 25 - 1.5 2.4 V
CC
= 5.0V 25 - 1.8 2.4 V
V
CC
= V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
CC
= ±12V, VCC= 0V or 3V to 5.5V
OUT
Automatic Powerdown or FORCEOFF
T1
=T2IN= GND, T3IN=VCC, T3
IN
GND, T1
=3kΩ, CL= 1000pF, One Transmitter Switching Full 250 500 - kbps
L
Output, C
PHL
PHL
CC
R
=3kΩ to 7kΩ,
L
Measured From 3V to -3V or -3V to 3V
IEC61000-4-2 Contact Discharge ICL3221 - ICL3243 25 - ±8-kV
IEC61000-4-2 Air Gap Discharge ICL3221 - ICL3232 25 - ±8-kV
OUT
L
- t
PLH
- t
PLH
=3.3V,
and T2
= 150pF
Loaded with 2.5mA Each
OUT
= SHDN =GND
Loaded with 3kΩ to
OUT
t
PHL
t
PLH
= 200pF to 2500pF 25 4 8.0 30 V/µs
C
L
= 200pF to 1000pF 25 6 - 30 V/µs
C
L
ICL3241 - ICL3243 25 - ±6-kV
(°C) MIN TYP MAX UNITS
25 - 100 - µs
25 - 1 - µs
25 - 30 - µs
Full - - ±25 µA
Full ±5- -V
25 - 0.3 - µs
25 - 0.3 - µs
Full - 200 1000 ns
Full - 100 500 ns
9
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Detailed Description
ICL32XX interface ICs operate from a single +3V to +5.5V supply, guarantee a 250kbps minimum data rate, require only four small external 0.1µF capacitors, feature low power consumption, and meet all ElA RS-232C and V.28 specifications. The circuit is divided into three sections: charge pump, transmitters and receivers.
Charge-Pump
Intersil’s new ICL32XX family utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate ±5.5V transmitter supplies from a V low as 3.0V. This allows these devices to maintain RS-232 compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1µF capacitors for the voltage doubler and inverter functions at V the Capacitor Selection section, and Table 3 for capacitor recommendations for other operating conditions. The charge pumps operate discontinuously (i.e., they turn off as soon as the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232 output levels. Coupled with the on-chip ±5.5V supplies, these transmitters deliver true RS-232 levels over a wide range of single supply system voltages.
Except for the ICL3232, all transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (See Table 2). These outputs may be driven to ±12V when disabled.
All devices guarantee a 250kbps data rate for full load conditions (3kΩ and 1000pF), V
≥ 3.0V, with one
CC
transmitter operating at full speed. Under more typical conditions of V
≥ 3.3V, RL=3kΩ, and CL= 250pF, one
CC
transmitter easily operates at 900kbps.
Transmitter inputs float if left unconnected, and may cause I
increases. Connect unused inputs to GND for the best
CC
performance.
Receivers
All the ICL32XX devices contain standard inverting receivers that three-state (except for the ICL3232) via the EN FORCEOFF products include noninverting (monitor) receivers (denoted by the R state of any control lines. All the receivers convert RS-232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3kΩ to 7kΩ input impedance (See Figure 1) even if the power is off (V receivers’ Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions.
control lines. Additionally, the two ICL324X
label) that are always active, regardless of the
OUTB
CC
= 3.3V. See
CC
= 0V). The
CC
supply as
or
The ICL3221/22/23/41 inverting receivers disable only when EN
is driven high. ICL3243 receivers disable during forced (manual) powerdown, but not during automatic powerdown (See Table 2).
ICL324X monitor receivers remain active even during manual powerdown and forced receiver disable, making them extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral’s protection diodes (See Figures 2 and 3). This renders them useless for wake up functions, but the corresponding monitor receiver can be dedicated to this task as shown in Figure 3.
V
CC
R
XIN
-25V ≤ V
FIGURE 1. INVERTING RECEIVER CONNECTIONS
RIN
≤ +25V
GND
5kΩ
R
GND ≤ V
XOUT
ROUT
≤ V
CC
Low Power Operation
These 3V devices require a nominal supply current of
0.3mA, even at V
= 5.5V, during normal operation (not in
CC
powerdown mode). This is considerably less than the 5mA to 11mA current required by comparable 5V RS-232 devices, allowing users to reduce system power simply by switching to this new family.
Pin Compatible Replacements For 5V Devices
The ICL3221/22/32 are pin compatible with existing 5V RS-232 transceivers - see the Features section on the front page for details.
This pin compatibility coupled with the low Icc and wide operating supply range, make the ICL32XX potential lower power, higher performance drop-in replacements for existing 5V applications. As long as the ±5V RS-232 output swings are acceptable, and transmitter input pull-up resistors aren’t required, the ICL32XX should work in most 5V applications.
When replacing a device in an existing 5V application, it is acceptable to terminate C Operating Circuit. Nevertheless, terminate C possible, as slightly better performance results from this configuration.
to VCC as shown on the Typ ica l
3
to GND if
3
Powerdown Functionality (Except ICL3232)
The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to 1µA, because the on-chip charge pump turns off (V+ collapses to V and the transmitter outputs three-state. Inverting receiver outputs may or may not disable in powerdown; refer to Table 2 for details. This micro-power mode makes these devices ideal for battery powered and portable applications.
, V- collapses to GND),
CC
10
FN4805.21
March 1, 2006
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Software Controlled (Manual) Powerdown
Most devices in the ICL32XX family provide pins that allow the user to force the IC into the low power, standby state.
On the ICL3222 and ICL3241, the powerdown control is via a simple shutdown (SHDN normal operation, while driving it low forces the IC into its powerdown state. Connect SHDN function isn’t needed. Note that all the receiver outputs remain enabled during shutdown (See Table 2). For the lowest power consumption during powerdown, the receivers should also be disabled by driving the EN next section, and Figures 2 and 3).
) pin. Driving this pin high enables
to VCC if the powerdown
input high (See
The ICL3221, ICL3223, and ICL3243 utilize a two pin approach where the FORCEON and FORCEOFF determine the IC’s mode. For always enabled operation, FORCEON and FORCEOFF
are both strapped high. To switch between active and powerdown modes, under logic or software control, only the FORCEOFF
input need be driven. The FORCEON state isn’t critical, as FORCEOFF dominates over FORCEON. Nevertheless, if strictly manual control over powerdown is desired, the user must strap FORCEON high to disable the automatic powerdown circuitry. ICL3243 inverting (standard) receiver outputs also disable when the device is in manual powerdown, thereby eliminating the possible current path through a shutdown peripheral’s input protection diode (See Figures 2 and 3).
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE
RS-232
SIGNAL
PRESENT
AT
RECEIVER
INPUT?
ICL3222, ICL3241
N.A. L N.A. L High-Z Active Active N.A. Manual Powerdown
N.A. L N.A. H High-Z High-Z Active N.A. Manual Powerdown w/ Rcvr. Disabled
N.A. H N.A. L Active Active Active N.A. Normal Operation
N.A. H N.A. H Active High-Z Active N.A. Normal Operation w/Rcvr. Disabled
ICL3221, ICL3223
No H H L Active Active N.A. L Normal Operation
No H H H Active High-Z N.A. L
Yes H L L Active Active N.A. H Normal Operation
Yes H L H Active High-Z N.A. H
No H L L High-Z Active N.A. L Powerdown Due to Auto Powerdown
No H L H High-Z High-Z N.A. L
Yes L X L High-Z Active N.A. H Manual Powerdown
Yes L X H High-Z High-Z N.A. H Manual Powerdown w/Rcvr. Disabled
No L X L High-Z Active N.A. L Manual Powerdown
No L X H High-Z High-Z N.A. L Manual Powerdown w/Rcvr. Disabled
ICL3243
No H H N.A. Active Active Active L Normal Operation
Yes H L N.A. Active Active Active H Normal Operation
No H L N.A. High-Z Active Active L Powerdown Due to Auto Powerdown
Yes L X N.A. High-Z High-Z Active H Manual Powerdown
No L X N.A. High-Z High-Z Active L Manual Powerdown
NOTE:
4. Applies only to the ICL3241 and ICL3243.
FORCEOFF
OR SHDN
INPUT
FORCEON
INPUTENINPUT
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
(NOTE 4)
R
OUTB
OUTPUTS
INVALID
OUTPUT MODE OF OPERATION
(Auto Powerdown Disabled)
(Auto Powerdown Enabled)
Logic
(Auto Powerdown Disabled)
(Auto Powerdown Enabled)
Logic
inputs
11
FN4805.21
March 1, 2006
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The INVALID output always indicates whether or not a valid RS-232 signal is present at any of the receiver inputs (See Table 2), giving the user an easy way to determine when the interface block should power down. In the case of a disconnected interface cable where all the receiver inputs are floating (but pulled to GND by the internal receiver pull down resistors), the INVALID
logic detects the invalid levels and drives the output low. The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, INVALID logic wakes up the interface block. INVALID
switches high, and the power management
can also be used to indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to GND (as in the case of a powered down driver). Connecting FORCEOFF
and FORCEON together disables the automatic powerdown feature, enabling them to function as a manual SHUTDOWN
V
CC
POWERED
DOWN
UART
GND
input (See Figure 4).
V
CC
V
OUT = VCC
Rx
Tx
= GND
SHDN
V
CC
CURRENT FLOW
OLD
RS-232 CHIP
FORCEOFF
LOGIC
CPU
PWR MGT
FORCEON
INVALID
ICL3221/23/43
I/O
UART
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE PRESENT
With any of the above control schemes, the time required to exit powerdown, and resume transmission is only 100µs. A mouse, or other application, may need more time to wake up from shutdown. If automatic powerdown is being utilized, the RS-232 device will reenter powerdown if valid receiver levels aren’t reestablished within 30µs of the ICL32XX powering up. Figure 5 illustrates a circuit that keeps the ICL32XX from initiating automatic powerdown for 100ms after powering up. This gives the slow-to-wake peripheral circuit time to reestablish valid RS-232 output levels.
POWER
MANAGEMENT
UNIT
MASTER POWERDOWN LINE
0.1µF 1MΩ
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
V
CC
TRANSITION
DETECTOR
WAKE-UP
V
CC
POWERED
DOWN
UART
TO
LOGIC
R
X
T
X
FORCEOFF = GND OR SHDN
R2
OUTB
V
HI-Z
OUT =
R2
OUT
T1
IN
= GND, EN = V
CC
ICL324X
R2
T1
IN
OUT
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
FORCEOFF
ICL3221/23/43
FORCEON
FIGURE 5. CIRCUIT TO PREVENT AUTO POWERDOWN FOR
100ms AFTER FORCED POWERUP
Automatic Powerdown (ICL3221/23/43 Only)
Even greater power savings is available by using the devices which feature an automatic powerdown function. When no valid RS-232 voltages (See Figure 6) are sensed on any receiver input for 30µs, the charge pump and transmitters powerdown, thereby reducing supply current to 1µA. Invalid receiver levels occur whenever the driving peripheral’s outputs are shut off (powered down) or when the RS-232 interface cable is disconnected. The ICL32XX powers back up whenever it detects a valid RS-232 voltage level on any receiver input. This automatic powerdown feature provides additional system power savings without changes to the existing operating system.
12
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
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2.7V
0.3V
-0.3V
-2.7V
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
VALID RS-232 LEVEL - ICL32XX IS ACTIVE
INDETERMINATE - POWERDOWN MAY OR
INVALID LEVEL - POWERDOWN OCCURS AFTER 30ms
INDETERMINATE - POWERDOWN MAY OR
VALID RS-232 LEVEL - ICL32XX IS ACTIVE
MAY NOT OCCUR
MAY NOT OCCUR
Automatic powerdown operates when the FORCEON input is low, and the FORCEOFF
input is high. Tying FORCEON high disables automatic powerdown, but manual powerdown is always available via the overriding FORCEOFF
input.
Table 2 summarizes the automatic powerdown functionality.
Devices with the automatic powerdown feature include an INVALID
output signal, which switches low to indicate that invalid levels have persisted on all of the receiver inputs for more than 30µs (See Figure 7). INVALID
switches high 1µs after detecting a valid RS-232 level on a receiver input. INVALID
operates in all modes (forced or automatic powerdown, or forced on), so it is also useful for systems employing manual powerdown circuitry. When automatic powerdown is utilized, INVALID
= 0 indicates that the
ICL32XX is in powerdown mode.
RECEIVER
INPUTS
TRANSMITTER
OUTPUTS
INVALID OUTPUT
V
V
CC
CC
0
V+
0
t
INVL
AUTOPWDN
t
INVH
INVALID
}
REGION
PWR UP
(standard) receiver outputs placing them in a high impedance state. This is useful to eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of a powered down (V
CC
= GND) peripheral (See Figure 2). The enable input has no effect on transmitter nor monitor (R
OUTB
) outputs.
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V operation. For other supply voltages refer to Table 3 for capacitor values. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C increased without increasing C increase C
without also increasing C2, C3, and C4 to
1
maintain the proper ratios (C
, C3, and C4 can be
2
’s value, however, do not
1
to the other capacitors).
1
When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-.
TABLE 3. REQUIRED CAPACITOR VALUES
V
CC
(V)
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 0.47
C
(µF)
1
C
2
, C3, C
(µF)
4
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple V capacitor of the same value as the charge-pump capacitor C
to ground with a
CC
1
Connect the bypass capacitor as close as possible to the IC.
Operation Down to 2.7V
ICL32XX transmitter outputs meet RS-562 levels (±3.7V), at full data rate, with V typically ensure interoperability with RS-232 devices.
as low as 2.7V. RS-562 levels
CC
.
V-
FIGURE 7. AUTOMATIC POWERDOWN AND INVALID
TIMING DIAGRAMS
Transmitter Outputs when Exiting Powerdown
Figure 8 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two
The time to recover from automatic powerdown mode is typically 100µs.
transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note
Receiver ENABLE Control (ICL3221/22/23/41 Only)
Several devices also feature an EN input to control the receiver outputs. Driving EN
high disables all the inverting
that the transmitters enable only when the magnitude of the supplies exceed approximately 3V.
13
FN4805.21
March 1, 2006
5V/DIV
www.BDTIC.com/Intersil
FORCEOFF
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an
T1
RS-232 receiver.
V
CC
0.1µF
+
2V/DIV
T2
VCC = +3.3V C1 - C4 = 0.1µF
TIME (20µs/DIV)
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
Mouse Driveability
The ICL324X have been specifically designed to power a serial mouse while operating from low voltage supplies. Figure 9 shows the transmitter output voltages under increasing load current. The on-chip switching regulator ensures the transmitters will supply at least
±5V during worst
case conditions (15mA for paralleled V+ transmitters, 7.3mA for single V- transmitter). The Automatic Powerdown feature does not work with a mouse, so FORCEOFF FORCEON should be connected to V
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
TRANSMITTER OUTPUT VOLTAGE (V)
-6 0246810
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
V
= 3.0V
CC
T1
V
+
OUT
T2
V
T3
CC
13579
LOAD CURRENT PER TRANSMITTER (mA)
ICL3241/43
-
V
OUT
CURRENT (PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS FOR TOTAL V
CC
.
OUT+
and
V
+
OUT
V
-
OUT
CURRENT)
High Data Rates
The ICL32XX maintain the RS-232 ±5V minimum transmitter output voltages even at high data rates. Figure 10 details a transmitter loopback test circuit, and Figure 11 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF, at 120kbps. Figure 12 shows the loopback results
V
+
C
1
+
C
2
V
CC
C1+
C1-
C2+
C2-
T
IN
R
OUT
EN
SHDN OR FORCEOFF
CC
ICL32XX
T
OUT
V+
V-
R
IN
5K
FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV
T1
IN
T1
OUT
R1
OUT
VCC = +3.3V C1 - C4 = 0.1µF
5µs/DIV
FIGURE 11. LOOPBACK TEST AT 120kbps
5V/DIV.
T1
IN
T1
OUT
R1
OUT
VCC = +3.3V C1 - C4 = 0.1µF
2µs/DIV.
FIGURE 12. LOOPBACK TEST AT 250kbps
+
C
3
C
4
+
1000pF
14
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Interconnection with 3V and 5V Logic
The ICL32XX directly interface with 5V CMOS and TTL logic families. Nevertheless, with the ICL32XX at 3.3V, and the logic supply at 5V, AC, HC, and CD4000 outputs can drive ICL32XX inputs, but ICL32XX outputs do not reach the minimum V
for these logic families. See Table 4 for more
IH
information.
Typical Performance Curves VCC = 3.3V, TA = 25°C
6
V
+
4
2
1 TRANSMITTER AT 250kbps 1 OR 2 TRANSMITTERS AT 30kbps
0
-2
-4
TRANSMITTER OUTPUT VOLTAGE (V)
-6 1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
OUT
V
OUT
-
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
V
CC
SUPPLY
VOLTAGE
(V) COMPATIBILITY
3.3 3.3 Compatible with all CMOS families.
5 5 Compatible with all TTL and
CMOS logic families.
5 3.3 Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX outputs are incompatible with AC, HC, and CD4000 CMOS inputs.
25
20
15
-SLEW
SLEW RATE (V/µs)
10
5
0 1000 2000 3000 4000 5000
+SLEW
LOAD CAPACITANCE (pF)
FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
45
ICL3221
40
35
30
25
20
15
SUPPLY CURRENT (mA)
10
5
0
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
250kbps
120kbps
20kbps
FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 14. SLEW RATE vs LOAD CAPACITANCE
45
ICL3222 - ICL3232
40
35
30
25
20
15
SUPPLY CURRENT (mA)
10
5
0
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
250kbps
120kbps
20kbps
FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
15
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ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Typical Performance Curves VCC = 3.3V, TA = 25°C (Continued)
45
ICL324X
40
35
30
25
20
15
SUPPLY CURRENT (mA)
10
5
0
0
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
1000
WHEN TRANSMITTING DATA
2000
LOAD CAPACITANCE (pF)
3000
250kbps
120kbps
20kbps
4000
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3221: 286 ICL3222: 338 ICL3223: 357 ICL3232: 296 ICL324X: 464
PROCESS:
Si Gate CMOS
5000
3.5
3.0
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
ICL3221 - ICL3232
ICL324X
SUPPLY VOLTAGE (V)
NO LOAD ALL OUTPUTS STATIC
ICL324X
16
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Dual-In-Line Plastic Packages (PDIP)
N
D1
-C-
E1
-B-
A1
A2
E
A
L
e
C
C
L
e
A
C
e
B
INDEX
AREA
BASE
PLANE
SEATING
PLANE
D1
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE­DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic­ular to datum .
7. e e
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
12 3 N/2
-A-
B1
B
e
A
and eC are measured at the lead tips with the leads unconstrained.
B
must be zero or greater.
C
D
e
0.010 (0.25) C AM BS
-C-
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC ­e
A
e
B
L 0.115 0.150 2.93 3.81 4
N16 169
0.300 BSC 7.62 BSC 6
- 0.430 - 10.92 7
NOTESMIN MAX MIN MAX
Rev. 0 12/93
17
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Dual-In-Line Plastic Packages (PDIP)
N
D1
-C-
E1
-B-
A1
A2
E
A
L
e
C
C
L
e
A
C
e
B
INDEX
AREA
BASE
PLANE
SEATING
PLANE
D1
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic­ular to datum .
7. e e
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3 may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
12 3 N/2
-A-
B1
B
e
A
and eC are measured at the lead tips with the leads unconstrained.
B
must be zero or greater.
C
D
e
0.010 (0.25) C AM BS
-C-
E18.3 (JEDEC MS-001-BC ISSUE D)
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.210 - 5.33 4 A1 0.015 - 0.39 -4 A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 ­D 0.845 0.880 21.47 22.35 5
D1 0.005 - 0.13 -5
E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
e
A
e
B
L 0.115 0.150 2.93 3.81 4
N 18 18 9
0.300 BSC 7.62 BSC 6
- 0.430 - 10.92 7
NOTESMIN MAX MIN MAX
Rev. 2 11/03
18
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Small Outline Plastic Packages (SOIC)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
L
h x 45°
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
M
A1
C
0.10(0.004)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 1 6/05
19
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX AREA
123
0.05(0.002)
-A­D
e
b
0.10(0.004) C AM BS
NOTES:
1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact. (Angles in degrees)
E1
-B-
SEATING PLANE
A
-C-
M
0.25(0.010) BM M
E
α
A1
0.10(0.004)
GAUGE
PLANE
0.25
0.010
A2
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A-0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
L
c
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.020 0.028 0.50 0.70 6
N16 167
o
α
0
o
8
o
0
o
8
NOTESMIN MAX MIN MAX
-
Rev. 1 2/02
20
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Small Outline Plastic Packages (SSOP)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
GAUGE
PLANE
0.25
0.010
L
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen­sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
M
A1
0.10(0.004)
A2
C
M16.209 (JEDEC MO-150-AC ISSUE B)
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.233 0.255 5.90 6.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N16 167
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 3 6/05
21
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Small Outline Plastic Packages (SOIC)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
L
h x 45°
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
M
A1
C
0.10(0.004)
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 1 6/05
22
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Small Outline Plastic Packages (SOIC)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
L
h x 45°
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
M
A1
C
0.10(0.004)
M18.3 (JEDEC MS-013-AB ISSUE C)
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4469 0.4625 11.35 11.75 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N18 187
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 1 6/05
23
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX AREA
123
0.05(0.002)
-A­D
e
b
0.10(0.004) C AM BS
NOTES:
1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
E1
-B-
SEATING PLANE
A
-C-
M
0.25(0.010) BM M
E
α
A1
0.10(0.004)
GAUGE PLANE
0.25
0.010
A2
L
c
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.047 - 1.20 ­A1 0.002 0.006 0.05 0.15 ­A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 -
D 0.252 0.260 6.40 6.60 3 E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N20 207
o
α
0
o
8
o
0
o
8
Rev. 1 6/98
NOTESMIN MAX MIN MAX
-
24
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Shrink Small Outline Plastic Packages (SSOP)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) B
H
α
e
B
0.25(0.010) C AMB
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.
M
A1
0.10(0.004)
S
GAUGE
PLANE
M
0.25
0.010
A2
M
L
M20.209 (JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.068 0.078 1.73 1.99 A1 0.002 0.008’ 0.05 0.21 A2 0.066 0.070’ 1.68 1.78
B 0.010’ 0.015 0.25 0.38 9
C 0.004 0.008 0.09 0.20’
D 0.278 0.289 7.07 7.33 3
E 0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
C
H 0.301 0.311 7.65 7.90’
L 0.025 0.037 0.63 0.95 6
N20 207
α
0 deg. 8 deg. 0 deg. 8 deg.
NOTESMIN MAX MIN MAX
Rev. 3 11/02
25
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX AREA
123
0.05(0.002)
-A­D
e
b
0.10(0.004) C AM BS
NOTES:
1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
E1
-B-
SEATING PLANE
A
-C-
M
0.25(0.010) BM M
E
α
A1
0.10(0.004)
GAUGE
PLANE
0.25
0.010
A2
L
c
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.047 - 1.20 ­A1 0.002 0.006 0.05 0.15 ­A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 -
D 0.378 0.386 9.60 9.80 3 E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N28 287
o
α
0
o
8
o
0
o
8
Rev. 0 6/98
NOTESMIN MAX MIN MAX
-
26
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Shrink Small Outline Plastic Packages (SSOP)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
GAUGE
PLANE
0.25
0.010
L
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
M
A1
0.10(0.004)
A2
C
M28.209 (JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.390 0.413 9.90 10.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N28 287
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 2 6/05
27
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
www.BDTIC.com/Intersil
Small Outline Plastic Packages (SOIC)
N
INDEX AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
L
h x 45
o
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.
M
A1
0.10(0.004)
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 ­D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
C
h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6
N28 287
o
α
0
o
8
o
0
o
8
Rev. 0 12/93
NOTESMIN MAX MIN MAX
-
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
28
FN4805.21
March 1, 2006
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