Intersil Corporation HUF76429P3 Datasheet

HUF76429P3, HUF76429S3S

Data Sheet October 1999

44A, 60V, 0.025 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET

Packaging

JEDEC TO-220AB JEDEC TO-263AB

SOURCE

DRAIN

(FLANGE)

HUF76429P3

DRAIN

GATE

GATE

SOURCE

HUF76429S3S

DRAIN

(FLANGE)

Symbol

D

G

S

File Number 4672.1

Features

• Ultra Low On-Resistance

-r

-r

= 0.022Ω, VGS= 10V

DS(ON)

= 0.025Ω, VGS= 5V

DS(ON)

• Simulation Models

- Temperature Compensated PSPICE

®

and SABER

©

Electrical Models

- Spice and SABER Thermal Impedance Models

- www.semi.Intersil.com

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Switching Time vs R

GS

Curves

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76429P3 TO-220AB 76429P
HUF76429S3S TO-263AB 76429S

NOTE: Whenordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76429S3ST.

Absolute Maximum Ratings T

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain Current

Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TC= 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Figures 6, 17, 18

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

NOTES:

1. TJ = 25oC to 150oC.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

= 25oC, Unless Otherwise Specified

C

DSS

DGR

GS

DM

STG

pkg

HUF76429P3, HUF76429S3S UNITS

60 V
60 V

±16 V

D
D
D
D

D

L

44
47
31
30

Figure 4

110

0.74

-55 to 175

300
260

A
A
A
A

W

W/oC

o

C

o

C

o

C

1

SABER is a Copyright of Analogy, Inc. 1-888-INTERSIL or 407-727-9207

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

UltraFET™ is a trademark of Intersil Corporation. PSPICE™ is a trademark of MicroSim Corporation.

| Copyright © Intersil Corporation 1999.

HUF76429P3, HUF76429S3S

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R
Thermal Resistance Junction to

Ambient

SWITCHING SPECIFICATIONS (V

= 4.5V)

GS

Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t
SWITCHING SPECIFICATIONS (V

GS

= 10V)
Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q
Gate Charge at 5V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Gate to Drain "Miller" Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

DSSID

I

D

DSS

VDS = 55V, VGS = 0V - - 1 µA
V

GSS

GS(TH)VGS

DS(ON)ID

θJC

R

θJA

ON

d(ON)

d(OFF)

OFF

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(5)

g(TH)

ISS
OSS
RSS

VGS = ±16V - - ±100 nA

I

D

I

D

TO-220 and TO-263 - - 1.36oC/W

VDD = 30V, ID = 30A
VGS= 4.5V, RGS = 7.5Ω
(Figures 15, 21, 22)

r

f

VDD = 30V, ID = 47A
VGS= 10V,RGS = 8.2Ω
(Figures 16, 21, 22)

r

f

VGS = 0V to 5V - 21 25 nC
VGS = 0V to 1V - 1.3 1.6 nC

gs

gd

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)

= 250µA, VGS = 0V (Figure 12) 60 - - V
= 250µA, VGS = 0V , TC = -40oC (Figure 12) 55 - - V

= 50V, VGS = 0V, TC = 150oC - - 250 µA

DS

= VDS, ID = 250µA (Figure 11) 1 - 3 V
= 47A, VGS = 10V (Figures 9, 10) - 0.018 0.022 Ω
= 31A, VGS = 5V (Figure 9) - 0.021 0.025 Ω
= 30A, VGS = 4.5V (Figure 9) - 0.022 0.027 Ω

--62oC/W

- - 325 ns

-13-ns

- 203 - ns

-30-ns

-74-ns

- - 155 ns

- - 160 ns

- 7.8 - ns

- 100 - ns

-51-ns

- 104 - ns

- - 235 ns

= 0V to 10V VDD = 30V,

-3846nC
ID = 31A,
I

= 1.0mA

g(REF)

(Figures 14, 19, 20)

- 3.8 - nC

- 9.7 - nC

- 1480 - pF

- 440 - pF

-90-pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

Reverse Recovery Time t
Reverse Recovered Charge Q

2

SD

RR

ISD = 44A - - 1.25 V
I

= 22A - - 1.00 V

SD

rr

ISD = 31A, dISD/dt = 100A/µs--98ns
ISD = 31A, dISD/dt = 100A/µs - - 230 nC

Typical Performance Curves

HUF76429P3, HUF76429S3S

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

-5

10

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

50

40

VGS= 10V

30

VGS= 4.5V

20

, DRAIN CURRENT (A)

D

I

10

0

25

50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENTvs

CASE TEMPERATURE

P

DM

t

1

NOTES:
DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

-2

10

-1

10

θJC

10

0

2

x R

θJC

+ T

175

t

2

C

1

10

600

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

30

-5

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

VGS = 5V

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

3

TC = 25oC
FOR TEMPERATURES
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

0

10

C

150

1

10

HUF76429P3, HUF76429S3S

Typical Performance Curves (Continued)

300

100

OPERATION IN THIS

10

AREA MAY BE
LIMITED BY r

, DRAIN CURRENT (A)

D

I

SINGLE PULSE
T

= MAX RATED

J

TC = 25oC

1

1

DS(ON)

10 100

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

50

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 15V

V

DD

40

30

100µs

1ms

10ms

100

STARTING TJ = 25oC

STARTING TJ = 150oC

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

10

0.001 0.01 0.1 1
tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

DSS

- VDD) +1]

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

50

V

= 10V

GS

40

30

VGS = 5V
VGS = 4V

VGS = 3.5V

20

DRAIN CURRENT (A)

D,

I

10

0

1.5 2 2.5 3 3.5 4
VGS, GATE TO SOURCE VOLTAGE (V)

TJ= 175oC

TJ= -55oC

TJ= 25oC

20

, DRAIN CURRENT (A)

D

I

10

0

01234

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

40

ID = 44A

30

ID = 22A

, DRAIN TO SOURCE

20

ON RESISTANCE (mΩ)

DS(ON)

r

10

246810

, GATE TO SOURCE VOLTAGE (V)

V

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TC = 25oC

2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 3V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TC = 25oC

VGS = 10V, ID = 47A

160

FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

4

FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

HUF76429P3, HUF76429S3S

Typical Performance Curves (Continued)

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

160

200

FIGURE 11. NORMALIZED GATETHRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

3000

1000

C, CAPACITANCE (pF)

100

30

0.1 1.0 10 60
VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS= 0V, f = 1MHz

C

= CGS + C

ISS

C

≅ CDS+ C

OSS

C

= C

RSS

GD

GD

GD

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 200
, JUNCTION TEMPERATURE (oC)

T

J

160160

FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

VDD = 30V

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

010203040

5152535

, GATE CHARGE (nC)

Q

g

WAVEFORMS IN
DESCENDING ORDER:

ID = 44A

= 22A

I

D

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 14. GATE CHARGE WAVEFORMSFORCONSTANT

GATE CURRENT

600

VGS = 4.5V, VDD = 30V, ID = 30A

450

t

r

300

t

150

SWITCHING TIME (ns)

0

0 1020304050

RGS, GATE TO SOURCE RESISTANCE (Ω)

f

t

d(OFF)

t

d(ON)

250

VGS = 10V, VDD = 30V, ID = 47A

200

t

150

100

t

SWITCHING TIME (ns)

50

0

0 1020304050

d(OFF)

RGS, GATE TO SOURCE RESISTANCE (Ω)

f

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE

5

t

r

t

d(ON)

HUF76429P3, HUF76429S3S

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 1V

0

I

g(REF)

0

V

GS

Q

g(TH)

Q

gs

t

P

I

AS

t

AV

Q

g(TOT)

V

DS

Q

g(5)

VGS = 5V

Q

gd

V

DS

V

DD

VGS= 10V

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

V

DS

R

L

V

GS

+

V

DD

-

V

DS

0

DUT

R

GS

V

GS

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM

6

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

HUF76429P3, HUF76429S3S

PSPICE Electrical Model

.SUBCKT HUF76429 2 1 3 ; rev 25 June 1999

CA 12 8 1.95e-9
CB 15 14 1.95e-9
CIN 6 8 1.39e-9

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 68.05
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1e-9

LGATE 1 9 5.80e-9
LSOURCE 3 7 4.57e-9

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.8e-3
RGATE 9 20 2.80
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 41.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD

GATE

1

LGATE

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

6
8

13

10

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

S2A

S2B

5

RSLC1

51

+

5

ESLC

51

-

50
RDRAIN

16

21

-

19

8

MMED

MSTRO

CIN

15

CB

+

8

14

5
8

-

DBREAK

11

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*117),3))}
.MODEL DBODYMOD D (IS = 1.28e-12 IKF = 11.5 RS = 5.25e-3 TRS1 = 1.78e-3 TRS2 = 1.85e-6 CJO = 1.68e-9 TT = 6.14e-8 M = 0.48 XTI = 4.35)

.MODEL DBREAKMOD D (RS = 2.27e-1 TRS1 = 9.10e-4 TRS2 = -1e-6)
.MODEL DPLCAPMOD D (CJO = 1.23e-9 IS = 1e-30 N = 10 M = 0.8)
.MODEL MMEDMOD NMOS (VTO = 1.98 KP = 3.2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.80)
.MODEL MSTROMOD NMOS (VTO = 2.30 KP = 67 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.72 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 28.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.08e-3 TC2 = 1.35e-7)
.MODEL RDRAINMOD RES (TC1 = 8.25e-3 TC2 = 1.85e-5)
.MODEL RSLCMOD RES (TC1 = 4.97e-3 TC2 = 5.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 1.5e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.85e-3 TC2 = -9.48e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.72e-3 TC2 = 9.50e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.2 VOFF= -2.4)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.4 VOFF= -6.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.1 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.1)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

7

HUF76429P3, HUF76429S3S

SABER Electrical Model

REV 25 June 1999
template huf76429 n2,n1,n3

electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.28e-12, cjo = 1.68e-9, tt = 6.14e-8, xti = 4.35, m = 0.48)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.23e-9, is = 1e-30, n = 10, m = 0.8)
m..model mmedmod = (type=_n, vto = 1.98, kp = 3.2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.30, kp = 67, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.72, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2.4)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -6.2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.1, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.1)

c.ca n12 n8 = 1.95e-9
c.cb n15 n14 = 1.95e-9
c.cin n6 n8 = 1.39e-9

d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 5.80e-9
l.lsource n3 n7 = 4.57e-9

GATE

LGATE

1

RLGATE

RGATE

9

EVTEMP
+

20

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1 = 1.08e-3, tc2 = 1.35e-7
res.rdbody n71 n5 = 5.25e-3, tc1 = 1.78e-3, tc2 = 1.85e-6

S1A

12

res.rdbreak n72 n5 = 2.27e-1, tc1 = 9.10e-4, tc2 = -1.00e-6
res.rdrain n50 n16 = 7.80e-3, tc1 = 8.25e-3, tc2 = 1.85e-5
res.rgate n9 n20 = 2.80
res.rldrain n2 n5 = 10

S1B

CA

res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 41.6
res.rslc1 n5 n51 = 1e-6, tc1 = 4.97e-3, tc2 = 5.05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1 = 1.5e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.72e-3, tc2 = 9.50e-7
res.rvthres n22 n8 = 1, tc1 = -1.85e-3, tc2 = -9.48e-6

spe.ebreak n11 n7 n17 n18 = 68.05
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {

i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/117))** 3))
}
}

10

RSLC2

-

6

ESG

8

+

6

-

18
22

13

14

8

13

13

+

+

6

EGS EDS

8

-

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

15

CIN

CB

-

+

-

5

RSLC1

51

50
RDRAIN

21

MSTRO

14

5
8

ISCL

16

8

MMED

RDBREAK

72

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

7

-

+

22

RVTEMP
19

LDRAIN

RLDRAIN

RDBODY

71

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

8

HUF76429P3, HUF76429S3S

SPICE Thermal Model

REV 2 August 1999

HUF76429

CTHERM1 th 6 2.45e-3
CTHERM2 6 5 8.15e-3
CTHERM3 5 4 7.40e-3
CTHERM4 4 3 7.45e-3
CTHERM5 3 2 1.01e-2
CTHERM6 2 tl 7.49e-2

RTHERM1 th 6 9.00e-3
RTHERM2 6 5 1.80e-2
RTHERM3 5 4 9.15e-2
RTHERM4 4 3 2.43e-1
RTHERM5 3 2 3.50e-1
RTHERM6 2 tl 3.62e-1

SABER Thermal Model

SABER thermal model HUF76429
template thermal_model th tl

thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.45e-3
ctherm.ctherm2 6 5 = 8.15e-3
ctherm.ctherm3 5 4 = 7.40e-3
ctherm.ctherm4 4 3 = 7.45e-3
ctherm.ctherm5 3 2 = 1.01e-2
ctherm.ctherm6 2 tl = 7.49e-2

rtherm.rtherm1 th 6 = 9.00e-3
rtherm.rtherm2 6 5 = 1.80e-2
rtherm.rtherm3 5 4 = 9.15e-2
rtherm.rtherm4 4 3 = 2.43e-1
rtherm.rtherm5 3 2 = 3.50e-1
rtherm.rtherm6 2 tl = 3.62e-1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

CASE

tl

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

9

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]