TM
HUF76113T3ST
Data Sheet June 2000
4.7A, 30V, 0.031 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
This N-Channel power MOSFET is
®
manufactured using the innov ative
UltraFET process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where po w er
efficiency is important, such as switching regulators, switching
converters, motor drivers, rela y driv ers , low-voltage bus
switches, and power management in portable and batteryoperated products.
Formerly developmental type TA76113.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF76113T3ST SOT-223 76113
NOTE: HUF76113T3ST is available only in tape and reel.
File Number 4388.3
Features
• Logic Level Gate Drive
• 4.7A, 30V
• Ultra Low On-Resistance, r
• Temperature Compensating PSPICE
DS(ON)
= 0.031Ω
®
Model
• Temperature Compensating SABER™ Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
Packaging
DRAIN
(FLANGE)
S
SOT-223
SOURCE
DRAIN
GATE
1
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation. SABER™ is a trademark of Analogy, Inc.
UltraFET® is a registered trademark of Intersil Corporation.
HUF76113T3ST
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
A
HUF76113T3ST UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (RGS = 20kΩ ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
DGR
GS
30 V
30 V
± 16 V
Drain Current
Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Continuous (TA= 100oC, VGS = 5V) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Continuous (TA= 100oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
D
D
DM
AS
D
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
4.7
2.7
2.6
Figure 4
Figure 6
1.1
0.0091
-55 to 150
300
260
A
A
A
W
W/oC
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
A
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV
Zero Gate Voltage Drain Current I
DSSID
DSS
= 250µ A, VGS = 0V (Figure 12) 30 - - V
VDS = 25V, VGS = 0V - - 1 µ A
VDS = 25V, VGS = 0V, TC = 150oC - - 250 µ A
Gate to Source Leakage Current I
GSS
VGS = ± 16V - - ± 100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V
Drain to Source On Resistance r
GS(TH)VGS
DS(ON)ID
= VDS, ID = 250µ A (Figure 11) 1 - 3 V
= 4.7A, VGS = 10V (Figure 9, 10) - 0.027 0.031 W
ID = 2.7A, VGS = 5V (Figure 9) - 0.033 0.038 W
ID = 2.6A, VGS = 4.5V (Figure 9) - 0.035 0.040 W
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient R
θ JA
Pad Area = 0.173 in2 (Note 2) - - 110
Pad Area = 0.068 in2 (See TB377) - - 133
Pad Area = 0.026 in2 (See TB377) - - 157
o
o
o
C/W
C/W
C/W
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time t
Turn-On Delay Time t
d(ON)
Rise Time t
Turn-Off Delay Time t
d(OFF)
Fall Time t
Turn-Off Time t
ON
OFF
VDD = 15V, ID≅ 2.6A,
RL = 5.8Ω , VGS= 4.5V,
RGS = 18Ω
(Figure 15)
r
f
- - 90 ns
-1 2-n s
-4 6-n s
-3 1-n s
-3 1-n s
- - 95 ns
2
HUF76113T3ST
Electrical Specifications T
= 25oC, Unless Otherwise Specified
A
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
SWITCHING SPECIFICATIONS (V GS = 10V)
Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q
Gate Charge at 5V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Gate to Drain “Miller” Charge Q
CAPACITANCE SPECIFICATIONS
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
NOTES:
2. Rated with R
=110oC/W measured using FR-4 board with 0.173 in2 copper at 1000 seconds.
θ JA
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q
ON
VDD = 15V, ID≅ 4.7A,
RL = 3.2Ω , VGS= 10V,
d(ON)
d(OFF)
OFF
g(TOT)VGS
g(5)
g(TH)
ISS
RGS = 9.1Ω
(Figure 16)
r
f
VGS = 0V to 5V - 9.5 11.5 nC
VGS = 0V to 1V - 0.73 0.90 nC
gs
gd
VDS = 25V, VGS = 0V,
f = 1MHz
OSS
RSS
SD
(Figure 13)
ISD = 4.7A - - 1.25 V
ISD = 2.7A - - 1.00 V
ISD = 2.7A, dISD/dt = 100A/µ s- - 4 4 n s
rr
RR
ISD = 2.7A, dISD/dt = 100A/µ s- - 4 6 n C
= 0V to 10V VDD=15V,ID≅2.7A,
RL = 5.5Ω
I
= 1.0mA
g(REF)
(Figure 14)
- - 40 ns
-4-n s
-2 1-n s
-3 1-n s
-2 5-n s
- - 85 ns
- 17.0 20.5 nC
- 1.50 - nC
- 4.30 - nC
- 625 - pF
- 310 - pF
-6 0-p F
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWERDISSIPATION vs AMBIENT
TEMPERATURE
3
125
5
VGS= 10V, R
4
3
VGS= 4.5V, R
2
, DRAIN CURRENT (A)
D
I
1
0
25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (oC)
= 110oC/W
θ JA
= 110oC/W
θ JA
FIGURE 2. MAXIMUM CONTINUOUS DRAINCURRENTvs
AMBIENT TEMPERATURE
Typical Performance Curves (Continued)
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
0.1
, NORMALIZED
JA
θ
0.01
Z
THERMAL IMPEDANCE
0.001
-5
10
-4
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
SINGLE PULSE
-3
10
HUF76113T3ST
-2
10
t, RECTANGULAR PULSE DURATION (s)
-1
10
10
NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z
0
R
= 110oC/W
JA
θ
P
DM
t
1
t
2
1/t2
x R
JA
θ
1
10
+ T
JA
A
θ
2
10
3
10
500
100
10
VGS = 10V
, PEAK CURRENT (A)
DM
I
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
-5
10
200
100
-4
10
VGS = 5V
-3
10
TJ = MAX RATED
TA = 25oC
R
θ
-2
10
-1
10
10
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
40
If R = 0
tAV = (L)(IAS)/(1.3*RATED BV
If R ≠ 0
= (L/R)ln[(IAS*R)/(1.3*RATED BV
t
AV
100µ s
10
= 110oC/W
JA
0
TC = 25oC
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
- VDD)
DSS
150 - T
125
2
10
- VDD) +1]
I = I
25
1
10
DSS
STARTING TJ = 25oC
A
3
10
10
, DRAIN CURRENT (A)
D
I
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
1
DS(ON)
V
DSS(MAX)
= 30V
1ms
10ms
1 10 100
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
4
STARTING TJ = 150oC
, AVALANCHE CURRENT (A)
AS
I
1
0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY