Intersil Corporation HUF75332G3, HUF75332P3, HUF75332S3S Datasheet

HUF75332G3, HUF75332P3, HUF75332S3S

Data Sheet June 1999 File Number

60A, 55V, 0.019 Ohm, N-Channel UltraFET
Power MOSFETs

These N-Channel powerMOSFETs
are manufactured using the
innovative UltraFET™ process.

This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low­voltage bus switches, and power management in portable
and battery-operated products.

Formerly developmental type TA75332.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75332G3 TO-247 75332G
HUF75332P3 TO-220AB 75332P
HUF75332S3S TO-263AB 75332S

NOTE: Whenordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75332S3ST.

Features

• 60A, 55V

• Simulation Models

®

- Temper ature Compensated PSPICE

and SABER

Models

- SPICE and SABER Thermal Impedance Models
Available on the WEB at: www.intersil.com

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

4489.3

©

Packaging

DRAIN
(TAB)

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

JEDEC TO-263AB

GATE
SOURCE

DRAIN

(FLANGE)

DRAIN

(FLANGE)

SOURCE

DRAIN

GATE

94

SABER is a Copyright of Analogy, Inc. http://www.intersil.com or 407-727-9207

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.

| Copyright © Intersil Corporation 1999

HUF75332G3, HUF75332P3, HUF75332S3S

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

55 V
55 V

±20 V

Drain Current

Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

D

DM

AS

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60

Figure 4

Figures 6, 14, 15

145

0.97

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV
Zero Gate Voltage Drain Current I

DSSID

DSS

= 250µA, VGS = 0V (Figure 11) 55 - - V
VDS = 50V, VGS = 0V - - 1 µA
VDS = 45V, VGS = 0V, TC = 150oC - - 250 µA

Gate to Source Leakage Current I

GSS

VGS = ±20V - - ±100 nA

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

GS(TH)VGS

DS(ON)ID

= VDS, ID = 250µA (Figure 10) 2 - 4 V

= 60A, VGS = 10V (Figure 9) - 0.016 0.019 Ω

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

θJC
θJA

(Figure 3) - - 1.03
TO-247 - - 30
TO-220, TO-263 - - 62

o

C/W

o

C/W

o

C/W
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t

ON

OFF

VDD = 30V, ID≅ 60A,
RL = 0.50Ω, VGS= 10V,
RGS = 6.8Ω

r

f

- - 100 ns

-12- ns

-55- ns

-11- ns

-25- ns

- - 55 ns

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q
Gate Charge at 10V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Reverse Transfer Capacitance Q

g(TOT)VGS

g(10)

g(TH)

gs
gd

= 0V to 20V VDD = 30V,
VGS = 0V to 10V - 40 50 nC
VGS = 0V to 2V - 2.5 3.0 nC

ID≅ 60A,
RL = 0.50Ω
I

= 1.0mA

g(REF)

(Figure 13)

-7085nC

-6-nC

-15-nC

95

HUF75332G3, HUF75332P3, HUF75332S3S

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

Typical Performance Curves

1.2

1.0

0.8

ISS

OSS

RSS

SD

rr

RR

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)

- 1300 - pF

- 480 - pF

- 115 - pF

ISD = 60A - - 1.25 V
ISD = 60A, dISD/dt = 100A/µs--75ns
ISD = 60A, dISD/dt = 100A/µs - - 140 nC

80

60

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TC, CASE TEMPERATURE (oC)

125 175

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

40

20

, DRAIN CURRENT (A)

D

I

0

25

50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

1

NOTES:
DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

-2

10

-1

10

10

2

x R

θJC

0

t

θJC

2

+ T

C

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

96

HUF75332G3, HUF75332P3, HUF75332S3S

Typical Performance Curves

1000

VGS = 10V

, PEAK CURRENT (A)

100

DM

I

500

100

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

50

-5

10

-4

10

(Continued)

-3

10

t, PULSE WIDTH (s)

-2

10

FIGURE 4. PEAK CURRENT CAPABILITY

500

TJ = MAX RATED

= 25oC

T

C

100µs

100

TC = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

-1

10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

o

C DERATE PEAK

175 - T

25

0

10

- VDD)

DSS

STARTING TJ = 25oC

STARTING TJ = 25oC

150

- VDD) +1]

DSS

C

1

10

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

V

DSS(MAX)

1

1 200

DS(ON)

= 55V

10 100

1ms

10ms

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

150

V

= 20V

120

90

60

, DRAIN CURRENT (A)

D

I

30

0

0 1.5 3.0 4.5 6.0 7.5

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

GS

VGS = 10V

= 7V

V

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

T

= 25oC

C

V

VGS= 5V

GS

= 6V

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

AS

I

10

0.001 0.01 0.1 1 10
t

, TIME IN AVALANCHE (ms)

AV

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

150

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

120

90

60

, DRAIN CURRENT (A)

D

I

30

0

0 1.5 3.0 4.5 6.0 7.5

V

, GATE TO SOURCE VOLTAGE (V)

GS

25oC

-55oC

175oC

VDD = 15V

FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS

97

HUF75332G3, HUF75332P3, HUF75332S3S

Typical Performance Curves

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 10V, ID = 60A

V

GS

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-40 0 40 80 120 160 200

-80
TJ, JUNCTION TEMPERATURE (oC)

(Continued)

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.2
ID = 250µA

1.1

NORMALIZED GATE

THRESHOLD VOLTAGE

1.2

1.0

0.8

0.6

-40 0 40 80 120 160 200

-80
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

FIGURE 10. NORMALIZED GATETHRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

2000

1500

1000

C

ISS

VGS= 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C

GD

≈ CDS + C

GD

GD

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-40 0 40 80 120 160 200

-80
T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

10 20 30 40 50 600

Q

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

C, CAPACITANCE (pF)

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

WAVEFORMS IN
DESCENDING ORDER:

VDD = 30V

, GATE CHARGE (nC)

g

C

500

0

0 102030405060

V

DS

ID = 60A

= 45A

I

D

= 30A

I

D

= 15A

I

D

OSS

C

RSS

, DRAIN TO SOURCE VOLTAGE (V)

98

HUF75332G3, HUF75332P3, HUF75332S3S

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

V

I

G(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 2V

0

I

g(REF)

0

V

GS

Q

g(TH)

Q

gs

t

P

I

AS

t

AV

Q

g(TOT)

V

DS

Q

g(10)

VGS = 10V

Q

gd

V

DS

V

DD

VGS= 20V

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM

V

DS

R

L

V

GS

+

V

DD

-

V

DS

0

DUT

R

GS

V

GS

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

t

10%

r

PULSE WIDTH

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

99

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%