Intersil Corporation HSP-EVAL Datasheet

HSP-EVAL

USER’S MANUAL May 1999

DSP Evaluation Platform

The HSP-EVAL is the mother board for a set of daughter
boards based on the HSPxxxxx family of Digital Signal
Processing products. Each product specific daughter board
is mated with the HSP-EVAL to provide a mechanism for
rapid evaluation and prototyping. As shown in Figure 1, the
HSP-EVAL consists of a series of busses which provide
input, output, and control to the target daughter board.
These busses are brought out through dual 96 Pin
connectors to support daisy chaining HSP-EVALs for
multichip prototyping and evaluation.

For added flexibility, the input and control busses can be
driven by registers on-board the HSP-EVAL which have
been down loaded with data via the parallel port of an IBM

TM

PC

or compatible. In addition, a Shift Register is provided
to serialize data on the daughter board output busses for
reading into the PC via the status lines of the parallel port.
Together, the I/O and Control Registers can be used to drive
the target daughter board with a PC based vector set while
collecting daughter board outputs to the PC’s disk.

File Number 3366.2

Features

• Single HSP-EVAL May be Used to Evaluate a Variety of
Parts Within the HSPXXXXX Family of DSP Products

• MaybeDaisyChainedto SupportEvaluationof Multi-Chip
Solutions

• Parallel Port Interface to Support IBM PC™ Based
Evaluation and Control

• Three Clocking Modes for Flexibility in Performance
Analysis and Prototyping

• Dual 96-Pin Input/Output Connectors Conforming to the
VME J2/P2 Connector Standard

Applications

• PC Based Performance Analysis of HSPXXXXX Family of
DSP Products

• Rapid Prototyping

Jumper selectable clock sources pro vide three different
methods of clocking the part under evaluation. In mode one,
the clock signal is generated under PC based software
control. In mode two,theHSP-EVAL’s on-board oscillator may
be selected as the clock source. In mode three, the user ma y
provide an external clock through the 96 Pin Input Connector.

The HSP-EVAL was built into a 3U Euro-Card form factor
with dual 96 Pin Input/Output connectors. The I/O
connectors conform to the VME J2/P2 connector standard.

DSP Evaluation Platform

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Copyright © Intersil Corporation 2000

IBM PC™ is a trademark of IBM Corporation.

HSP-EVAL

Getting Started

The HSP-EVAL was designed to operate in conjunction with
daughter boards designed for the HSPXXXXX family of DSP
products. A simple procedure for assembly and operation of
the target daughter board with the HSP-EVAL is described in
the respective daughter board’sUser’s Manual. What follows
in this document is a detailed description of the HSP-EVAL
and its operation.

Bus Structure

The HSP-EV AL utilizes a series of 16-bit busses for daughter
board input, output and control as shown in Figure 1. The
input and output busses interface the daughter board to the
outside world through 96 Pin DIN connectors conforming to
the VME J2/P2 connector standard. Daughter board control is
provided by register driven control busses do wn loaded with
data via the parallel port of a PC. For added flexibility, the
input busses may also be register driven with do wn loaded
data.

Two input busses, IN1_0-15 and IN2_0-15, bring data from
the 96 Pin DIN connector (P1) to the daughter board through
the 50 position Input Connector (J1). Each input bus is 16
bits wide and the signal mapping for the above connectors is
given in Tables 1 and 3. As an alternative, the input busses
may be driven by registers which have been down loaded
with data through the Parallel Port Bus.

Two output busses, OUT1_0-15 and OUT2_0-15, carry
daughter board output from the 50 Pin Output Connector

(J2) to the 96 Pin DIN connector (P2). Each output bus is 16
bits wide and the signal mapping for the above connectors is
given in Tables 2 and 4. A shift register is provided to
serialize data on the output busses for transmission via the
Parallel Port Bus.

A status bus, STAT0-3, maps four status outputs from the
daughter board Output Connector J2 to the Configuration
Jumper Field (J4). The Configuration Jumper Field is used to
select one of the four status lines for transmission via the
Parallel Port Bus (see Configuration Jumper Field Section).

The two control busses, IN3_0-15 and CTL0-15, connect a
set of registers to the 50 Pin Control Connector (J3). Each
control bus is 16 bits wide and the signal mapping for the J3
Control Connector is shown in Table 5. The four least
significant bits of the CTL0-15 bus are also used to control
the operation of the HSP-EVAL (see Register Structure
Section). As with the registers driving the input busses, the
registers driving the control busses are down loaded with
data via the Parallel Port Bus.

Parallel Port Bus

The Parallel Port Bus carries the data and signals required
to support bidirectional data transfers between the HSP­EVAL and the parallel port of an IBM PC or compatible. The
port bus contains eight data lines, PCD0-7, two control lines,
PCWR0-1, and three serial output lines, PCRD0-2. The con­trol and data lines are used to down load data into the HSP­EVAL's on board registers via the Parallel Port Interface. The
serial output lines carry daughter board status and output
serialized by the On Board Shift Register.

96 PIN INPUT CONNECTOR (P1)

EXT CLK

INPUT BUS 1

(IN1_0-15)

INPUT BUS 2

(IN2_0-15)

CLK IN

OSC

CONTROL CONNECTOR

16

16

INPUT CONNECTOR (J1)

INPUT
REG 1

PARALLEL PORT BUS

CONFIGURATION JUMPER FIELD (J4)

INPUT
REG 2

SELECT ENABLE SELECT SELECT

FIGURE 1. BLOCK DIAGRAM OF HSP-EVAL

OUTPUTOUTPUTADDRESSCLK

16

INPUT BUS 3

INPUT
REG 3

(J3)

16

(IN3_0-15)

CTL0

CTL CONTROL

(CTL0-15)

CTL BUS

REG

OUTPUT CONNECTOR (J2)

OUTPUT BUS 1

(OUT1_0-15)

OUTPUT BUS 2

(OUT2_0-15)

CTL2-3

STAT0-3

SHROUDED HEADER

(J5)

SHIFT REGISTER

PARALLEL PORT

INTERFACE

26 PIN HEADER

16

16

CLK OUT

13

96 PIN OUTPUT CONNECTOR (P2)

2

HSP-EVAL

TABLE 1. PIN ASSIGNMENTS FOR 96 PIN INPUT

CONNECTOR P1

ROW A

PIN

NUMBER

SIGNAL

MNEMONI

1 AUXIN0 V

ROW B

SIGNAL

MNEMONIC

CC

2 IN2_0 GND IN2_1
3 IN2_2 N.C. IN2_3
4 IN2_4 N.C. IN2_5
5 IN2_6 N.C. IN2_7
6 GND N.C. IN2_8
7 IN2_9 N.C. IN2_10
8 IN2_11 N.C. IN2_12

9 IN2_13 N.C. IN2_14
10 IN2_15 N.C. GND
11 AUXIN1 N.C. IN1_0
12 IN1_1 GND IN1_2
13 IN1_3 V

CC

14 IN1_5S N.C. IN1_6
15 IN1_7 N.C. GND
16 IN1_8 N.C. IN1_9
17 IN1_10 N.C. IN1_11
18 IN1_12 N.C. IN1_13
19 IN1_14 N.C. IN1_15
20 GND N.C. CLKIN
21 GND N.C. N.C.
22 GND GND N.C.
23 GND N.C. N.C.
24 GND N.C. N.C.
25 GND N.C. N.C.
26 PCD0 N.C. PCD1
27 PCD2 N.C. PCD3
28 PCD4 N.C. PCD5
29 PCD6 N.C. PCD7
30 PCWR0 N.C. GND
31 PCWR1 GND PCRD0
32 PCRD1 V

CC

ROW C

SIGNAL

MNEMONIC

GND

IN1_4

PCRD2

TABLE 2. PIN ASSIGNMENTS FOR 96 PIN OUTPUT

CONNECTOR P2

ROW A

PIN

NUMBER

SIGNAL

MNEMONIC

1 AUXOUT0 V

ROW B

SIGNAL

MNEMONIC

CC

GND
2 OUT2_0 GND OUT2_1
3 OUT2_2 N.C. OUT2_3
4 OUT2_4 N.C. OUT2_5
5 OUT2_6 N.C. OUT2_7
6 GND N.C. OUT2_8
7 OUT2_9 N.C. OUT2_10
8 OUT2_11 N.C. OUT2_12
9 OUT2_13 N.C. OUT2_14

10 OUT2_15 N.C. GND
11 AUXOUT1 N.C. OUT1_0
12 OUT1_1 GND OUT1_2
13 OUT1_3 V

CC

OUT1_4

14 OUT1_5 N.C. OUT1_6
15 OUT1_7 SN.C. GND
16 OUT1_8 N.C. OUT1_9
17 OUT1_10 N.C. OUT1_11
18 OUT1_12 N.C. OUT1_13
19 OUT1_14 N.C. OUT1_15
20 GND N.C. CLKOUT
21 GND N.C. STAT0
22 GND GND STAT1
23 GND N.C. STAT2
24 GND N.C. STAT3
25 GND N.C. N.C.
26 PCD0 N.C. PCD1
27 PCD2 N.C. PCD3
28 PCD4 N.C. PCD5
29 PCD6 N.C. PCD7
30 PCWR0 N.C. GND
31 PCWR1 GND PCRD0
32 PCRD1 V

CC

PCRD2

ROW C

SIGNAL

MNEMONIC

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HSP-EVAL

The Parallel Port Bus is interfaced to the PC by connecting
the provided ribbon cable between the 26 position shrouded
header (J5) and the PC's parallel port. The ribbon cable
maps the Parallel Port Bus signals to the PC's parallel port
as shown in Table 6.

The Parallel Port Bus is brought out through each of the 96
Pin DIN connectors (P1, P2) so that Multiple HSP-EVALs
can be daisy chained. This allows different HSP-EVALs in
the chain to be controlled through a single HSP-EVAL which
has been connected to a host PC.

TABLE 3. SIGNAL ASSIGNMENTS FOR 50 POSITION INPUT

CONNECTOR J1

PIN

NUMBER

1 AUX_IN0 GND
2 IN2_0 IN2_1
3 IN2_2 IN2_3
4 IN2_4 IN2_5
5 IN2_6 IN2_7
6 GND IN2_8
7 IN2_9 IN2_10
8 IN2_11 IN2_12

9 IN2_13 IN2_14
10 IN2_15 GND
11 AUX_IN1 IN1_0
12 IN1_1 IN1_2
13 IN1_3 IN1_4
14 IN1_5 IN1_6
15 IN1_7 GND
16 IN1_8 IN1_9
17 IN1_10 IN1_11
18 IN1_12 IN1_13
19 IN1_14 IN1_15
20 GND CLKIN
21 GND N.C.
22 GND V
23 GND V
24 GND V
25 GND V

J1A SIGNAL

MNEMONIC

J1B SIGNAL

MNEMONIC

CC
CC
CC
CC

Register Structure

The HSP-EVAL provides a series of registers which may be
used as a source for daughter board input and control. In
addition, a Shift Register is supplied to serialize data on the
daughter board output bus for transmission via the Parallel
Port Bus. Data transfers involving these registers are
described in the following sections.

The HSP-EVAL has a set of eight 8-bit data registers which
are organized as a set of four “logical” input and control
registers, Input Registers 1 thru 3 and the CTL Control
Register. The outputs of these registers drive four 16 bit
busses which are mapped to the daughter board through the
Input Connector (J1) and the Control Connector (J3) (see
Bus Structure Section). The mapping of the 8-bit data
registers to bus signals and “logical” registers is given in
Table 7.

TABLE 4. SIGNAL ASSIGNMENTS FOR 50 POSITION

OUTPUT CONNECTOR J2

PIN

NUMBER

1 AUXOUT0 GND
2 OUT2_0 OUT2_1
3 OUT2_2 OUT2_3
4 OUT2_4 OUT2_5
5 OUT2_6 OUT2_7
6 GND OUT2_8
7 OUT2_9 OUT2_10
8 OUT2_11 OUT2_12

9 OUT2_13 OUT2_14
10 OUT2_15 GND
11 AUXOUT1 OUT1_0
12 OUT1_1 OUT1_2
13 OUT1_3 OUT1_4
14 OUT1_5 OUT1_6
15 OUT1_7 GND
16 OUT1_8 OUT1_9
17 OUT1_10 OUT1_11
18 OUT1_12 OUT1_13
19 OUT1_14 OUT1_15
20 GND CLKOUT
21 GND STAT0
22 GND STAT1
23 GND STAT2
24 GND STAT3
25 GND N.C.

J2A SIGNAL

MNEMONIC

J2B SIGNAL

MNEMONIC

4