Intersil Corporation HSP50415EVAL1 Datasheet
TM
HSP50415EVAL1
Data Sheet April 2000
HSP50415EVAL1 Evaluation Kit
The HSP50415EVAL1 is an evaluation kit fortheHSP50415
wideband programmable modulator. The kit consists of an
evaluation Circuit Card Assembly (CCA) complete with the
HSP50415 device and additional circuitry to provide for
control via a computer parallel port. Windows based
demonstration software is provided for full user
programmability and control of all HSP50415 operational
modes. The evaluation board provides digital outputs which
are accessible through a standard logic analyzer header. It
also provides both single ended and differential analog
outputs via standard SMA connectors. Documentation
includes a user’s manual, full evaluation board schematics
and PCB layout materials. Special filter files, pattern files
and exampleconfiguration script files are included for quickly
configuring the board.
File Number 4859
Features
• Evaluation CCA Complete With HSP50415 Wideband
Programmable Modulator
• Windows Based Demonstration Software
• Example Files For Common Modulation Techniques
Reference Documents
• HSP50415EVAL1 Demonstration Software in File
HSP50415.exe
• Example Configuration Files in *.js, filter files in *.coe, and
Pattern Files in *.pat
• HSP50415EVAL1 Schematics in File sch415bx.pdf
• HSP50415EVAL1 Layout in File fab415bx.pdf
• HSP50415EVAL1 Bill of Material in File bom415bx.pdf
The latestversion forall reference materials and programs is
available via the Intersil internet website:
‘www.intersil.com/commlink/download/hsp50415eval1’.
Block Diagram
COMPUTER
PARALLEL
PORT
P1 25 PIN ‘D’
LPT PORT
U1
LVX161284
IEEE XCVR
J14 TEST
SOCKET
U8
HC244
BUFFER
JTAG /6
P5 JTAG
HEADER
CY37256V CPLD
/17
P2 DEBUG
HEADER OSC SMA
U2
CONTROL /3
DATA /18
CONTROL /7
ADDRESS /20
DEBUG /16
U5
/4
D3-D6 STATUS
STATUS /4
CONTROL /8
U3
ALVCH16823
DATA REG
U7
CY7C1327
SRAM
J5
LEDs
J15 TEST
SOCKET
J13 TEST
SOCKET
HSP50415 WIDEBAND PROG. MOD.
FEMPT, FOVRFL, FFULL LOCKDET
CE, WR, RD, RESET, ADDR<2:0>, INTREQ
CDATA<7:0>
TXEN
ISTRB
DIN<15:0>
DATACLK
SYSCLK/2
2XSYSCLK
REFCLK
CLK
U6
OSC
U4
PLLRC
J4
SMA FILTER
LOOP
I OUT<13:0>
IOUTA
IOUTB
QOUTA
QOUTB
P3 TEST
HEADER
T1
T2
J2
SMA
J3
SMA
I OUT
Q OUT
EXTERNAL CLK
4-1
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
EXTERNAL CLK
HSP50415EVAL1
Getting Started
Installation Requirements
1. A personal computer running Windows 95, Windows 98,
or Windows NT with a bidirectional parallel port.
2. A 5V
evaluation CCA by sourcing 1.0 amps.
power supply capable of supporting the
DC
Software Installation
Obtain the latest version of the downloadable software from
‘www.intersil.com/commlink/download/hsp50415eval1’. The
software is packaged into an executable zip file format. Copy
the file onto the target computer from the website.
Windows 95
1. Executethe ‘HSP50415.exe’installation program. This
program will create folder HSP50415 and install the
required files.
2. Selectand execute‘ste51en.exe.’This programwill install
the required Windows scripting host.
Windows 98
1. Executethe ‘HSP50415.exe’installation program. This
program will create folder HSP50415 and install the
required files.
2. Ifthe target computer’soperating system wasloadedwith
the default system configuration, it is not necessary to
select and execute “ste51en.exe.” This program would
have been part of the default. If scripting errors are
encountered, execute ‘ste51en.exe.’
Windows NT
1. Executethe ‘HSP50415.exe’installation program. This
program will create folder HSP50415 and install the
required files.
2. Selectand execute‘ste51en.exe.’This programwill install
the required Windows scripting host.
3. Execute‘TDLPortIO.exe’from the disk. ‘TDLPortIO.exe’
installs the parallel port driver, a necessary component
for running the software under Windows NT. In order to
run ‘TDLPortIO.exe’ successfully you must have
administrator privileges on your NT machine, and have
the ‘DLLPortIO.dll’ and ‘DLLPortIO.sys’files in the same
directory from which you are executing ‘TDLPortIO.exe’.
Upon completion, you must reboot in order for the driver
to take effect.
Hardware Description
Board Components
The evaluation board consistsof three major components as
depicted in the block diagram:
1. HSP50415 (U4): This is the wideband programmable
modulator device.
2. SRAM (U7). The board uses a 256K x 18 bits
synchronous RAMto store digital data patterns for theInphase and Quadrature inputs to the HSP50415. The
SRAM is clocked with the same clock that strobes data
into the HSP50415 (DATACLK). The RAM can hold I/Q
stimulus patterns that are repeatable with no overhead.
3. CPLD (U2): The CPLD’s main function is to interface
between the HSP50415, the PC’s parallel port, and the
SRAM. The CPLD is in system re-programmable,
allowing for CCA configuration fielded upgrades.
Communication with the PC is achieved using the ‘EPP’
(Standard Parallel Port) handshake. Each of the evaluation
board’s two clocks can be either driven internally by U5 and
U6, or externally via SMA connectors J4 and J5. When
providing these clocks externally, 50Ω terminators for the
external clock sources must be enabled through jumpers
JP6 and JP7.
CPLD Registers
The CPLD contains three groups of registers, the first group
contains an Address register and a Data register for
implementing the EPP handshake. Note that the PC doesn’t
necessarily require an EPP, as the evaluation software will
emulate the EPP handshake. The second group of CPLD
registers is shown in Table 2. These registers can be
accessed from the evaluation software using the console
commands “pldread” and “pldwrite” or using scripts. The
third group of registers is shown in Table 3. These registers
can be accessed from the evaluation software using the
console commands “read” and “write” or using scripts. For
more details refer to the ‘Software Description’ section.
Hardware Configuration
Verify the following defaultjumper configurations per Table 1:
1. JP1 in position 1-2. (programming ‘norm’ mode).
2. JP-2 and JP-3 in position 1-2. (board address to 00).
3. JP4 has no jumper. (software controls the source of
DATACLK).
4. JP5 in position 1-2. (HSP50415 REFLO enabled as the
1.2V internal reference).
5. JP6 has no jumper (for using the internal REFCLK).
6. JP7 has no jumper (for using the internal Clk).
7. Connect the 5V power supply to the evaluation board
connector J1using the supplied power cable.Ensure the
power supply can source 1.0 amps regulated at
5V
±5%.
DC
WARNING: Ensure care is utilized to prevent the application of
reverse polarity power to the CCA.
8. Connect the supplied ribbon cablefrom the PC’s parallel
port to the evaluation board’sP1 connector ensuring the
arrowindicating pinone onthe ribbon cable connectorJ1
and the CCA P1 are correctly mated.
Software Description
The evaluation software provides a graphical user interface
that allows full control over the HSP50415 evaluation board.
Through the software, all operational modes of the
HSP50415 can be exerted, via the CPLD and SRAM. The
software also implements functions for loading stimulus
4-2
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