Intersil Corporation HSP50307 Datasheet
HSP50307
December 1996
Features
• 256 KBPS Data Rate and 128 KBPS Baud Rate
• Burst QPSK Modulation
• Programmable Carrier Frequency from 8MHz to
15MHz With a Frequency Step Size of 32kHz
• α = 0.5 Root Raised Cosine (RRC) Filtering For Spectrum Shaping
• On-Board Synthesizer
• Programmable Output Level From 22 to 62dBmV in
1dB Steps
• Programmable Charge Pump Current Control
• 62dBmV Differential Output Driver for 75Ω Cable
Applications
• Burst QPSK Modulator
• HSP50307EVAL1 Evaluation Board Is Available
Ordering Information
TEMP.
PART NUMBER
HSP50307SC 0 to 70 28 Ld SOIC M28.3
RANGE (oC) PACKAGE
PKG.
NO.
Burst QPSK Modulator
Description
The HSP50307 is a mixed signal burst QPSK Modulator for
upstream CATV Applications. The HSP50307 demultiplexes
and modulates a serial data stream onto an RF Carrier centered between 8 and 15MHz. The signal spectrum is shaped
with α = 0.5 root raised cosine (RRC) digital filters. On-chip filtering limits spurs and harmonics to levels below -35dBc during transmissions. The output power level is adjustable over a
40dB range in 1dB steps. The maximum differential output
level is +62dBmV into 75Ω. A transmitter inhibit function disables the RF output outside the burst interval. The differential
output amplifier int7-erfaces to the cable via a transformer.
The Block Diagram of the HSP50307 QPSK Modulator is
shown below. The HSP50307 consists of a digital control
interface, an I/Q generator, a synthesizer, and a quadrature
modulator.
The data clock is derived from the master clock. The
HSP50307 demultiplexes the input data bits into in-phase (I)
and quadrature (Q) data streams. The first bit and subsequent
alternating bits of the burst are in-phase data. The two data
streams are filtered, converted from digital to analog, and low
pass filtered to produce the baseband I and Q analog signals.
The baseband signals are up-converted to RF in the Quadrature Modulation Section. The synthesizer provides the local
oscillator (LO) for the quadrature modulator. The frequency is
programmable via the control interface with a resolution of
32kHz. The output of the quadrature modulator is low pass filtered to remove harmonic distortion.
Block Diagram
VCO_INRCLK
RESET
CCLK
C_EN
CDATA
TX_EN
TX_DATA
TXCLK
MCLK
†
Indicates analog circuitry.
MCLK MUST ALWAYS BE PRESENT FOR PROPER OPERATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
http://www.intersil.com or 407-727-9207
CONTROL
INTERFACE
I/Q GENERATOR
I
8RRC LPF
DEMUX
Q
8RRC
/100
DAC_REF
| Copyright © Intersil Corporation 1999
VCO_SET PD_OUT
SYNTHESIZER
9
D/A
9
D/A
LPF
7-68
†
†
IBBOUT
QBBOUT
IBBIN
QUAD
GEN
QBBIN
QUADRATURE
MODULATOR
+
LPF PGA
TX_EN
VCM_REF
†
MOD_OUT-
MOD_OUT+
File Number
4219
Pinout
MCLK
TXCLK
TX_EN
TX_DATA
RESET
DGND
AVCC
AGND
IBBOUT
QBBOUT
QBBIN
IBBIN
DAC_REF
VCM_REF
HSP50307
28 LEAD SOIC
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
CCLK
CDATA
27
26
C_EN
25
DVCC
24
RCLK
23
AGND
PD_OUT
22
21
VCO_IN
20
VCO_SET
19
AVCC
MOD_OUT-
18
MOD_OUT+
17
16
AVDD
AGND
15
Pin Description
SYMBOL TYPE DESCRIPTION
MCLK I Master clock input (25.6MHz). (D)
TXCLK O PSK data clock (256kHz) for PSK_DATA_IN. (D)
TX_EN I Transmit Enable. When high, the modulator output is enabled. This pin should be high for the entire burst. The signal is
extended internally until data has fully exited the part before turning off for spurious free turn on and turn off. (D)
TX_DATA I 256 KBPS serial data input. (D)
RESET I Digital Reset Pin (active low). The part is reset immediately on assertion of the reset pin. The output of the part is
disabled on the assertion of reset. The part will come out of reset 2 master clock periods after the reset is deasserted. Reprogramming (see Control Interface Section) is needed after deassertion of reset for proper operation. (D)
DGND I Negative supply for the digital filters and control. (P)
AVCC I Positive supply for the quadrature modulator. AVCC should be tied to +5V analog. (P)
AGND I Negative supply for the quadrature modulator. AGND is tied to GND. (P)
IBBOUT O I baseband filtered output. (A)
QBBOUT O Q baseband filtered output. (A)
QBBIN I Q baseband modulator input. (A)
IBBIN I I baseband modulator input. (A)
DAC_REF O D/A reference node. A 0.1µF capacitor to ground is suggested. (A)
VCM_REF O Modulator common mode reference node. A 0.1µF capacitor to ground is suggested. (A)
AGND I Negative supply for the cable interface. (P)
AVDD I Positive supply for the cable interface (+9V analog). (P)
MOD_OUT+ O Positive output drive pin for the cable interface. (A)
MOD_OUT- O Negative output drive pin for the cable interface. (A)
7-69
HSP50307
Pin Description
SYMBOL TYPE DESCRIPTION
AVCC I Positive supply for the synthesizer (+5V analog). (P)
VCO_SET I/O VCO free running frequency set resistor (normally 6.25kΩ). (D)
VCO_IN I Voltage-controlled oscillator control voltage. (D)
PD_OUT O Phase/frequency detector output. (D)
AGND I Negative supply for the synthesizer. (P)
RCLK I Synthesizer reference clock input (2.048MHz). (D)
DVCC I Positive supply for the digital filters and control (+5V digital). (P)
C_EN I Control interface enable for 3 wire interface. See Control Interface Section. (D)
CDATA I Serial data input for 3 wire interface. See Control Interface Section. (D)
CCLK I 3 wire interface clock. See Control Interface Section. (D)
NOTE: (A) = analog, (D) = digital, (P) = power.
Functional Description
The HSP50307 is designed to transmit 256 KBPS data
using QPSK modulation on a programmable carrier over
75Ω cable lines. The incoming 256 KBPS data is first
demultiplexed into in-phase (I) and quadrature (Q) data
streams. The burst QPSK modulator shapes the two
128 KBPS demultiplexed data streams using interpolateby-8 root-raised cosine (RRC) filters with α = 0.5. The
resulting 1.024MHz data streams are sent through D/A
converters and are then sent through low-pass
reconstruction filters for over 40dB image rejection. The
baseband analog output and input pins allow the signals to
be AC coupled. The returning analog signal is upconverted
by an analog quadrature modulator. The control section is
(Continued)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
COEFFICIENT VALUE
0
-0.1
-0.2
1
8 16243240485664
configured by loading 23 bits of information via a three-wire
interface. These bits configure the DSP filter section, the
carrier frequency, the analog synthesizer, and the output
driver sections.
FIGURE 1. NORMALIZED IMPULSE RESPONSE OF THE RRC
INTERPOLATION FILTER WITH α = 0.5
TAP NUMBER
Digital Filters
The burst QPSK modulator uses an interpolate-by-8 digital
RRC filter on both the I and Q data streams. The shaping
factor is set to α = 0.5. The FIR order of the digital RRC filter
is 64. Figure 1 shows the impulse response of the RRC filter.
Figure 2 is a spectrum analyzer plot of the modulator output
for a baud rate of 128 kbaud and a pseudorandom data pattern. The 128kHz 3dB bandwidth and 192kHz stopband
edges are readily apparent.
REF -15.0 dBm
PEAK
LOG
5dB/
WA SB
SC FS
CORR
CENTER 8.0960MHz
#RES BW 300Hz VBW 300Hz
FIGURE 2. SPECTRUM OF 8.096MHz RANDOM DATA MODU-
LATED CARRIER
# AT 60dB
MKR 8.0960MHz
7-70
-16.83dBm
SPAN 400.0kHz
SWP 13.3s
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