Intersil Corporation HSP50215 Datasheet

HSP50215

Data Sheet January 1999 File Number

Digital UpConverter

The HSP50215 Digital UpConverter (DUC) is a QASK/FM modulator/FDM upconverter designed for high dynamic range applications such as cellular basestations. The DUC combines shaping and interpolation filters, a complex modulator, and Timing and Carrier NCO’s into a single package. Each DUC can create a single FDM channel. Multiple DUC’s can be cascaded digitally for multi-channel applications.

The HSP50215 supports both vector and FM modulation. In vector modulation mode, the DUC accepts 16-bit I and Q samples to generate virtually any quadrature AM or PM modulation format. The DUC also has two FM modulation modes. In the FM with pulse shaping mode, the 16-bit frequency samples are pulse shaped/bandlimited prior to FM modulation. No bandlimiting filter follows the FM modulator . This FM mode is useful for GMSK type modulation formats. In the FM with bandlimiting filter mode, the 16-bit frequency samples directly drive the FM modulator. The FM modulator output is filtered to limit the spectral occupancy. This FM mode is useful for analog FM or FSK modulation formats.

The DUC includes an NCO driven interpolation ﬁlter, which allows the input and output sample rate to have anoninteger or variable relationship. This re-sampling feature simpliﬁes cascading modulators with sample rates that do not have harmonic or integer frequency relationships.

The DUC offers digital output spectral purity that exceeds 85dB at the maximum output sample rate of 52 MSPS, for input sample rates as high as 300 KSPS.

A 16-bit microprocessor compatible interface is used to load configuration and baseband data. A programmableFIFO depth interrupt simplifies the interface to the I and Q input FIFOs.

4346.4

Features

• Output Sample Rates Up to 52 MSPS (48 MSPS Industrial); Input Data Rates Up to 3.25 MSPS

• I/Q Vector, FM, and Shaped FM Modulation Formats

• 32-Bit Programmable Carrier NCO; 30-Bit Programmable Symbol Timing NCO

• Programmable I and Q, 256 Tap, Shaping FIR Filters with Interpolation by 4, 8 or 16

• Interpolation Filter Up Samples Shaping Filter Output to Output Sample Rate Under NCO Control

• Processing Capable of >90dB SFDR

• Cascade Input for Multiple Channel Transmissions

• 16-Bit µProcessor Interface for Conﬁguration and User Data Input

Applications

• Single or Multiple Channel Digital Software Radio Transmitters (Wide-Band or Narrow-Band)

• Base Station Transceivers

• Operates with HSP50214 in Software Radio Solutions

• Compatible with the HI5741 D/A Converter

• HSP50215EVAL Evaluation Board Available

Ordering Information

PART

NUMBER

HSP50215VC 0 to 70 100 Ld MQFP Q100 .14x20 HSP50215VI -40 to 85 s100 Ld MQFP Q100 .14x20

TEMP

RANGE (oC) PACKAGE PKG. NO

Block Diagram

CAS(15:0)

CASZ

IIN(15:0) †

QIN(15:0) †

REFCLK

SYNCIN

RST

RD CE

C(15:0)

A(9:0)

CONTROL

3-422

FIFO

1-7 DEEP

MUX

MOD

QIN(15:0) † IIN(15:0) † CF(31:0) †

SF(29:0) †

† = µP CONTROL SIGNALS

IFIFO

QFIFO

MUX

SHAPING FILTER

IFM

Q FM

NCO

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

GAIN

CTRL

MUX

http://www.intersil.com or 407-727-9207

FILTER

INTERPOLATION

SIN NCO

CF(31:0) †

LIMITER

OUTPUT FORMATTER

COS

OUT(15:0)

OE OFM

SYNCOUT

FIFORDY SAMPCLK

Functional Block Diagram

CAS(1P5:0)

CASZ

3-423

REFCLK

RST

RD CE

C(15:0)

A(9:0)

MOD (1:0) †

IIN(15:0) †

QIN(15:0) †

CONTROL

RTH (2:0)†

RST †

FIFO

MOD

IFIFO

QFIFO

MUX

1-7 DEEP

MOD (1:0) † SR(29:0) †

ICOEFFICIENTS(15:0) † QCOEFFICIENTS(15:0) † CF(31:0) †

OUTGAIN (7:0)† EN OUT † DLYSEL †

DS (3:0)† IP (1:0)†

STATUS

MUX

MOD (1:0) †

COARSE PHASE

NCO

EnNCO

SHAPING

FILTER

I FM

Q FM

LIMITER

MOD (1:0) †

SET CLOSE TO LIMIT

MUX

GAIN

CTRL

(-2dBFS)

0.8 MAX

INTERPOLATION

FINE

PHASE

FILTER

(-3dBFS)

0.707

SIN

COS

NCO

EN_OUT †

SR CF EN_OUT MOD OUTGAIN FIFORDY IFIFOEMPTY QFIFOEMPTY

RTH EnNCO

SYNCPOL DS IP

OUT(15:0)

LIMITER

OUTPUT FORMATTER

OFM OE

HSP50215

FIFORDY SAMPCLK

SYNCIN

SYNCPOL † SYNCSEL †

SYNC

CW3 WR

SYNCOUT

† = µP CONTROL SIGNALS

Pinout

HSP50215

100 LEAD MQFP

TOP VIEW

OFM

CASZ CAS0 CAS1

GND CAS2 CAS3 CAS4

CAS5 CAS6 CAS7

GND

REFCLK

CAS8 CAS9

CAS10 CAS11

CAS12 CAS13 CAS14 CAS15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

OUT14

OUT15

99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100

OUT13

VCCOUT12

OUT10

OUT11

GND

OUT9

OUT8

VCCOUT7

OUT5

OUT6

GND

OUT4

OUT3

OUT2

OUT1

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

OUT0

C15 C14 C13

C12 C11 C10 C9 GND C8

C7 C6 C5 V

C4 SAMPCK C3 C2

GND C1 C0

SYNCOUT

32 33 34 35 36 37 38 40 42 44 46 47 48 50494543413931

GND

FIFORDY

GND

RST

SYNCIN

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HSP50215

Pin Descriptions

NAME TYPE DESCRIPTION

GND - Power supply ground input.

C(15:0) I/O µP Bidirectional Data bus. The C(15:0) bus is used for loading the conﬁguration data and sample vectors for mod-

A(9:0) I µP Address Bus. The A(9:0) bus is used for addressing the proper registers for loading the conﬁguration data and

WR I µP Write Strobe. When CE is asserted, data on the C(15:0) data bus is loaded into the address location found on

RD I µP Read Control. When RD and CE are low, the data found in the address location deﬁned by A(9:0) is routed to

CE I µP Chip Enable. Used to gate the WR and RD µP interface control signals.

FIFORDY O FIFO Ready. A FIFORDY assertion indicates that the I and Q FIFOs havereachedtheprogrammedFIFOdepthand

REFCLK I Reference Clock. REFCLK is the master clock for the DUC. All timing is relative to the REFCLK rising edge. The

CAS(15:0) I Cascade Input Bus. This input bus is used to cascade multiple parts by routing the digital modulated signal from

CASZ I Cascade Input Bus Zero. When CASZ is asserted (pulled high), the part places zeroes on the CAS(15:0) data path.

- +5V Power supply input.

ulation. C15 is the MSB.

sample vectors for modulation. A9 is the MSB.

the A(9:0) busontherisingedgeoftheWRsignal.Insomecases,thereisaninternalsynchronizationtothemaster clock that must be completed before the next data is written. See the µP interface section for more information.

the C(15:0) µP data bus on the next rising edge of REFCLK.

more samples are required to maintain that FIFO depth.

frequency of the reference clock is denoted f

one DUC into the output summer of a second DUC. CAS(15:0) is 2’s complement format and is sampled on the rising edge of REFCLK. CAS15 is the MSB.

CASZ is asynchronous (not registered) to REFCLK and should not be changed on the ﬂy.When unused, pull high with a pull up resistor (~22kΩ).

, and is the rate at which data is output from the part.

CLK

OUT(15:0) O Output Data Bus. OUT(15:0) contains the digital modulated DUC output samples and is updated on the rising edge

of the REFCLK. OUT15 is the MSB.

OFM I Output Data Bus Format. When OFM is asserted (pulled high), the output bus format is 2’s complement. When not

asserted, the output format is offset binary. The OFM input is asynchronous (not registered) to REFCLK and should not be changed on the ﬂy.

OE I Output Data Bus Enable.When OE is asserted (dropped low), the output data bus OUT(15:0) is enabled. When OE

is not asserted (pulled high), the output data bus OUT(15:0) is placed in the high impedance state.

SYNCIN I Sync Input. The SYNCIN input is used to synchronize the processing of multiple parts. The SYNCOUT of one part

acts as a master and is connected to the SYNCIN of all of the DUC’s that are to by synchronized. The DUC can be programmed so that either rising or falling edge of this signal initiates the processing.

SYNCOUT O Sync Output. The SYNCOUT output is used to synchronize the processing of multiple parts. The SYNCOUT of one

part acts as a master, and is connected to the SYNCIN of all of the DUC’s that are to be synchronized.

SAMPCLK O Sample Clock. This clock is provided to the data source to indicate when data is being transferred from the FIFO to

the shaping ﬁlter. The SAMPCLK output is generated by the sample rate NCO when the digital ﬁlter takes a new sample. It has approximately 50% duty cycle. The sample is taken on the high-to-low transition. SAMPCLK may be used instead of FIFORDY.

RST I Reset. When the RST input is asserted (dropped low), the DUC is reset and all processing halts. The DUC may

also be reset on µP command. Processing remains halted until a sync is generated either by µP command or assertion of SYNCIN. See the Reset section details of the specific functions halted by this control signal.

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HSP50215

Functional Description

The HSP50215 Digital UpConverter (DUC) converts digital baseband data into modulated or frequency translated digital samples. The DUC can be conﬁgured to create any quadrature amplitude shift-keyed (QASK) data modulated signal, including QPSK, BPSK, and m-ary QAM. The DUC can also be conﬁgured to create both shaped and unﬁltered FM signals. A minimum of 16 bits of resolution is maintained throughout the internal processing.

The DUC is conﬁgured via the 16-bit microprocessor data bus, using the address bus and signals. Conﬁguration data that is loaded via this bus includes the 30-bit Sample Rate NCO center frequency, the 32-bit Carrier NCO center frequency, the modulation format, gain control, FIFO control, reset control and sync control. The I and Q baseband channels each have a 256 tap FIR ﬁlter whose coefﬁcients and conﬁguration are also programmed via the µP interface. Similarly, the control signals for the I and Q channel interpolation ﬁlters are programmed via the µP interface. Once the operational conﬁguration for the device has been set, the 16-bitµP interfaceis used to input the I and Q data into the associated FIFOs.

The FIFOs provide the data interface between the µP and either the FM modulator or the shaping ﬁlters. Multiplexers route the I data to the FM modulator in the FM with bandlimiting ﬁlter mode. Both I and Q are routed to the 256 tap FIR shaping ﬁlters in the QASK mode. The shaping ﬁlter serves to both shape and interpolate the sample rate to 4, 8, or 16 times the input sample rate. The I shaping ﬁlter output can also be routed to the FM modulator for the FM with pulse shaping mode. Multiplexers select either the FM modulator output or the shaping ﬁlter output to be scaled and routed to the interpolation ﬁlters.

RD,WR and CE control

A(000)

IIN(15:0)

R E G

ZERO’S

A(2:0)

RTH(2:0)

FM ENABLED

QIN(15:0)

R E G

A(001) WR

DFF1 DFF2 DFF3 DFF4

R E G

WRITE SHIFT ENABLE

DFF1 DFF2 DFF3

R E G

R E

COMP

8:1 MUX

R E G

8:1 MUX

R E G

R E

† ALL REGISTERS

ARE CLOCKED AT

REFCLK UNLESS SHOWN OTHERWISE

R E G

DFF

R E G

DFF4

R E

R E G

IFIFO(15:0)

FIFORDY

QFIFO(15:0)

R E G

The I and Q interpolation filters allow a non-integer increase in sample rate, up to the reference clock r ate. The interpolation filter output data is upconverted or modulated by the Carrier NCO and multipliers. The modulated signal is added to modulated inputs from other cascaded DUC’s. The output formatter sets the output buffer state and the output data format.

Programmable FIFO

The Programmable FIFOs provide a data storage and interface between the microprocessor data write holding register and the shaping ﬁlter or the FM modulator. Signal routing out of the FIFO is set by the modulation format. Each FIFO has seven 16-bit registers. Figure 1 shows the conceptual details of the I and Q FIFOs.

3-426

FIGURE 1. I AND Q FIFO BLOCK DIAGRAM

REFCLK

DLY DATA

DFF 1

DFF 2

DFF 3

DFF 4

WR SHFT EN

REG1

FIFORDY

FIFO NEEDS MORE DATA

1234

FIGURE 2. FIFORDY AND DATA DELAY TIMING

FIFO NEEDS MORE DATA

HSP50215

Data enters the FIFO with a write command to either Control Word 0 (for I data), or Control W ord 1 (for Q data). This transfersdata from the microprocessor holding register into the first 16-bit register of the FIFO. The FIFO counter is incremented every time data is written into the FIFO. F our REFCLK periods are required from the rising edge of a WR signal before another WR rising edge can occur, (i.e ., bef ore data can once again be written into either the I or Q FIFO). This limits the maximum data input (write) rate to 52MHz/4 = 13MHz.

NOTE: The Write rate is not the parameter that determines the

maximuminput rate, the shaping filter is. Themaximum input for the shaping filter is 52MHz/(IP)(DS), which is 52MHz/16 =3.25 MHz for a minimal shaping filter (DS = IP=

4). See the Shaping Filter Section for more details.

The timing details of these FIFO registers are shown in Figure

2. While the data for the I and Q inputs are independent, the Write cycle limitations of the FIFO constrains the maximum input symbol rate of quadrature symbols (both I and Q data) as noted.

When the Shaping Filter requires another sample of data, a request is made to the FIFO for data and the FIFO counter is decremented. Figure 3 indicates the timing of a request for data from the Shaping filter to the actual appearance of data at the FIFO output. The FIFO has circuitry for detecting an empty FIFO as well as a full FIFO. An “empty” FIFO detection causes “zero” data to be entered into the shaping filter. A “full” FIFO detection prevents data from being pushed out of the FIFO before the filter requests it.

NOTE: Do not write to a full FIFO. Writing to a full FIFO is an er-

ror condition and the part will be reset to prevent transmission of erroneous data over the air.

A programmable FIFO depth threshold sets when the FIFORD Ysignal is asserted, alerting the data source that more data is required. The

FIFORD Y signal assists a data source in maintaining the desired FIFO data depth. Control Word 18, bits 0-2 are used to set the data FIFO depth threshold for both I and Q inputs.

NOTE: SAMPCLK may be used instead of FIFORDY to indicate

that data is transferred from the FIFO to the shaping filter. See the Pin Description Tab le.

with post-modulation ﬁltering, and 10:FM with premodulation pulse shaping. These modulation paths are deﬁned in the following subsections.

Modulation Mode 00 - QASK

This modulation mode conﬁgures the PUC as a BPSK, QPSK, OQPSK, MSK or m-QAM modulator. The ﬁlter conﬁguration is shown in Figure 4. The data FIFO outputs are routed to the shaping ﬁlters. Here the samples are interpolated by 4, 8, or 16 and shaped using a FIR ﬁlter with up to a 256 taps. The ﬁlter impulse response can span 4-16 input samples. A half (input) sample delay can be set in the I channel for implementing OQPSK modulation. The output of the shaping ﬁlter is routed through a gain adjust multiplier and into the interpolation ﬁlter. The interpolation ﬁlter interpolates by a factor set in the resampling NCO. The output of the interpolation ﬁlter is at the master clock frequency, REFCLK. The samples are then mixed with the carrier L.O. for quadrature upconversion. The output is then summed with the cascade input signal, saturated (in the case of overﬂow), and formatted for output.

SHAPING

FILTER

INTERPOLATION

FILTER

FIGURE 4. QASK

TO MODULATOR

Modulation Mode 01 - FM with BANDLIMITING Filter

This mode conﬁgures the PUC as an FM modulator with post-modulation ﬁltering. This mode provides for FSK and FM modulation schemes. In this mode, the I input samples drive the frequency control section of a quadrature NCO to produce a zero IF FM signal. The FM quadrature signals are then routed to the shaping FIR ﬁlter and into the interpolation ﬁlter for bandlimiting and interpolation up to the master clock rate as shown in Figure 5. The quadrature filtered FM signals are then upconverted to the carrier frequency by the carrier NCO and mixers. The output is then summed with the cascade input signal, saturated (in the case of overflow), and formatted for output. Note that pulse shaping in this mode must be provided prior to the PUC.

REFCLK

EnFIFO

IFIFO

FIGURE 3. FIFO DATA AND ENABLE TIMING

Data Modulation Path

Three data path options are provided, one for each modulation format. The modulation format is selected using Control Word 16 (See the Microprocessor Write section). Control Word 16 bits (1:0) are deﬁned as: 00:QASK, 01:FM

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MODULATOR

FIGURE 5. FM WITH BANDLIMITING

SHAPING

FILTER

INTERPOLATION

FILTER

Modulation Mode 10 - FM with Pulse Shaping

This mode conﬁgures the PUC as an FM modulator with premodulation baseband pulse shaping. The data from the FIFO (I channel only) is routed to the FIR shaping ﬁlter. The FIR shaping ﬁlter output drives the frequency control section

MODULATOR

HSP50215

of a quadrature NCO to produce a zero I.F.FM signal. These FM modulated quadrature samples are then up sampled in the interpolation ﬁlter to the output sample rate. The baseband modulated signal is then upconverted to the carrier frequency by the carrier NCO and mixers. The output is then summed with the cascade input signal, saturated, and formatted for output.

SHAPING

FILTER

FIGURE 6. FM WITH PULSE SHAPING

MODULATOR

INTERPOLATION

FILTER

In Mode 10, the amplitude out of the shaping ﬁlter needs to be limited in order to prevent frequency excursions that cannot be ﬁltered out in the interpolation ﬁlter. The quality of the FM signal is affected by the amplitude slew rate out of the shaping ﬁlter.As a rule of thumb, limiting this slew rate to less than 1/8 the sample rate will minimize this distortion.

FM Modulator

The FM modulator provides for frequency modulation of the carrier center frequency by the PUC input data. The FM modulator is driven either directly by the PUC I input (Mode

1) or by the output of the FIR shaping ﬁlter (Mode 2). The input data to the FM Modulator, is deﬁned as dφ(n)/dt, where φ(nT) is the phase of a theoretical sinusoid described by:

sn() A (cos φ nT()]+ j sin φ nT()[]); A ≈ 1 in Modulator[=

(EQ. 1)

modulator. The maximum phase step that can occur in one clock is ±180 degrees. Table 1 provides the change in phase weighting of the input bits.

TABLE 1. FM MODULATOR TRANSFER FUNCTION

dφ(nT)/dt DEGREES/SAMPLE

1000 0000 0000 0000 -180 0000 0000 0000 0000 0 0111 1111 1111 1111 ~+180

MODULATOR

Shaping Filter

The shaping ﬁlter provides the necessary pulse shaping required on the input data to implement various quadrature ASK and shaped FM modulation formats. Two identical shaping ﬁlters (one each for the I and Q channels) are provided. The ﬁlters can implement a 4-16 input sample span impulse response using up to 256 taps with 16 bits of resolution in the coefﬁcients.

The range of valid digital values for the coefﬁcients is from 8001 to 7FFF. The value 8000 is not allowed. The coefﬁcient format is 2’s complement. The span of the Impulse response of the polyphase ﬁlter can be from 4-16 samples. The desired sample span value minus one is programmed into the Data Samples (DS) ﬁeld in Control Word 19, bits 2-5. The ﬁlter has a programmable interpolation rate (IP) of 4, 8, or 16. This interpolation rate is programmed by Control Address 19, bits 0 and 1. Thus, the required number of coefﬁcients (or ﬁlter span) becomes

Figure 7 illustrates the conceptual design of the FM modulator. The input to the FM modulator, dφ(n)/dt, is integ rated via the carrier NCO accumulator. The NCO accumulator output represents phase and is used to address a SIN/COS generator, synthesizing a sinusoid of the form described in Equation 1. The phase accumulator feedback of the NCO is 16 bits and sixteen bits of the phase word are routed to the SIN/COS generator. Sixteen bits of resolution are provided on the Sine and Cosine outputs.

dφ(nT)/dt

EnNCO

MODE

1 OR 2

FIGURE 7. FM MODULATOR BLOCK DIAGRAM

∑

R E G

φ(nT)

ROM

SIN/COS

COS[φ(nT)]

SIN[φ(nT)]

The transfer function of the FM modulator is defined by the change in degrees per sample value, dφ(nT)/dt,where dφ(nT)/dt is a 16-bit, twos complement, fractionally notated frequency control word with a range from -F +F

SAMP

/2. F

is deﬁned as the sample rate into FM

SAMP

/2 to

# Coefﬁcients = (DS)(IP)

(EQ. 2)

with 256 being the maximum number of coefﬁcients. Note that

REFCLK DS()IP()fS()>

where f

is the input sample rate of the shaping ﬁlter. For a

(EQ. 3)

16 input sample impulse response span, the total impulse response is 64, 128 or 256 ﬁlter taps for interpolation rates of 4, 8 or 16, respectively. The ﬁlter structure precludes coefﬁcient re-use for symmetric ﬁlters, so both asymmetric and symmetric ﬁlters have up to 256 taps available and are loaded in identical manner.

The maximum input sample rate is:

fS=f

CLK

where f

[IP()⁄ DS()]

is the frequency of the reference clock, IP is the

CLK

(EQ. 4)

shaping ﬁlter interpolate rate; and DS is the number of data samples in the ﬁlter span. For example,if f

= 52MHz, the

CLK

ﬁlter span is 16 samples, and the interpolation rate is 16, then the maximum input sample rate, f

is 52/256 = 203kHz.

Table 2 shows severalexamples of calculations for FIR input sample rates based on master reference clock rate, number of data samples, and interpolation rate.

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