Intersil Corporation HSP48901 Datasheet

HSP48901

Data Sheet May 1999

3 x 3 Image Filter

The Intersil HSP48901 is a high speed 9-Tap FIR Filter which utilizes 8-bit wide data and coefﬁcients. It can be conﬁgured as a one dimensional (1-D) 9-Tap ﬁlter for a variety of signal processing applications, or as a two dimensional (2-D) ﬁlter for image processing. In the 2-D conﬁguration, the device is ideally suited for implementing 3 x 3 kernel convolution. The 30MHz clock rate allows a large number of image sizes to be processed within the required frame time for real-time video.

Data is provided to the HSP48901 through the use of programmable data buffers such as the HSP9500 or any other Programmable Shift Register. Coefﬁcient and pixel input data are 8-bit signed or unsigned integers, and the 20-bit extended output guarantees no overﬂow will occur during the ﬁltering operation.

There are two internal register banks for storing independent 3 x 3 ﬁlter kernels, thus, facilitating the implementation of adaptive ﬁlters and multiple ﬁlter operations on the same data.

The conﬁguration of the HSP48901 Image Filter is controlled through a standard microprocessor interface and all inputs and outputs are TTL compatible.

File Number

2459.5

Features

• DC to 30MHz Clock Rate

• Conﬁgurable for 1-D and 2-D Correlation/Convolution

• Dual Coefﬁcient Mask Registers, Switchable in a Single Clock Cycle

• Two’s Complement or Unsigned 8-Bit Input Data and Coefﬁcients

• 20-Bit Extended Precision Output

• Standard µP Interface

Applications

• Image Filtering

• Edge Detection/Enhancement

• Pattern Matching

• Real Time Video Filters

Ordering Information

TEMP.

PART NUMBER

RANGE (oC) PACKAGE

HSP48901JC-20 0 to 70 68 Ld PLCC N68.95 HSP48901JC-30 0 to 70 68 Ld PLCC N68.95 HSP48901GC-20 0 to 70 68 Ld PGA G68.A HSP48901GC-30 0 to 70 68 Ld PGA G68.A

PKG.

NO.

Block Diagram

DIN3 (0-7)

DIN2 (0-7)

DIN1 (0-7)

FRAME

CIN0-7

A0-2

CLK

HOLD

-1

CONTROL

LOGIC

ADDRESS DECODER

INTERNAL

CLOCK

GEN

MODE MODE

-1

+ + +

-1

2:1

-1

2:1

-1

ABCDEFGHI

-1

DOUT 0-19

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Pinouts

HSP48901

68 LEAD PLCC

TOP VIEW

DOUT3

A2A1A0

HOLD

DOUT4

DOUT5

4327 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

DOUT6

DOUT7

DOUT8

DOUT9

GND

DOUT10

DOUT11

DOUT12

DOUT13

DOUT14

DOUT15

DOUT16

DOUT17

DOUT18

DOUT19

FRAMES

DIN2 (7) DIN2 (6) DIN2 (5) DIN2 (4) DIN2 (3) DIN2 (2) DIN2 (1) DIN2 (0)

GND DIN3 (7) DIN3 (6) DIN3 (5) DIN3 (4) DIN3 (3)

DIN3 2) DIN3 (1) DIN3 (0)

VCCDIN1 (0)

DIN1 (1)

DIN1 (2)

DIN1 (3)

DIN1 (4)

DIN1 (5)

DIN1 (6)

DIN1 (7)

GND

DOUT0

DOUT1

DOUT2

9 8 7 6 5 4 3 2 1 6867666564636261

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

CLK

GND

CIN7

CIN6

CIN5

CIN4

CIN3

CIN2

CIN1

CIN0

GND

68 PIN GRID ARRAY (PGA)

TOP VIEW

DOUT6

DOUT7

DOUT9

DOUT10

DOUT12

DOUT14

DOUT16

DOUT18

DOUT5

DOUT3

DOUT1

GND

DIN1 (6)

DIN1 (4)

DIN1 (2)

DIN1 (0)

DOUT4

DOUT2

DOUT0

DIN1 (7)

DIN1 (5)

DIN1 (3)

DIN1 (1)

DIN2 (7)

DIN2 (6)

BCDEFGHJKLA

DOUT6

DIN2 (5)

DIN2 (4)

GND

DIN2 (3)

DIN2 (2)

DOUT11

DIN2 (1)

DIN2 (0)

DOUT13

GND

DIN2 (7)

DOUT15

DIN3 (6)

DIN3 (5)

DOUT17

DIN3 (4)

DIN3 (3)

DOUT19

DIN3 (2)

DIN3 (1)

FRAME

CIN0

CIN2

CIN4

CIN6

GND

DIN3 (0)

HOLD

GND

CIN1

CIN3

CIN5

CIN7

CLK

HSP48901

Pin Descriptions

NAME PLCC PIN TYPE DESCRIPTION

GND 18, 29, 38, 56 The device ground.

CLK 28 I Input and System clock. Operations are synchronous with therising edgeof this clock signal.

DIN1(7-0) 1-8 I Pixel Data Input Bus #1. These inputs are used to provide 8-bit pixel data to the HSP48901.

DIN2(7-0) 10-17 I Pixel Data Input Bus #2. Same as above. These inputs should be grounded when operating

DIN3(7-0) 19-26 I Pixel Data Input Bus #3. Same as above. These inputs should be grounded when operating

CIN7-0 30-37 I Coefficient Data Input Bus. This input bus is used to load the Coefficient Mask Register(s)

DOUT19-0 46-55, 57-60,

FRAME 44 I FRAME is an asynchronous new frame or vertical sync input. A low on this input resets all

HOLD 40 I The Hold Input is used to gate the clock from all of the internal circuitry of the HSP48901.

A2-0 41-43 I Control RegisterAddress. These linesare decodedto determine whichregister in thecontrol

LD 39 I Load Strobe. LD is usedfor loading the Internal Registers of theHSP48901. The rising edge

9, 27, 45, 61 The +5V power supply pins. 0.1µF capacitors between the VCC and GND pins are

recommended.

The data must be provided in a synchronous fashion, andis latched on the rising edge of the CLK signal. The DIN1(0-7) inputs are also used to input data when operating in the 9-Tap FIR mode.

in the 1D mode.

and the Initialization Register. The register to be loaded is defined by the register address bits A0-2. The CIN0-7 data is loaded to the addressed register through the use of the LD input.

O Output Data Bus. This 20-Bit output port is used to provide the convolution result. The result

62-67

is the sum of products of the input data samples and their corresponding coefficients.

internalcircuitry except for the Coefficientand INT Registers. Thus, aftera FRAME resethas occurred, a new frame of pixels may be convolved without reloading these registers.

This signal is synchronous, is sampled on the rising edge of CLK and takes effect on the following cycle. While this signal is active (high), the clock will have no effect on the HSP48901 and internal data will remain undisturbed.

logic is the destination for the data on the CIN0-7 inputs. Register loading is controlled by the A0-2 and LD inputs.

of LD will latch the CIN0-7 data into the register specified by A0-2. The Address on A0-2 must be setup with respect to the falling edge of LD and must be held with respect to the rising edge of LD.

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