Intersil Corporation HSP48410 Datasheet

HSP48410

Data Sheet May 1999

Histogrammer/Accumulating Buffer

The Intersil HSP48410 is an 84 lead Histogrammer IC
intended for use in image and signal analysis. The on-board
memory is configured as 1024 x 24 array. This translates to
a pixelresolutionof 10 bits and an image size of 4k x 4k with
no possibility of overflow.

In addition to Histogramming, the HSP48410 can generate
and store the Cumulative Distribution Function for use in
Histogram Equalization applications. Other capabilities of
the HSP48410 include: Bin Accumulation, Look Up Table,
24-bit Delay Memory, and Delay and Subtract mode.

A Flash Clear pin is available in all modes of operation and
performs a single cycle reset on all locations of the internal
memory array and all internal data paths.

The HSP48410 includes a fully asynchronous interface
which provides a means for communications with a host,
such as a microprocessor. The interface includes dedicated
Read/Write pins and an address port which are
asynchronous to the system clock. This allows random
access of the Histogram Memory Array for analysis or
conditioning of the stored data.

Ordering Information

TEMP.

PART NUMBER

HSP48410JC-33 0 to 70 84 Ld PLCC N84.1.15
HSP48410JC-40 0 to 70 84 Ld PLCC N84.1.15
HSP48410GC-33 0 to 70 84 Ld PGA G84.A
HSP48410GC-40 0 to 70 84 Ld PGA G84.A

RANGE (oC) PACKAGE

PKG.

NO.

File Number

3185.2

Features

• 10-Bit Pixel Data

• 4k x 4k Frame Sizes

• Asynchronous Flash Clear Pin

• Single Cycle Memory Clear

• Fully Asynchronous 16 or 24-Bit Host Interface

• Generates and Stores Cumulative Distribution Function

• Look Up Table Mode

• 1024 x 24-Bit Delay Memory

• 24-Bit Three State I/O Bus

• DC to 40MHz Clock Rate

Applications

• Histogramming

• Histogram Equalization

• Image and Signal Analysis

• Image Enhancement

• RGB Video Delay Line

Block Diagram

DIN0-23

PIN0-9

IOADD0-9

24

10

10

ADDRESS

GENERATOR

1

24

24

HISTOGRAM

MEMORY

ARRAY

DAT A

MUX

10

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

DAT A
IN

ADDRESS

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

OUT

24

ADDER

DIO

INTERACE

DIO0-23

Pinouts

HSP48410

84 PGA

TOP VIEW

PIN ‘A1’

ID

11

10

9

8

7

PIN9 DIN0 GND DIO12 DIO11DIO10

6

CC

PIN8 PIN7 PIN6 DIO7 GNDDIO6

5

PIN5 PIN4 DIO4 DIO5

4

PIN3 PIN1 FCT0 IOADD9 IOADD8 DIO1 DIO3

3

PIN2

2

START LD FCT1 GND IOADD5 IOADD7 IOADD4 IOADD IOADD1 V

PIN0

1

CLKDIN1V

FC RD FCT2 WR UWS IOADD6 IOADD3 IOADD0 DIO0 DIO2

BAGCDEF HJK L

DIN22 DIO23 DIO22 DIO19DIN13 DIN16 DIN17 DIN19DIN8 DIN10 DIN11

DIO20 DIO17DIN23 DIO21DIN12DIN7 DIN9DIN5 DIN21 DIN20DIN15

DIO18 DIO16DIN4 DIN6 GND DIN18DIN14

DIO15 DIO14DIN3DIN2

DIO8 DIO13DIO9

CC

84 PGA

BOTTOM VIEW

DIN22DIO23DIO22DIO19 DIN13DIN16DIN17DIN19 DIN8DIN10DIN11

DIO20DIO17 DIN23DIO21 DIN12 DIN7DIN9 DIN5DIN21DIN20 DIN15

DIO18DIO16 DIN4DIN6GNDDIN18 DIN14

DIO15DIO14 DIN3 DIN2

DIO8DIO13 DIO9

V

CC

CLK DIN1

LDFCT1GNDIOADD5IOADD7IOADD4IOADD2IOADD1

11

10

9

8

PIN9DIN0GNDDIO12DIO11 DIO10

V

PIN8PIN7PIN6DIO7GND DIO6

PIN5PIN4DIO4DIO5

PIN3PIN1FCT0IOADD9IOADD8DIO1DIO3

FCRDFCT2WRUWSIOADD6IOADD0DIO0DIO2 IOADD3

PIN2

PIN0START

CC

7

6

5

4

3

2

1

BAGCDEF HJK L

2

HSP48410

Pinouts

(Continued)

FC

RD

START

LD
FCT2
FCT1
FCT0

WR

GND

UWS
IOADD9
IOADD8
IOADD7
IOADD6
IOADD5
IOADD4
IOADD3
IOADD2
IOADD1
IOADD0

V

CC

84 LEAD PLCC

PIN0

PIN1

PIN2

PIN3

PIN4

PIN5

PIN6

111098765432184838281807978777675

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

PIN7

PIN8

CC

CLK

V

GND

PIN9

DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

DIN8

74

DIN9

73

DIN10

72

DIN11

71

DIN12

70

DIN13

69

DIN14

68

DIN15

67

DIN16

66

DIN17

65

GND

64

DIN18

63

DIN19

62

DIN20

61

DIN21

60

DIN22

59

DIN23

58

DIO23

57

DIO22

56

DIO21

55

DIO20

54

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

DIO6

DIO7

GND

DIO8

DIO9

DIO10

DIO11

DIO12

DIO13

DIO14

DIO15

DIO16

DIO17

DIO19

DIO18

3

HSP48410

Pin Description

NAME PLCC PIN TYPE DESCRIPTION

CLK 1 I Clock Input. This input has no effect on the chips functionality when the chip is programmed

to an asynchronous mode. All signals denoted as synchronous have their timing specified
with reference to this signal.

PIN0-9 3-11, 83 I Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on-chip RAM

with address values in Histogram, Bin Accumulate and LUT(write) mode. During Asynchro­nous modes it is unused.

LD 15 I The Load pin is used to load the FCT0-2 bits into the FCT Registers. (See below).

FCT0-2 16-18 I These three pins are decoded to determine the mode of operation for the chip. The signals

are sampled by the rising edge of LD and take effect after the rising edge of LD. Since the
loading of this function is asynchronous to CLK, it is necessary to disable the STARTpindur­ing loading and enable START at least 1 CLK cycle following theLD pulse.

START 14 I This pin informstheon-chipcircuitry which clock cycle will start and/or stop the current mode

of operation. Thus, the modes are asynchronously selected (via LD) but are synchronously
started and stopped. This input is sampled by the rising edge of CLK. The actual function of
this input depends on the mode that is selected. STARTmust always be held high (disabled)
when changing modes. This will provide a smooth transition from one mode to the next by
allowing the part to reconfigure itself before a new mode begins. When START is high,
LUT(read) mode is enabled except for Delay and Delay and Subtract modes.

FC 12 I Flash Clear. This input provides a fully asynchronous signal which effectively resets all bits

in the RAM Array and the input and output data paths to zero.

DIN0-23 58-63,

65-82

DIO0-23 33-40,

42-57

IOADD0-9 22-31 I RAM address in asynchronous modes. Sampled on the falling edge of WR or RD.

UWS 21 I Upper Word Select. In 16-bit Asynchronous mode, a one on this pin denotes the contents of

WR 19 I Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured in one

RD 13 I Read control for the data on DIO0-23 in asynchronous modes. Output enable for DIO0-23

V

CC

GND 20, 41, 64, 84 Ground

NOTES:

1. An overbar denotes an active low signal.

2. Bit 0 is the LSB on all busses.

2, 32 +5V. 0.1µF capacitors between the VCC and GND pins are recommended.

I Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT, Delay and

Delay and Subtract modes. Synchronous to CLK.

I/O Asynchronous Data Bus. Provides RAM access for a microprocessor in preconditioning the

memory array and reading the results of the previous operation. Configurable as either a 24
or 16-bit bus.

DIO0-7 as being the upper eight bitsof the data in or out ofthe Histogrammer. A zero means
that DIO0-15 are the lower 16 bits. In all other modes, this pin has no effect.

of the asynchronous modes. Asynchronous to CLK.

in other modes. Asynchronous to CLK.

4