Intersil Corporation HSP45116 Datasheet

HSP45116

Data Sheet May 1999

Numerically Controlled
Oscillator/Modulator

The Intersil HSP45116 combines a high performance
quadrature Numerically Controlled Oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a
complex vector to be multiplied by the internally generated
(cos, sin) vector for quadrature modulation and
demodulation. As shown in the Block Diagram, the
HSP45116 is divided into three main sections. The
Phase/Frequency Control Section (PFCS) and the
Sine/Cosine Section together form a complex NCO. The
CMAC multiplies the output of the Sine/ Cosine Section with
an external complex vector.

The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.008Hz at 33MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.

The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector
and can accumulate the result. The resulting complex vectors
are available through two 20-bit output ports which maintain
the 90dB spectral purity. This result can be accumulated
internally to implement an accumulate and dump filter.

A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be down converted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.

File Number

2485.7

Features

• NCO and CMAC on One Chip

• 15MHz, 25.6MHz, 33MHz Versions

• 32-Bit Frequency Control

• 16-Bit Phase Modulation

• 16-Bit CMAC

• 0.008Hz Tuning Resolution at 33MHz

• Spurious Frequency Components < -90dBc

• Fully Static CMOS

Applications

• Frequency Synthesis

• Modulation - AM, FM, PSK, FSK, QAM

• Demodulation, PLL

• Phase Shifter

• Polar to Cartesian Conversions

Ordering Information

TEMP.

PART NUMBER

HSP45116VC-15 0 to 70 160 Ld MQFP Q160.28x28
HSP45116VC-25 0 to 70 160 Ld MQFP Q160.28x28
HSP45116GC-15 0 to 70 145 Ld CPGA G145.A
HSP45116GC-25 0 to 70 145 Ld CPGA G145.A
HSP45116GC-33 0 to 70 145 Ld CPGA G145.A
HSP45116GI-15 -40 to 85 145 Ld CPGA G145.A
HSP45116GI-25 -40 to 85 145 Ld CPGA G145.A
HSP45116GI-33 -40 to 85 145 Ld CPGA G145.A
HSP45116GM-15/883 -55 to 125 145 Ld CPGA G145.A
HSP45116GM-25/883 -55 to 125 145 Ld CPGA G145.A
HSP45116AVC-52 0 to 70 160 Ld MQFP Q160.28x28

†This part has its own data sheet under HSP45116A, AnswerFAX
document no. 4156.

RANGE (oC) PACKAGE PKG. NO.

Block Diagram

MICROPROCESSOR

INTERFACE
INDIVIDUAL

CONTROL SIGNALS

1

VECTOR INPUT

RI

SINE/

PHASE/

FREQUENCY

CONTROL

SECTION

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

COSINE

ARGUMENT

http://www.intersil.com or 407-727-9207

SINE/

COSINE

SECTION

SIN

COS

VECTOR OUTPUT

CMAC

RI

| Copyright © Intersil Corporation 1999

Pinouts

A

HSP45116

145 PIN PGA

TOP VIEW

123456789101112131415

IMIN4IMIN8IMIN9IMIN11IMIN

V

CC

GND V

IMIN

16

15

CC

IO

IO

18

IO

15

12

GND

IO
10

V

CC

A

IMIN

GND

B

RIN

RIN

C

RIN

D

RIN10RIN14RIN

E

RIN RIN RIN

F

V

G

GND

H

RIN RIN RIN

J

RIN

K

L

M

REG

18

15

RIN

17

13

71112

RIN RIN

CC

RIN RIN

314

RIN

2

ACC

SH

0

PEAKENPH

1

5 7 10 13

23612

IMIN

INDEX

0

16

98

65

SH

0

1

RBYTILD

MOD

1

IMINIMINIMIN IMIN

IMINIMINIMINIMIN

IMIN

IMIN17IMIN18IO

IO
19

14

IO
16

17

11

14

IO

IO

13

8

IO

IO

9

6

IO

IO

RO

14

RO

RO

RO

RO

PACO

OEREXT OEI RO

7

4

3

0

9

8

5

1

5

IO

1

RO19RO

RO16RO

RO13RO

RO12RO

RO

7

RO

4

RO

2

DET1RO

2

RO

18

17

15

11

10

GND

V

CC

RO

6

3

0

B

C

D

E

F

G

H

J

K

L

M

IO

IO

IO

IO

IO

IO

OUT-

OUT-

C

MUX

2

1
C

C

3

6

C

C

5

7

MUX

0

C

1

C

4

OEIEXT

OER

C
0

ENOF

N

P

Q

BINFMT

REG

TICO PACI

V

CC

123456789101112131415

PMSEL

ENPHAC

GND GNDV

MOD

0

LOAD

CLROFR

ENI

ENCF

MODPI

REG

ENTIREGWRCS

CLK

/

AD

2PI

AD

0

1

CC

C

C

14

C

15

C

13

8

C

C

10

9

C

C

12

11

2

DET

0

GND

V

CC

N

P

Q

HSP45116

Pinouts

A

B

C

D

E

F

G

H

J

(Continued)

GND

V

CC

IO

IO

2

5

RO

RO

RO

RO

RO

GND

V

IO

18

17

15

11

10

CC

1

RO

19

RO

16

RO

13

RO

12

RO

7

RO

4

IO
10

IO

IO

IO

IO

RO

14

RO

RO

RO

145 PIN PGA

BOTTOM VIEW

123456789101112131415

GNDV

IMIN

IO

15

12

IO

7

4

3

0

9

8

5

IO

8

11

IO

IO

9

6

CC

18

IO

IO
16

IO
17

IO19IMIN

IMIN

18

14

IO
13

IO

IO

IMIN

16

15

14

IMIN IMIN IMIN IMIN

IMIN

17

IMIN

11

IMIN IMIN IMINIMIN

IMIN

9

INDEX

IMIN

8

571013

23612

IMIN

0

RIN

16

IMIN

V

4

IMIN

GND

1

RIN18RIN

RIN17RIN

RIN

RIN

14

RINRINRIN

RINRIN

V

98

RINRIN

GND

65

RINRINRIN

CC

A

B

C

15

D

13

E

10

F

71112

CC

G

H

314

J

K

L

M

N

P

Q

RO6RO

RO

3

0

DET

OEIEXT

0

GND

V

CC

2

DET

1

OER

C
0

PACO

OEREXTOEIRO

RO

1

OUT­MUX

0

C

1

C

4

OUT­MUX

1
C

3

C
5

RIN0RIN

SH

1

MOD

1

MOD

0

ACC

PEAK ENPH

BINFMT

ENOF

GNDGND V

RBYTILD

AD

C

C

C

C

8

2

C

C

6

9

C

C

7

11

14

13

C

C

15

10

C

12

AD

0

1

CC

MODPI

2PI

/

CS

WR

ENTIREG

ENCF

REG

CLK

LOAD

CLROFR

ENI

PMSEL

ENPHAC

2

SH

0

REG

REG

TICOPACI

V

CC

123456789101112131415

K

L

M

N

P

Q

3

HSP45116

Pinouts

IMIN0
RIN18
RIN17
RIN16
RIN15
RIN14

GND
RIN13
RIN12
RIN11
RIN10

RIN9
RIN8
RIN7
RIN6
RIN5
RIN4
RIN3
RIN2

GND

RIN1

RIN0

ACC

ENPHREG
ENOFREG

PEAK

RBYTILD

BINFMT

GND

TICO

MOD1
MOD0

PACI

LOAD

PMSEL

(Continued)

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

V

CC

23
24

SH1

25

SH0

26
27
28
29
30
31
32
33

V

34

CC

35
36
37
38
39

NC

40

160LEAD MQFP

TOP VIEW

CC

NC

V

159

160

1

41

42

IMIN3

IMIN2

GND

IMIN1

157

158

155

156

43444546474849505152535455565758596061626364656667686970717273747576777879

IMIN5

IMIN4

153

154

IMIN7

IMIN6

151

152

IMIN9

IMIN8

149

150

IMIN11

IMIN10

147

148

146

VCCIMIN12

145

GND

IMIN13

143

144

IMIN14

142

IMIN16

IMIN15

140

141

IMIN18

IMIN17

138

139

IO19

137

IO18

136

IO17

135

IO16

134

133

VCCIO15

132

GND

131

IO14

130

IO13

129

IO12

128

IO11

127

IO10

126

125

VCCGND

124

IO9

123

IO8

122

IO7

121

80

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103

102
101
100

NC
GND
IO6
IO5
IO4
IO3
GND
IO2
IO1
V

CC

IO0
RO19
GND
RO18
RO17
RO16
RO15
RO14
V

CC

RO13
RO12
RO11

99

GND

98

RO10

97

RO9

96

V

95

CC

RO8

94

RO7

93

GND

92

RO6

91

RO5

90

RO4

89

RO3

88

V

87

CC

RO2

86

RO1

85

RO0

84

GND

83

DET1

82

DET0

81

CLROFR

ENCFREG

ENPHAC

ENTIREG

4

ENI

MODPI/2PI

CS

GND

CLK

C9

C8

CC

WR

C15

C14

C13

C12

C11

V

AD1

AD0

C10

C7C6C5C4C3C2C1

GND

C0

OUTMUX1

OER

GND

OUTMUX0

CC

V

OEREXT

OEI

OEIEXT

NC

PACO

HSP45116

Pin Description

NAME NUMBER TYPE DESCRIPTION

V

CC

GND A8, A14, B1, H1,

C0-15 N8-11, P8-13,

AD0-1 N7, P7 I Address pins for selecting destination of C0-15 data.

CS P6 I Chip Select (active low).

WR Q6 I Write Enable. Data is clocked into the register selected byAD0-1 on the rising edge of WR when

CLK Q5 I Clock. All registers, except the control registers clocked with WR, are clocked (when enabled)

ENPHREG M1 I Phase Register Enable (active low). Registered on chip by CLK. When active, after being

ENOFREG N1 I Frequency Offset Register Enable (active Low). Registered on chip by CLK. When active, after

ENCFREG N5 I Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after

ENPHAC Q3 I Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after

ENTIREG P5 I Time Interval Control Register Enable (active low). Registered on chip by CLK. When active,

ENI Q4 I Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by

MODPI/2PI N6 I Modulo π/2π Select. When low, the Sine and Cosine ROMs are addressed modulo 2π (360

CLROFR P4 I Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,

LOAD N4 I Phase Accumulator Load Control (activelow). Registered on chip byCLK. Zeroes feedbackpath

MOD0-1 M3, N3 I External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90,

PMSEL P3 I Phase Modulation Select Line. This line determines the source of the data clocked into the phase

RBYTILD L3 I ROM Bypass, Timer Load. Active low, registered by CLK. This input bypasses the sine/ cosine

PACI P2 I Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to

A1, A9, A15, G1,

J15, Q1, Q7, Q15

H15, P15, Q2, Q8

Q9-14

- +5V Power supply input.

- Power supply ground input.

I Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.

the CS line is low.

by the rising edge of CLK.

clocked onto chip,ENPHREG enables the clocking of data into the phase register.

being clocked onto chip,ENOFREG enables clocking of data into the frequency offset register.

being clocked onto chip, ENCFREG enables clocking of data into the center frequency register.

being clocked onto chip,ENPHAC enables clocking of the phase accumulator register.

after being clocked onto chip, ENTIREG enables clocking of data into the time accumulator
register.

CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.

degrees). When high, the most significant address bit is held low so that the ROMs are
addressed modulo π (180 degrees). This input is registered on chip by clock.

after being clocked onto chip, CLROFR zeros the data path from the frequency offset register to
the frequency adder. New data can still be clocked into the frequency offset register; CLROFR
does not affect the contents of the register.

in the phase accumulator without clearing the phase accumulator register.

180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of
the phase control path are set to zero.

These bits are loaded into the phase register when ENPHREG is low.

register.When high, the phase control register is selected. When low, the external modulation pins
(MOD0-1) are selected for the most significant two bits and the least significant two bits and the
least significant 14 bits are set to zero. This control is registered by CLK.

ROM so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go
directly to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the timer
accumulator register by zeroing the feedback in the accumulator.

increment by one, in addition to the values in the phase accumulator register and frequency
adder.

5

HSP45116

Pin Description

NAME NUMBER TYPE DESCRIPTION

PACO L13 O Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output

TICO P1 O Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low

RIN0-18 C1, C2, D1, D2, E1-

IMIN0-18 A2-7, B2-7, C3-8,

SH0-1 K3, L1 I Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the

ACC L2 I Accumulate/Dump Control. This input controls the complex accumulators and their holding

BINFMT N2 I This input is used to convert the two’s complement output to offset binary (unsigned) for

PEAK M2 I This input enables the peak detect feature of the block floating point detector. When high, the

OUTMUX0-1 N12, N13 I These inputs select the data to be output on RO0-19 and IO0-19.

RO0-19 C15, D14, D15,

IO0-19 A10-13, B8-15, C9-

DET0-1 N15, L14 O Theseoutput pins indicate the number of bits of growth in the accumulators. While PEAK is low,

OER P14 I Three-state control for bits RO0-15. Outputs are enabled when the line is low.

OEREXT M13 I Three-state control for bits RO16-19. Outputs are enabled when the line is low.

OEI M14 I Three-state control for bits IO0-15. Outputs are enabled when the line is low.

OEIEXT N14 I Three-state control for bits IO16-19. Outputs are enabled when the line is low.

(Continued)

3, F1-3, G2, G3,

H2, H3, J1-3, K1,

K2

D3

E14, E15, F13-15,

G13-15, H13, H14,

J13, J14, K13-15,

L15, M15

14, D13, E13

indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has
been reached.

when a carryis generated by the time interval accumulator.This function is provided to time out
control events such as synchronizing register clocking to data timing.

I Real Input Data Bus. This is the external real component into the complex multiplier. The bus is

clocked into the real input data register by CLK when ENI is asserted; two’s complement.

I ImaginaryInput Data Bus. This is the external imaginary component into the complex multiplier.

The bus is clocked into the real input data register by CLK when ENI is asserted; two’s
complement.

complex multiplier. The shift controls are common to the shifters on both of the busses.

registers. When high, the accumulators accumulate and the holding registers are disabled.
When low, the feedback in the accumulators is zeroed to cause the accumulators to load.

The holding registers are enabled to clock in the results of the accumulation. This input is
registered by CLK.

applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal
two’s complement representation. This input is registered by CLK.

maximum bit growth in the output holding registers is encoded and output on the DET0-1 pins.
When the PEAK input is asserted,the block floating point detector output will track the maximum
growth in the holding registers, including the data in the holding registers at the time that PEAK
is activated.

O Real Output Data Bus. These Three-state outputs are controlled by OER and OEREXT.

OUTMUX0-1 select the data output on the bus.

O Imaginary Output Data Bus. These Three-state outputs are controlled by OEI and OEIEXT.

OUTMUX0-1 select the data output on the bus.

these pins indicate the peak growth. The detector examines bits 15-18, real and imaginary
accumulator holding registers and bits 30-33 of the real and imaginary CMAC holding registers.
The bits indicate the largest growth of the four registers.

6