Intersil Corporation HSP45106 Datasheet

HSP45106

Data Sheet October 1999

16-Bit Numerically Controlled Oscillator

The Intersil HSP45106 is a high performance 16-bit quadrature Numerically Controlled Oscillator (NCO16). The NCO16 simpliﬁes applications requiring frequency and phase agility such as frequency-hopped modems, PSK modems, spread spectrum communications, and precision signal generators. As shown in the block diagram, the HSP45106 is divided into a Phase/Frequency Control Section (PFCS) and a Sine/Cosine Section.

The inputs to the Phase/Frequency Control Section consist of a microprocessor interface and individual control lines. The frequency resolution is 32 bits, which provides for resolution of better than 0.008Hz at 33MHz. User programmable center frequency and offset frequency registers give the user the capability to perform phase coherent switching between two sinusoids of different frequencies. Further, a programmable phase control register allows forphasecontrolofbetter than 0.006 requiring up to 8-level PSK, three discrete inputs are provided to simplify implementation.

The output of the PFCS is a 28-bit phase which is input to the Sine/Cosine Section for conversion into sinusoidal amplitude. The outputs of the Sine/Cosine Section are two 16-bit quadrature signals. The spurious free dynamic range of this complex vector is greater than 90dBc.

For added ﬂexibility when using the NCO16 in conjunction with DAC’s, a choice of either parallel or serial outputs with either two’s complement or offset binary encoding is provided. In addition, a synchronization signal is available which indicates serial word boundaries.

. In applications

File Number 2809.5

Features

• 25.6MHz, 33MHz Versions

• 32-Bit Center and Offset Frequency Control

• 16-Bit Phase Control

• 8 Level PSK Supported Through Three Pin Interface

• Simultaneous 16-Bit Sine and Cosine Outputs

• Output in Two’s Complement or Offset Binary

• <0.008Hz Tuning Resolution at 33MHz

• Serial or Parallel Outputs

• Spurious Frequency Components <-90dBc

• 16-Bit Microprocessor Compatible Control Interface

Applications

• Direct Digital Synthesis

• Quadrature Signal Generation

• Spread Spectrum Communications

• PSK Modems

• Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK)

• Frequency Hopping Communications

• Precision Signal Generation

• Related Products

- Use with Data Acquisition Parts HI5731 or HI5741

Ordering Information

TEMP.

PART NUMBER

HSP45106JC-25 0 to 70 84 Ld PLCC N84.1.15 HSP45106JI-25 -40 to 85 84 Ld PLCC N84.1.15 HSP45106JC-33 0 to 70 84 Ld PLCC N84.1.15 HSP45106GC-33 0 to 70 85 Ld CPGA G85.A

RANGE (oC) PACKAGE PKG. NO.

Block Diagram

MICROPROCESSOR

INTERFACE

CLOCK

CONTROL SIGNALS

DISCRETE

SIN/COS

PHASE/

FREQUENCY

CONTROL

SECTION

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

ARGUMENT

1-888-INTERSIL or 407-727-9207

SINE/

COSINE

SECTION

SINE

COSINE

HSP45106

Pinouts

85 PIN CPGA

TOP VIEW

11 10 9 8 7 6 5 4 3 2 1

GND SIN1SIN0 SIN3

BINFMT V

INITP AC

PHAC ENTI

REG

ENCF

REG REG REG

CS GND

MOD2 MOD0

MOD1 A2 A1 C15 C12 C13 V

PAR/

SER

PACI

INITT

ENPO

TEST

CLK SIN2 V

INHOF

ENOF

SIN5 SIN4

SIN8

SIN6

SIN7

C10

C9 C6

SIN9

SIN10

SIN11

SIN12

GND

SIN13

SIN15

COS6

COS7

COS11

INDEX

SIN14

OES

OEC

COS2

COS4

COS8

COS10

GND

COS15

TICO

DAC

STRB

COS0

COS1

COS3

COS5

COS9

COS12

COS13

COS14

11 10 9 8 7 6 5 4 3 2 1

C0C0C0C0C0C0GNDA0

85 PIN CPGA

BOTTOM VIEW

DAC

STRB

COS0

COS1

COS3

COS5

COS9

COS12

COS13

SIN14

OES

OEC

COS2

COS4

COS8

COS10

GND

COS15

SIN13

SIN15

COS6

COS7

COS11

INDEX

SIN12

GND

SIN9

SIN10

SIN11

SIN8

SIN7

C9C6

SIN5SIN4

SIN6

C10

CLKSIN2V

INHOF

ENOF

PAR/

SER

PACI

INITT

ENPO

TEST

C0PMSEL

PIN ‘A1’

1110987654321

GNDSIN1 SIN0SIN3

BINFMTV

INITP AC

PHAC

ENTI REG

ENCF

REGREGREG

CSGND

MOD2MOD0

PIN ‘A1’

COS14

TICO

C0 C0 C0 C0 C0 C0 GND A0

MOD1A2A1C15C12C13V

PMSEL

1110987654321

HSP45106

Pinouts (Continued)

TICO COS15 COS14 COS13

GND COS12 COS11 COS10

COS9 COS8 COS7 COS6 COS5 COS4

COS3 COS2 COS1 COS0

OEC

DACSTRB

84 LEAD PLCC

TOP VIEW

C0C1C2C3C4C5C6

111098765432184838281807978777675

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

33 34 3536 3738 3940 41 4243 4445 4647 48 4950 5152 53

OES

SIN13

SIN14

SIN15

GND

SIN11

SIN12

VCCC7C8C9

SIN7

SIN8

SIN9

SIN10

C10

SIN6

C11

SIN5

C12

C13

SIN4

C14

SIN3

C15

GNDA0A1

SIN1

SIN2

SIN0

CLK

74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54

GND

PMSEL MOD0 MOD1 MOD2 TEST V

WR GND CS ENCFREG ENOFREG INHOFR ENTIREG INITTAC ENPOREG INPHAC PACI INITPAC BINFMT PAR/SER V

Pin Descriptions

NAME TYPE DESCRIPTION

GND Ground.

C(15:0) I Control input bus for loading phase, frequency, and timer data into the PFCS. C0 is LSB.

A(2:0) I Address pins for selecting destination of C(15:0) data (Table 2). A0 is the LSB

CS I Chip select (active low). Enables data to be written into Control Registers by WR.

WR I Write enable (active low). Data is clocked into the register selected by A(2:0) on the rising edge of WR when CS

CLK I Clock. All registers, excepttheControlRegistersclocked with WR, are clocked (when enabled) bytherisingedge

ENPOREG I PhaseOffsetRegister Enable (activelow).Registered on chip byCLK. When active,afterbeing clocked ontochip,

ENOFREG I Offset Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto

ENCFREG I Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto

ENPHAC I Phase Accumulator Register Enable (active low).Registeredonchipby CLK. When active, after being clockedonto

ENTIREG I Timer Increment Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto

INHOFR I Inhibit Offset FrequencyRegister Output (activelow). Registeredonchip byCLK.When active,afterbeing clocked

INITPAC I Initialize Phase Accumulator (active low). Registered on chip by CLK. Zeroes the feedback path in the Phase

MOD(2:0) I Modulation Control Inputs. When selected with the PMSEL line, these bits add an offset of 0, 45, 90, 135, 180,

+5 power supply pin.

is low.

of CLK.

ENPOREG enables the clocking of data into the Phase Offset Register. Allows ROM address to be updated regardless of ENPHAC.

chip, ENOFREG enables the clocking of data into the Offset Frequency Register.

chip, ENCFREG enables the clocking of data into the Center Frequency Register.

chip, ENPHAC enables the clocking of data into the Phase Accumulator Register.

chip, ENTIREG enables the clocking of data into the Timer Increment Register.

onto chip, INHOFR zeroes the data path from the Offset Frequency Register to the Frequency Adder. New data can be still clocked into the Offset Frequency Register.

INHOFR does not affect the contents of the register.

Accumulator. Does not clear the Phase Accumulator Register.

225, 270, or 315 degrees to the current phase (i.e., modulate the output). The lower 13 bits of the phase control are set to zero. These bits are registered when the Phase Offset Register is enabled.

HSP45106

Pin Descriptions (Continued)

NAME TYPE DESCRIPTION

PMSEL I Phase Modulation Select input. Registered on chip by CLK. This input determines the source of the data clocked

into the Phase Offset Register. When high, the Phase Input Register is selected. When low, the external modulation pins (MOD(2:1)) control the three most signiﬁcant bits of the Phase Offset Register and the 13 least signiﬁcant bits are set to zero.

PACI I Phase Accumulator Carry Input (active low). Registered on chip by CLK.

INITTAC I Initialize Timer Accumulator (active low).Thisinput is registered on chip by CLK.Whenactive, afterbeingclocked

onto chip, INITTAC enables the clocking of data into the Timer increment Register, and also zeroes the feedback path in the Timer Accumulator.

TEST I TestSelectInput.Registered on chip byCLK.This input is activehigh.When active, this inputenablestest busses

to the outputs instead of the sine and cosine data.

PAR/SER I Parallel/Serial Output Select. This input is registered on chip by CLK. When low, the sine and cosine outputs are

in serial mode. The Output Shift Registers will load in new data after ENPHAC goes low and will start shifting the data out after ENPHAC goes high. When this input is high, the Output Registers are loaded every clock and no shifting takes place.

BINFMT I Format. This input is registered on chip by CLK. When low, the MSB of the SIN and COS are inverted to form an

offset binary (unsigned) number. OES I Three-state control for bits SIN(15:0). Outputs are enabled when OES is low. OEC I Three-state control for bits COS(15:0). Outputs are enabled when OEC is low.

TICO O Timer Accumulator Carry Output. Active low, registered. This output goes low when a carry is generated by the

Timer Accumulator.

DACSTRB O DAC Strobe (active low). In serial mode, this output will go low when the ﬁrst bit of a new output word is valid at

the shift register output. This pin is active only in serial mode.

SIN(15:0) O Sine Output Data. When parallel mode is enabled, data is output on SIN(15:0). When serial mode is enabled,

output data bits are shifted out of SIN15 and SIN0. The bit stream on SIN15 is provided MSB ﬁrst while the bit

stream on SIN0 is provided LSB ﬁrst.

COS(15:0) O Cosine Output Data. When parallel mode is enabled, data is output on COS(15:0). When serial mode is enabled,

output data bits are shifted out of COS15 and COS0. The bit stream on COS15 is provided MSB ﬁrst while the bit

stream in COS0 is provided LSB ﬁrst.

Index Pin Used to align chip in socket or on circuit board. Must be left as a no connect in circuit. (CPGA Package only).

Functional Description

The 16-bit Numerically Controlled Oscillator (NCO16) produces a digital complex sinusoid waveform whose frequency and phase are controlled through a standard microprocessor interface and discrete inputs. The NCO16 generates 16-bit sine and cosine vectors at a maximum sample rate of 33MHz. The NCO16 can be preprogrammed to produce a constant (CW) sine and cosine output forDirect Digital Synthesis (DDS) applications. Alternatively, the phase and frequency inputs can be updated in real time to produce a FM, PSK, FSK, or MSK modulated waveform. To simplify PSK generation, a 3 pin interface is provided to support modulation of up to 8 levels.

As shown in Figure 1, the HSP45106 Block Diagram, the NCO16 is comprised of a Phase and Frequency Control Section (PFCS) and Sine/ Cosine Section. The PFCS stores the phase and frequency control inputs and uses them to calculate the phase angle of a rotating complex vector. The Sine/Cosine Section performs a lookup on this phase and generates the appropriate amplitude values for the sine and cosine. These quadrature outputs may be conﬁgured as serial or parallel with either two's complement or offset binary format.

Phase/Frequency Control Section

The phase and frequency of the quadrature outputs are controlled by the PFCS (Figure 1). The PFCS generates a 32-bit word which represents the instantaneous phase (Sin/Cos argument) of the sine and cosine waves being generated. This phase is incremented on the rising edge of each CLK by the preprogrammed amounts in the phase and Frequency Control Registers. As the instantaneous phase steps from 0 through full scale (2 quadrature outputs proceeds from 0 counter clockwise.

The PFCS is comprised of a Phase Accumulator Section, Phase Offset adder, Input Section, and a Timer Accumulator Section. The Phase Accumulator computes the instantaneous phase angle from user programmed values in the Center and Offset Frequency Registers. This angle is then fed into the Phase Offset adder where it is offset by the preprogrammed value in the Phase Offset Register. The Input Section routes data from a microprocessor compatible control busanddiscreteinputsignalsinto the appropriate configuration registers. The Timer Accumulator supplies a pulse to mark the passage of a user programmed period of time.

- 1), the phase of the

around the unit circle

SIN(15:0)

DACSTRB

COS(15:0)

OUTPUT

CONTROL

FORMAT

CONTROL

16 COS

16 SIN

SIN/COS

DECODE ROM

ADDRESS

SIN/COS ARGUMENT

ADD

ADDER

PHASE OFFSET

MUX

PHASE INPUT

ENCODER

LSBs

CLK

0 1

'0'

CLK

MSBs

FREQUENCY

R.ENPOREG

CENTER

FREQUENCY

R.PMSEL

CENTER

ADDER

FREQUENCY

HSP45106

CLK

ADD

CLK

R.ENCFREG

OFFSET FREQUENCY

OFFSET

PHASE

ACCUMULATOR

FREQUENCY

PHASE

ACCUMULATOR

MUX

0 1

'0'

MUX

0 1

'0'

R.INHOFR

CLK

R.ENOFREG

SECTION

R.P ACI

R.INITPAC

R.ENPHAC

TIMER

TICO

CLK

ADD

TIMER

INCREMENT

INCREMENT CLK

CLK

MUX

0 1

'0'

R.INITTAC

R.ENTIREG

TIMER

ACCUMULATOR

SECTION

R.INITTAC

OES

OEC

FIGURE 1. BLOCK DIAGRAM OF THE HSP45106

LSB

REG (16)

PHASE

INPUT REG (16)

AND PROCESSOR CONTROL INTERF A CE)

INPUT SECTION (DISCRETE CONTROL INPUT SIGNALS

MSB CENTER

PHEN

CENTER

FREQUENCY INPUT

FREQUENCY

INPUT REG (16)

MSB OFFSET

FREQUENCY INPUT

LSCFEN

REG (16)

LSB OFFSET

FREQUENCY

INPUT REG (16)

LSOFEN

INPUT REG (16)

MSB TIMER INCREMENT

REG (16)

LSB TIMER

INCREMENT INPUT

LSTIEN

MSTIEN

CLK

PHEN

MSCFEN

LSCFEN

MSOFEN

LSOFEN

MSTIEN

LSTIEN

DECOD

TEST

R.ENPHAC

BINFMT

PAR/SER

C(15:0)

MOD(2:1)

A(2:0)

R.PMSEL

R.ENCFREG

PMSEL

ENCFREG

R.ENOFREG

R.INHOFR

INHOFR

ENOFREG

ENPOREG R.ENPOREG

R.ENPHAC

R.ENTIREG

R.INITPAC

R.PACI

R.INITTAC

PACI

INITPAC

ENPHAC

INITTAC

ENTIREG

CLK

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