intersil HSP45102 DATA SHEET

®

www.BDTIC.com/Intersil

HSP45102

Data Sheet April 25, 2007 FN2810.9

12-Bit Numerically Controlled Oscillator

The Intersil HSP45102 is Numerically Controlled Oscillator
(NCO12) with 32-bit frequency resolution and 12-bit output.
With over 69dB of spurious free dynamic range and worst
case frequency resolution of 0.009Hz, the NCO12 provides
significant accuracy for frequency synthesis solutions at a
competitive price.

The frequency to be generated is selected from two frequency
control words. A single control pin selects which word is used
to determine the output frequency. Switching from one
frequency to another occurs in one clock cycle, with a 6 clock
pipeline delay from the time that the new control word is
loaded until t4-he new frequency appears on the output.

Two pins, P0-1, are provided for phase modulation. They are
encoded and added to the top two bits of the phase
accumulator to offset the phase in 90° increments.

The 13-bit output of the Phase Offset Adder is mapped to the
sine wave amplitude via the Sine ROM. The output data
format is offset binary to simplify interfacing to D/A
converters. Spurious frequency components in the output
sinusoid are less than -69dBc.

The NCO12 has applications as a Direct Digital Synthesizer
and modulator in low cost digital radios, satellite terminals,
and function generators.

Features

• 33MHz, 40MHz Versions

• 32-Bit Frequency Control

• BFSK, QPSK Modulation

• Serial Frequency Load

• 12-Bit Sine Output

• Offset Binary Output Format

• 0.009Hz Tuning Resolution at 40MHz

• Spurious Frequency Components <-69dBc

• Fully Static CMOS

•Low Cost

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Direct Digital Synthesis

• Modulation

• PSK Communications

• Related Products

- HI5731 12-Bit, 100MHz D/A Converter

Ordering Information

TEMP.

PART NUMBER PART MARKING

HSP45102SC-33 HSP45102SC-33 0 to +70 28 Ld SOIC (300 mil) M28.3
HSP45102SC-33Z (Note) HSP45102SC-33Z 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3
HSP45102SC-40 HSP45102SC -40 0 to +70 28 Ld SOIC (300 mil) M28.3
HSP45102SC-40Z (Note) HSP45102SC-40Z 0 to +70 28 Ld SOIC (300 mil)(Pb-free) M28.3
HSP45102SI-3396 HSP45102SI -33 0 to +70 28 Ld SOIC (300 mil) (Tape and Reel) M28.3
HSP45102SI-33Z (Note) HSP45102SI-33Z 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

RANGE (°C) PACKAGE

PKG.

DWG. #

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 1999, 2004, 2005, 2007. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Block Diagram

www.BDTIC.com/Intersil

Pinout

CLK

PO-1

MSB/LSB

SFTEN

SD

SCLK

FREQUENCY

CONTROL

SECTION

LOAD

TXFR

ENPHAC

SEL_L/M

HSP45102

32
32

PHASE

ACCUMULATOR

HSP45102

(28 LEAD SOIC)

TOP VIEW

PHASE

OFFSET

13

ADDER

13 12

SINE
ROM

OUT0-11

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

GND

V

CC

SEL_L/ M

SFTEN

MSB/LSB

ENPHAC

SD

SCLK

OUT5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

OUT4

26

OUT3

25

OUT2

24

OUT1

23

OUT0

22

V

CC

21

GND

20

P0

19

P1

18

LOAD

17

TXFR

16

CLK

15

GND

2

FN2810.9

April 25, 2007

HSP45102

www.BDTIC.com/Intersil

Pin Description

NAME TYPE DESCRIPTION

V

CC

GND Ground
P0-1 I Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift of 0°, 90°,

CLK I NCO clock. (CMOS level)

SCLK I This pin clocks the frequency control shift register.

SEL_L/M

SFTEN

MSB/LSB

ENPHAC

SD I Data on this pin is shif te d int o th e fr equency regist er by the rising e dge of SCLK when SFTEN

TXFR

LOAD

OUT0-11 O Output data. OUT0 is LSB. Unsigned.

All inputs are TTL level, with the exception of CLK.

designates active low signals.

Overline

I A high on this input selects the least significant 32 bits of the 64-bit frequency register as the input to

I The active low input enables the shifting of the frequency register.
I This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB

I This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of

I This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four

I This input becomes active after a pipeline delay of five clocks. When low, the feedback in the phase

+5V power supply pin.

180°, or 270° can be selected as shown in Table 1.

the phase accumulator; a low selects the most significant 32 bits.

first; a high shifts in the data MSB first.

four clocks.

clocks. When low, the frequency control word selected by SEL_L/M
register to the phase accumulator’s input register.

accumulator is zeroed.

is transferred from the frequency

is low.

3

FN2810.9

April 25, 2007