Intersil Corporation HSP43891 Datasheet

HSP43891

Data Sheet May 1999

Digital Filter

The HSP43891 is a video-speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells
cascaded internally and a shift and add output stage, all in
a single integrated circuit. Each filter cell contains a 9x9
two’scomplementmultiplier,three decimation registers and
a 26-bit accumulator. The output stage contains an
additional 26-bit accumulator which can add the contents of
any filter cell accumulator to the output stage accumulator
shifted right by 8-bits. The HSP43891 has a maximum
sample rate of 30MHz. The effective multiply-accumulate
(mac) rate is 240MHz.

The HSP43891 DF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded
for larger filter lengths without degrading the sample rate or
a single DF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter
coefficients are less than 1.0, making even larger filter
lengths possible. The DF provides for 8-bit unsigned or
9-bit two’s complement arithmetic, independently
selectable for coefficients and signal data.

Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates

1

of

/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and NxN spatial
correlations/convolutions for image processing applications.

File Number

2785.5

Features

• Eight Filter Cells

• 0MHz to 30MHz Sample Rate

• 9-Bit Coefficients and Signal Data

• 26-Bit Accumulator per Stage

• Filter Lengths Over 1000 Taps

• Expandable Coefficient Size, Data Size and Filter Length

• Decimation by 2, 3 or 4

Applications

• 1-D and 2-D FIR Filters

• Radar/Sonar

• Digital Video

• Adaptive Filters

• Echo Cancellation

• Complex Multiply-Add

- Sample Rate Converters

Ordering Information

TEMP.

PART NUMBER

HSP43891VC-20 0 to 70 100 Lead MQFP Q100.14x20
HSP43891VC-25 0 to 70 100 Lead MQFP Q100.14x20
HSP43891VC-30 0 to 70 100 Lead MQFP Q100.14x20
HSP43891JC-20 0 to 70 84 Lead PLCC N84.1.15
HSP43891JC-25 0 to 70 84 Lead PLCC N84.1.15
HSP43891JC-30 0 to 70 84 Lead PLCC N84.1.15
HSP43891GC-20 0 to 70 85 Pin CPGA G85.A
HSP43891GC-25 0 to 70 85 Pin CPGA G85.A
HSP43891GC-30 0 to 70 85 Pin CPGA G85.A

RANGE (oC) PACKAGE PKG. NO.

Block Diagram

VCCV

DIENB
CIENB

DCM0 - 1

ERASE

CIN0 - 8

RESET

ADRO - 2

RESET

SHADD

SENBL

SENBH

CLK

CLK

5

DF
FILTER
CELL 0

5

5

3

ADR0, ADR1, ADR2

2

DF
FILTER
CELL 1

1

DIN0 - DIN8

9

9

26

DF
FILTER
CELL 2

26

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

FILTER

9

CELL 3

SUM0 - 25

DF

26

MUX

26

OUTPUT

STAGE

DF

FILTER

9

CELL 4

26

26

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

DF

FILTER

9

CELL 5

26

DF

FILTER

9

CELL 6

26

DF

FILTER

9

CELL 7

9

26

COUT0 - 8

COENB

SS

99

26

2

Pinout

HSP43891

85 PIN GRID ARRAY (PGA)

2173 4 5 6 8 9 10 11

V

RESET

A

V

SS

B

VCCCOUT7 ERASE DIN1 DIN2

C

COUT5 COUT6

D

COUT3 COUT4

E

COUT1

V

F

SS

G

ADR2 DCM0 CLK

H

ADR1

V

J

CC

SENBH

K

L

CC

COENB

COUT8 DIN8

ALIGN

PIN

COUT2

V

SS

COUT0 SHADD

SUM25

V

SUM24

SS

DIN7

DIENB

HSP43891

V

SUM19

CC

TOP VIEW

PINS DOWN

SUM14SUM18SUM21SUM22SUM23DCM1

SUM23
SUM22

V
SUM21
SUM20
SUM19
SUM18

V
SUM17
SUM16

V
SUM15
SUM14
SUM13
SUM12

V
SUM11
SUM10

SUM9
SUM8
SUM7

1234567891011

V

DIN6 DIN3 DIN0 CIN8

CIENB

DIN5 DIN4 CIN5 CIN3

SUM16SUM17SUM20

SUM15 SUM12 SUM10 SUM8 SUM6

V

SS

SUM13

V

CC

V

CC

CIN7 CIN6 CIN4

CIN2

CIN0

CIN1

V

CCVSS

SUM0

SUM3 SUM2

SUM1

SUM5 SUM4ADR0

SUM7

V

SS

SS

V

CC

SENBL

V

SS

SUM9SUM11

L

DCM1SUM23SUM22 SUM21SUM18 SUM14 SUM13 SUM11 SUM9

K

SENBH SUM24 SUM19 SUM15 SUM12 SUM10 SUM8 SUM6

J

V

SUM25

CC

H

G

F

E

D

C

B

A

ADR0

ADR1

ADR2 DCM0 CLK

V

COUT0 SHADD

SS

V

COUT1

COUT3COUT4

COUT5COUT6

V

CC

V

COENB

SS

84 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)

SS

V

DCM1

SUM24

SENBH

SUM25

111098765432184838281807978777675

12
13
14

CC

15
16
17
18
19

SS

20
21
22

CC

23
24
25
26
27

SS

28
29
30
31
32

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

SS

DCM0

ADDR1

VCCADDR0

V

HSP43891

TOP VIEW

ADDR2

CLK

COUT0

SHADD

COUT1

VSSCOUT3

SS

COUT2

VSSV

COUT2

ALIGN

PIN

V

CC

COUT4

V

CC

CC

V

SS

SUM20 SUM17 SUM16 SUM7

HSP43891

BOTTOM VIEW

PINS UP

DIENB

DIN5 DIN4

ERASECOUT7 DIN8COUT8

RESET

CC

COUT5

V

74

COUT6
COUT7

73

V

72

SS

COUT8

71

COENB

70

V

69

CC

ERASE

68

RESET

67

DIENB

66

DIN8

65

DIN7

64

DIN6

63

DIN5

62

DIN4

61

DIN3

60

DIN2

59

DIN1

58

DIN0

57

CIENB

56

CIN8

55

V

CC

54

DIN2DIN1

V

SUM1 SUM3 SUM2

SUM0

CIN1 CIN0

CIENB

CIN8

DIN0DIN3DIN6DIN7

SS

SUM5 SUM4

V

V

CCVSS

SENBL

V

CIN2

CIN5 CIN3

CIN4CIN6CIN7

V

CCVSS

SS

CC

V

SUM6

SS

SUM4

SUM5

CC

V

SUM3

SUM1

SUM2

SS

V

SUM0

CIN0

SENBL

CIN1

CIN3

CIN4

CIN5

SS

V

CIN7

CIN6

CC

V

CIN2

2

HSP43891

Pinout

(Continued)

DCM1

SUM24

V

SS

V

SS

SUM23
SUM22

V

CC

V

CC

SUM21
SUM20
SUM19
SUM18

V

SS

V

SS

SUM17
SUM16

V

CC

V

CC

SUM15
SUM14
SUM13
SUM12

V

SS

SUM11
SUM10

SUM9
SUM8
SUM7

NC

SUM6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

SUM25

SENBH

99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100

CCVCC

V

100 LEAD MQFP

TOP VIEW

SSVSS

V

ADDR1

ADDR0

ADDR2

DCM0

CLK

CC

SHADD

VCCV

COUT1

COUT0

SSVSS

V

COUT3

COUT2

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

COUT4
COUT5
V

CC

V

CC

COUT6
COUT7
V

SS

V

SS

COUT8
COENB

V

CC

V

CC

ERASE
RESET
DIENB
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
CIENB
CIN8
V

CC

CIN7
CIN6
V

SS

SS

32 33 34 35 36 37 38 40 42 44 4647 48 50494543413931

SUM5

SUM4

V

CC

SUM3

SUM2

SUM1

VSSV

VSSV

SUM0

SS

SENBL

CIN0

CIN1

CC

V

CIN2

CIN3

CIN4

CIN5

SS

V

3

HSP43891

Pin Description

PIN

SYMBOL

V

CC

V

SS

CLK G3 I The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz.

DIN0-8 A5-8,B5-7, C6,

DIENB C5 I A low on this input enables the data sample input bus (DIN0-8) to all the filter cells. A rising edge of the

CIN0-8 A9,B9-11, C10,

ALIGN PIN C3 Used for aligning chip on socket or printed circuit board. This pin must be left as a no connect in circuit.

CIENB B8 I A low on this input enables the C register of every filter cell and the D (decimation) registers of every

COUT0-8 B2, B3, C1, D1,

COENB A2 I Alow on the COENB input enables the COUT0-8 outputs. A high on this input places all these outputs

DCM0-1 L1, G2 I These two inputs determine the use of the internal decimation registers as follows:

NUMBER TYPE NAME AND FUNCTION

B1, J1, A3, K4,

L7, A10, F10,

D11

A1, F1, E2, K3,

K6, L9, A11,

F11, J11

C7

C11, D10, E9,

E10

E1, C2, D2, F2,

E3

+5 power supply input.

Power supply ground input.

I These nine inputs are the data sample input bus. Nine-bit data samples are synchronously loaded

through these pins to the X register of each filter cell of the DF simultaneously. The DIENB signal en­ables loading, which is synchronous on the rising edge of the clock signal.

The data samples can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s com­plement values, DIN8 is the sign bit. For 8-bit unsigned values, DIN8 must be held at logical zero.

CLK signal occurring while DIENB is low will load the X register of every filter cell with the 9-bit value
present on DIN0-8. A high on this input forces all the bits of the data sample input bus to zero; a rising
CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This signal is
latched inside the device, delaying its effect by one clock internal to the device.Therefore it must be low
during the clock cycle immediately preceding presentation of the desired data on the DIN0-8 inputs.De­tailed operation is shown in later timing diagrams.

I These nine inputs are used to input the 9-bit coefficients. The coefficients are synchronously loaded

into the C register of filter CELL0 if a rising edge of CLK occurs while CIENB is low. The CIENB signal
is delayed by one clock as discussed below.

The coefficients can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s comple­ment values, CIN8 is the sign bit. For 8-bit unsigned values, CIN8 must be held at logical zero.

filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while
CIENB is low will load the C register and appropriate D registers with the coefficient data present at
their inputs. This provides the mechanism for shifting coefficients from cell to cell through the device. A
high on this input freezes the contents of the C register and the D registers, ignoring the CLK signal.
This signal is latched and delayed by one clock internal to the DF. Therefore it must be low during the
clockcycle immediately preceding presentation of the desired coefficient on the CIN0-8 inputs. Detailed
operation is shown in later timing diagrams.

O Thesenine three-state outputs are used to output the 9-bit coefficients from filter CELL7. These outputs

are enabled by the COENB signal low. These outputs may be tied to the CIN0-8 inputs of the same DF
to recirculate to coefficients, or they may be tied to the CIN0-8 inputs of another DF to cascade DFs for
longer filter lengths.

in their high impedance state.

DCM1 DCM0 DECIMATION FUNCTION

0 0 Decimation registers not used
0 1 One decimation register is used
1 0 Two decimation registers are used
1 1 Three decimation registers are used

The coefficients pass from cell to cell at a rate determined by the number of decimation registers used.
When no decimation registers are used, coefficients move from cell to cell on each clock. When one
decimation register is used, coefficients move from cell to cell on every other clock, etc. These signals
are latched and delayed by one clock internal to the device.

4

HSP43891

Pin Description

SYMBOL

SUM0-25 F9, G9-G11,

H10, H11, J2,

J5-J7, J10, K2,

K5, K7-K11,

L2-L6, L8, L10,

SENBH K1 I A low on this input enables result bits SUM16-25. A high on this input places these bits in their high

SENBL E11 I A low on this input enables result bits SUM0-15. A high on this input places these bits in their high im-

ADR0-2 G1, H1, H2 I These three inputs select the one cell whose accumulator will be read through the output bus (SUM0-

SHADD F3 I The SHADD input controls the activation of the shift and add operation in the output stage. This signal

RESET A4 I A low on this input synchronously clears all the internal registers, except the cell accumulators It can

ERASE B4 I A low on this input synchronously clears the cell accumulator selected by the ADR0-2 signals. If RESET

(Continued)

PIN

NUMBER TYPE NAME AND FUNCTION

O These26 three-state outputs are used to output the results of the internal filter cell computations. Indi-

vidual filter cell results or the result of the shift and add output stage can be output. If an individual filter
cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal determines
whether the selected filter cell result or the output stage adder result is output. The signals SENBH and
SENBL enable the most significant and least significant bits of the SUM0-25 result respectively. Both

L11

SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or larger bus. However
individual enables are provided to facilitate use with a 16-bit bus.

impedance state.

pedance state.

25) or added to the output stage accumulator. They also determine which accumulator will be cleared
when ERASE is low.These inputs are latched in the DF and delayed by one clock internal to the device.
If ADR0-2 remains at the same address for more than one clock, the output at SUM0-25 will not change
to reflect any subsequent accumulator updates in the addressed cell. Only the result available during
the first clock, when ADR0-2 selects the cell, will be output. This does not hinder normal operation since
the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories
where the output is required to be fixed for more than one clock.

is latched on chip and delayed by one clock internal to the device. Detailed explanation is given in the
DF Output Stage section.

be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in the DF
and delayed by one clock internal to the device.

is also low simultaneously, all cell accumulators are cleared.

Functional Description

The Digital Filter Processor (DF) is composed of eight filter
cells cascaded together and an output stage for combining
or selecting filter cell outputs (See Block Diagram). Each
filter cell contains a multiplier-accumulator and several
registers (Figure 1). Each 9-bit coefficient is multiplied by a
9-bit data sample, with the result added to the 26-bit
accumulator contents. The coefficient output of each cell is
cascaded to the coefficient input of the next cell to its right.

DF Filter Cell

A 9-bit coefficient (CIN0-8) enters each cell through the C
register on the left and exits the cell on the right as signals
COUT0-8. With no decimation, the coefficient moves directly
from the C register to the output, and is valid on the clock
following its entrance. When decimation is selected the
coefficient exit is delayed by 1, 2 or 3 clocks by passing
through one or more decimation registers (D1, D2 or D3).

The combination of D registers through which the coefficient
passes is determined by the state of DCM0 and DCM1. The
output signals (COUT0-8) are connected to the CIN0-8
inputs of the next cell to its right. The
enables the COUT0-8 outputs of the right most cell to the
COUT0-8 pins of the device.

COENB input signal

The C and D registers are enabled for loading by
Loading is synchronous with CLK when
that

CIENB is latched internally. It enables the register for

CIENB is low. Note

loading after the next CLK following the onset of

CIENB.

CIENB low.
Actual loading occurs on the second CLK following the onset
of

CIENB low. Therefore CIENB must be low during the clock
cycle immediately preceding presentation of the coefficient
on the CIN0-8 inputs. In most basic FIR operations,

CIENB
will be low throughout the process, so this latching and delay
sequence is only important during the initialization phase.
When

CIENB is high, the coefficients are frozen.

The C and D registers are cleared synchronously under control
of

RESET, which is latched and delayed exactly like CIENB.
The output of the C register (C0-8) is one input to 9 x 9
multiplier.

The other input to the 9 x 9 multiplier comes from the output
of the X register. This register is loaded with a data sample
from the device input signals DIN0-8 discussed above. The
X register is enabled for loading by
synchronous with CLK when

DIENB. Loading is

DIENB is low.Note that DIENB
is latched internally. It enables the register for loading after
the next CLK following the onset of

DIENB low. Actual
loading occurs on the second CLK following the onset of
DIENB low; therefore, DIENB must be low during the clock

5

HSP43891

cycle immediately preceding presentation of the data sample
on the DIN0-8 inputs. In most basic FIR operations,

DIENB
will be low throughout the process, so this latching and delay
sequence is only important during the initialization phase.
When

DIENB is high, the X register is loaded with all zeros.

The multiplier is pipelined and is modeled as a multiplier core
followed b y two pipeline registers, MREG0 and MREG1
(Figure 1). The multiplier output is sign extended and input as
one operand of the 26-bit adder. The other adder operand is
the output of the 26-bit accumulator. The adder output is
loaded synchronously into both the accumulator and the
TREG.

The TREG loading is disabled by the cell select signal,
CELLn, where n is the cell number.The cell select is decoded
from the ADR0-2 signals to generate the TREG load enable.
The cell select is inverted and applied as the load enable to
the TREG. Operation is such that the TREG is loaded
whenever the cell is not selected. Theref ore, TREG is loaded
every clock except the clock following cell selection. The
purpose of the TREG is to hold the result of a sum-of­products calculation during the clock when the accumulator is
cleared to prepare for the next sum-of-products calculation.
This allows continuous accumulation without wasting clocks .

The accumulator is loaded with the adder output every clock
unless it is cleared. It is cleared synchronously in two ways.
When

RESET and ERASE are both low, the accumulator is
cleared along with all other registers on the device. Since
ERASE and RESET are latched and delayed one clock
internally, clearing occurs on the second CLK following the
onset of both

ERASE and RESET low.

The second accumulator clearing mechanism clears a single
accumulator in a selected cell. The cell select signal, CELLn,
decoded from ADR0-2 and the

ERASE signal enable

clearing of the accumulator on the next CLK.
The

ERASE and RESET signals clear the DF internal

registers and states as follows:

ERASE RESET CLEARING EFFECT

1 1 No clearing occurs, internal state remains

same.

10RESET only active, all registers except ac-

cumulators are cleared, including the inter­nal pipeline registers.

01ERASE only active, the accumulator

whose address is given by the ADR0-2 in­puts is cleared.

0 0 Both RESET and ERASE active, all accu-

mulators as well as all other registers are
cleared.

The DF Output Stage

The output stage consists of a 26-bit adder, 26-bit register,
feedback multiplexer from the register to the adder, an output
multiplexer and a 26-bit three-state driv er stage (Figure 2).

The 26-bit output adder can add any filter cell accumulator
result to the 18 most significant bits of the output buffer. This
result is stored back in the output buffer.This operation takes
place in one clock period. The eight LSBs of the output
buffer are lost. The filter cell accumulator is selected by the
ADR0-2 inputs.

The 18 MSBs of the output buffer actually pass through the
zero mux on their way to the output adder input. The zero
mux is controlled by the SHADD input signal and selects
either the output buffer 18 MSBs or all zeros for the adder
input. A low on the SHADD input selects zero. A high on the
SHADD input selects the output buffer MSBs, thus,
activating the shift-and-add operation. The SHADD signal is
latched and delayed by one clock internally.

6