Intersil Corporation HSP43220 Datasheet

HSP43220

Data Sheet February 1999 File Number

Decimating Digital Filter

The HSP43220 Decimating Digital Filter is a linear phase low pass decimation ﬁlter which is optimized for ﬁltering narrow band signals in a broad spectrum of a signal processing applications. The HSP43220 offers a single chip solution to signal processing applications which have historically required several boards of ICs. This reduction in component count results in faster development times as well as reduction of hardware costs.

The HSP43220 is implemented as a two stage ﬁlter structure. As seen in the block diagram, the ﬁrst stage is a high order decimation ﬁlter (HDF) which utilizes an efﬁcient sample rate reduction technique to obtain decimation up to 1024 through a coarse low-pass ﬁltering process. The HDF provides up to 96dB aliasing rejection in the signal pass band. The second stage consists of a ﬁnite impulse response (FIR) decimation ﬁlter structured as a transversal FIR ﬁlterwithupto 512 symmetric taps which can implement ﬁlters with sharp transition regions. The FIR can perform further decimation by up to 16 if required while preserving the 96dB aliasing attenuation obtained by the HDF. The combined total decimation capability is 16,384.

2486.7

Features

• Single Chip Narrow Band Filter with up to 96dB Attenuation

• DC to 33MHz Clock Rate

• 16-Bit 2’s Complement Input

• 20-Bit Coefﬁcients in FIR

• 24-Bit Extended Precision Output

• Programmable Decimation up to a Maximum of 16,384

• Standard 16-Bit Microprocessor Interface

• Filter Design Software Available DECIMATE™

• Up to 512 Taps

Applications

• Very Narrow Band Filters

• Zoom Spectral Analysis

• Channelized Receivers

• Large Sample Rate Converter

The HSP43220 accepts 16-bit parallel data in 2’s complement format at sampling rates up to 33 MSPS. It provides a 16-bit microprocessor compatible interface to simplify the task of programming and three-state outputs to allow the connection of several ICs to a common bus. The HSP43220 also provides the capability to bypass either the HDF or the FIR for additional ﬂexibility.

Block Diagram

DECIMATION UP TO 1024 DECIMATION UP TO 16

INPUT CLOCK

DATA INPUT

CONTROL AND COEFFICIENTS

16 16

HIGH ORDER DECIMATION

FILTER

Ordering Information

TEMP.

PART NUMBER

HSP43220VC-33 0 to 70 100 Ld MQFP Q100.14x20 HSP43220JC-15 0 to 70 84 Ld PLCC N84.1.15 HSP43220JC-25 0 to 0 84 Ld PLCC N84.1.15 HSP43220JC-33 0 to 70 84 Ld PLCC N84.1.15 HSP43220GC-25 0 to 70 84 Ld CPGA G84.A HSP43220GC-33 0 to 70 84 Ld CPGA G84.A

DECIMATE Software Development Tool (This software tool may be

downloaded from our Internet site: http://www.intersil.com)

DECIMATION

FIR CLOCK

RANGE (oC) PACKAGE PKG. NO.

FIR

FILTER

DATA OUT DATA READY

3-194

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

DECIMATE™ is a trademark of Intersil Corporation.

HSP43220

Pinouts

84 PIN GRID ARRAY (PGA)

1 23456789 1110

GND

STAR T

ASTAR T

CS WR

DATA

IN 1

STAR T

OUT

RESET

DATA

IN 2

DATA

IN 0

DATA

IN 4

DATA

IN 3

DAT A

DATA

IN 7

IN 8

DAT A

DATA

IN 6

IN 13

DAT A

DATA

IN 5

IN 9

DATA

IN 11

IN 14

DATA

IN 12

IN 15

DATA

IN 10

HSP43220

C_BUS15C_BUS

C_BUS

GND

C_BUS

C_BUS6C_BUS3C_BUS2C_BUS

C_BUS

TOP VIEW

PINS DOWN

OUT_

GND

SELH

OUT

ENP

OUT

ENX

DATA

RDY

FIR

DATA

GND

OUT 22

DATA

OUT 23

CK_IN

DATA OUT 5

DATA OUT 9

DATA

OUT 10

DATA

OUT 19

DATA

OUT 21

GND GND

DATA OUT 0

DATA OUT 3

DATA OUT 6

GND

DATA

OUT 13

DATA

OUT 16

DATA

OUT 17

DATA

OUT 20

DATA_ OUT 1

DATA OUT 2

DATA OUT 4

DATA OUT 7

DATA OUT 8

DATA

OUT 11

DATA_

OUT 12

DATA

OUT 14

DATA

OUT 15

DATA

OUT 18

12 3456789 11

C_BUS6C_BUS3C_BUS2C_BUS

C_BUS

GND

C_BUS

CS WR

ASTAR T

START

GND

C_BUS

C_BUS15C_BUS

RESET

START

OUT

DATA

IN 1

C_BUS

DATA

IN 0

DATA

IN 2

C_BUS

DATA

IN 3

DATA

IN 4

OUT

ENX

OUT

ENP

OUT_ SELH

HSP43220

BOTTOM VIEW

DATA

IN 5

DATA

IN 6

DATA

IN 7

DATA

RDY

GND

PINS UP

DATA

IN 9

DATA

IN 13

DATA

IN 8

GND

FIR

DATA

IN 10

DATA

IN 12

DATA

IN 11

DATA OUT 23

DATA OUT 22

DATA

IN 15

DATA

IN 14

DATA

OUT 21

DATA OUT 19

DATA OUT 10

DATA

OUT 9

DATA

OUT 5

CK_IN

DATA OUT 20

DATA OUT 17

DATA OUT 16

DATA OUT 13

GND

DATA

OUT 6

DATA

OUT 3

DATA

OUT 0

GND GND

DATA OUT 18

DATA OUT 15

DATA OUT 14

DATA_ OUT 12

DATA OUT 11

DATA

OUT 8

DATA

OUT 7

DATA

OUT 4

DATA

OUT 2

DATA_

OUT 1

3-195

HSP43220

Pinouts

(Continued)

GND GND

STARTOUT

STARTIN

ASTARTIN

RESET

A1 A0

CS C_BUS15 C_BUS14 C_BUS13 C_BUS12 C_BUS11 C_BUS10

C_BUS9

GND

GND C_BUS8 C_BUS7 C_BUS6

NC C_BUS5 C_BUS4

100 LEAD MQFP

TOP VIEW

VCCGND

GND

VCCDATA_IN15

DATA_IN14

DATA_IN13

DATA_IN12

DATA_IN11

DATA_IN10

DATA_IN9

DATA_IN8

DATA_IN7

DATA_IN6

DATA_IN5

DATA_IN0

DATA_IN1

99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

DATA_IN3

DATA_IN2

DATA_IN4

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

CK_IN V

GND GND DATA_OUT0 DATA_OUT1 DATA_OUT2 DATA_OUT3 DATA_OUT4 DATA_OUT5 DATA_OUT6 DATA_OUT7 DATA_OUT8 DATA_OUT9 DATA_OUT10 DATA_OUT11 GND GND V

DATA_OUT12 DATA_OUT13 DATA_OUT14 DATA_OUT15 DOUT_OUT16 DATA_OUT17 DATA_OUT18 DATA_OUT19 DATA_OUT20

32 33 34 35 36 37 38 40 42 44 46 47 48 50494543413931

C_BUS3

C_BUS2

C_BUS1

C_BUS0

OUT_ENP

OUT_ENX

OUT_SELH

GND

FIR_CK

GND

DATA_RDY

DATA_OUT21

DATA_OUT23

DATA_OUT22

3-196

HSP43220

Pinouts

(Continued)

84 PLASTIC LEADED CHIP CARRIER (PLCC)

VCCGND

CK_IN

DATA_OUT 21

DATA_OUT 20

DATA_OUT 19

74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54

DATA_OUT 18

GND DATA_OUT 0 DATA_OUT 1 DATA_OUT 2 DATA_OUT 3 DATA_OUT 4 DATA_OUT 5 DATA_OUT 6 DATA_OUT 7 DATA_OUT 8 DATA_OUT 9 DATA_OUT 10 DATA_OUT 11 GND V

DATA_OUT 12 DATA_OUT 13 DATA_OUT 14 DATA_OUT 15 DATA_OUT 16 DATA_OUT 17

STARTOUT

STARTIN

ASTARTIN

RESET

C_BUS 15 C_BUS 14 C_BUS 13 C_BUS 12 C_BUS 11 C_BUS 10

C_BUS 9

GND C_BUS 8 C_BUS 7 C_BUS 6

A1 A0

DATA_IN 1

DATA_IN 0

GND

DATA_IN 2

DATA_IN 3

DATA_IN 4

DATA_IN 5

DATA_IN 6

DATA_IN 7

DATA_IN 8

DATA_IN 9

DATA_IN 10

DATA_IN 11

DATA_IN 12

DATA_IN 13

DATA_IN 14

DATA_IN 15

111098765432184838281807978777675

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

GND

C_BUS 5

C_BUS 4

C_BUS 3

C_BUS 2

C_BUS 1

C_BUS 0

OUT_ENP

OUT_SELH

OUT_ENX

FIR_CK

DATA_RDY

DATA_OUT 23

DATA_OUT 22

Pin Description

NAME TYPE DESCRIPTION

GND The device ground.

CK_IN I Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock

FIR_CK I Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the

DATA_IN0-15 I Input Data Bus. This bus is used to provide the 16-bit input data to the HSP43220. The data must be provided in a synchro-

C_BUS0-15 I Control Input Bus. This input bus is used to load all the ﬁlter parameters. The pins WR, CS and A0, A1 are used to select

DATA_OUT

0-23

DATA_RDY O An active high output strobe that is synchronous with FIR_CK that indicates that the result of the just completed FIR cycle

RESET I RESET is an asynchronous signal which requires that the input clocks CK_IN and FIR_CK are active when RESET is as-

WR I Write Strobe. WR is used for loading the internal registers of the HSP43220. When CS and WR are asserted, the rising edge of

CS I Chip Select. The Chip Select input enables loading of the internal registers. When CS and WR are low,the A0 and A1 address

The +5V power supply pins.

frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks maybe tied together if required, or CK_IN can be divided down from FIR_CK. CK_IN is a CMOS level signal.

rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal.

nous fashion, and is latched on the rising edge of the CK_IN signal. The data bus is in 2's complement fractional format. Bit 15 is the MSB.

the destination of the data on the Control bus and write the Control bus data into the appropriate register as selected by A0 and A1

O Output Data Bus. This 24-Bit output port is used to provide the ﬁltered result in 2's complement format. The upper 8 bits of

the output, DATA_OUT16-23 will provide extension or growth bits depending on the state of OUT_SELH and whether the FIR has been put in bypass mode. Output bits DATA_OUT0-15 will provide bits 20 through 2-15 when the FIR is not bypassed and will provide the bits 2-16 through 2-31 when the FIR is in bypass mode.

is available on the data bus.

serted. RESET disables the clock divider and clears all of the internal data registers in the HDF. The FIR ﬁlter data path is not initialized. The control register bits that are cleared are F_BYP, H_STAGES,and H_DRATE. The F_DIS bit is set. In order to guarantee consistent operation of the part, the user must reset the DDF after power up.

WR will latch the C_BUS0-15 data into the register specified by A0 and A1.

lines are decoded to determine the destination of the data on C_BUS0-15. The rising edge of WR then loads the appropriate register as specified by A0 and A1.

3-197

HSP43220

Pin Description

NAME TYPE DESCRIPTION

A0, A1 I Control Register Address. These lines are decoded to determine which control register is the destination for the data on

ASTARTIN I ASTARTIN is an asynchronous signal which is sampled on the rising edge of CK_IN. It is used to put the DDF in operational

STARTOUT O STARTOUT is a pulse generated from the internally synchronized version of ASTARTIN. It is provided as an output for use

STARTIN I STARTIN is a Synchronous Input. A high to low transition of this signal is required to start the part. STARTIN is sampled on

OUT_SELH I Output Select. The OUT_SELH input controls which bits are provided at output pins DATA_OUT16-23. A HIGH on this control

OUT_ENP I Output Enable. The OUT_ENP input controls the state of the lower 16 bits of the output data bus, DATA_OUT0-15. A LOW on

OUT_ENX I Output Enable. The OUT_ENX input controls the state of the upper 8 bits of the output data bus, DATA_OUT16-23. A LOW

The HDF

The first filter section is called the High Order Decimation Filter (HDF) and is optimized to perform decimation by large factors . It implements a low pass filter using only adders and delay elements instead of a large number of multiplier/ accumulators that would be required using a standard FIR filter.

The HDF is divided into 4 sections: the HDF ﬁlter section, the clock divider, the control register logic and the start logic (Figure 1).

Data Shifter

After being latched into the Input Register the data enters the Data Shifter. The data is positioned at the output of the shifter

(Continued)

C_BUS0-15. Register loading is controlled by the A0 and A1, WR and CS inputs.

mode. ASTARTIN is internally synchronized to CK_IN and is used to generateSTARTOUT.

in multi-chip conﬁgurations to synchronously start multiple HSP43220's. The width of STARTOUT is equal to the period of CK_IN.

the rising edge of CK_IN. This synchronous signal can be used to start single or multiple HSP43220's.

line selects bits 28 through 21 from the accumulator output. A LOW on this control line selects bits 2-16 through 2-23 from the accumulator output. Processing is not interrupted by this pin.

this control line enables the lower 16 bits of the output bus. When OUT_ENP is HIGH, the output drivers are in the high impedance state. Processing is not interrupted by this pin.

on this control line enables the upper 8 bits of the output bus. When OUT_ENX is HIGH, the output drivers are in the high impedance state. Processing is not interrupted by this pin.

Integrator Section

The data from the shifter goes to the Integrator section. This is a cascade of 5 integrator (or accumulator) stages, which implement a low pass filter. Each accumulator is implemented as an adder followed by a register in the feed forward path. The integrator is clocked by the sample clock, CK_IN as shown in Figure 2. The bit width of each integrator stage goes from 66 bits at the ﬁrst integrator down to 26 bits at the output of the ﬁfth integrator.Bit truncation is performed at each integrator stage because the data in the integrator stages is being accumulated and thus is growing, therefore the lower bits become insigniﬁcant, and can be truncated without losing signiﬁcant data.

to preventerrors due to overflowoccurring at the output of the HDF. The number of bits to shift is controlled by H_GROWTH.

A0-1 WR CS C_BUS

H_GROWTH INT_EN1-5

DAT A

CK_IN

CK_DEC

CK_IN

H_DRATE

CONTROL

655

COMB_EN1-5

H_BYP

CLOCK

DIVIDER

CK DEC

HDF FILTER SECTION

ISTART COMB_EN1-5H_GROWTH INT_EN1-5 RESETRESET

INPUT

REG

DAT A

SHIFTER

FIGURE 1. HIGH ORDER DECIMATION FILTER FIGURE

INTEGRATOR

DEC REG

26661616

3-198

RESET

RESET ASTAR TINCK_IN

ISTART

COMB FILTER ROUND REG

START LOGIC

STARTIN

STARTOUT

TO FIR 16

TO FIR

HSP43220

FROM SHIFTER

CK IN

MUX

INT_EN5

66 63

REG

INT_EN4

MUX

REG

FIGURE 2. INTEGRATOR

There are three signals that control the integrator section; they are H_STAGES, H_BYP and

RESET. In Figure 2 these control signals have been decoded and are labelled INT_EN1 - INT_EN5. The order of the ﬁlter is loaded via the control bus and is called H_STAGES. H_STAGES is decoded to provide the enables for each integrator stage. When a given integrator stage is selected, the feedback path is enabled and the integrator accumulates the current data sample with the previous sum. The integrator section can be put in bypass mode by the H_BYP bit. When H_BYP or RESET is asserted, the feedback paths in all integrator stages are cleared.

Decimation Register

The output of the Integrator section is latched into the Decimation Register by CK_DEC. The output of the Decimation register is cleared when

RESET is asserted. The HDF decimation rate = H_DRATE +1, which is deﬁned as H

for convenience.

DEC

Comb Filter Section

The output of the Decimation Register is passed to the Comb Filter Section. The Comb section consists of 5 cascaded Comb filters or differentiators. Each Comb filter section calculates the difference between the current and previous integrator output. Each Comb filter consists of a register which is clocked by CK_DEC, followed by an subtractor, where the subtractor calculates the difference between the input and output of the register. Bit truncations are done at each stage as shown in Figure 3. The first stage bit width is 26 bits and the output of the fifth stage is 19 bits.

MUX

INT_EN3

REG

MUX

INT_EN2

REG

MUX

INT_EN1

∑∑∑∑∑

REG

TO DECIMATION REGISTER

There are three signals that control the Comb Filter; H_ STAGES, H_BYP and

RESET. In Figure 3 these control signals are decoded as COMB_EN1 - COMB_EN5. The order of the Comb ﬁlter is controlled by H_STAGES, which is programmed over the control bus. H_BYP is used to put the comb section in bypass mode.

RESET causes the register output in each Comb stage to be cleared. The H_ BYP and RESET control pins, when asserted force the output of all registers to zero so data is passed through the subtractor unaltered. When the H_STAGES control bits enable a given stage the output of the register is subtracted from the input.

It is important to note that the Comb filter section has a speed limitation. The Input sampling rate divided by the decimation factor in the HDF (CK_IN/H

) should not exceed 4MHz.

DEC

Violating this condition causes the output of the filter to be incorrect. When the HDF is put in bypass mode this limitation does not apply .Equation1 describes the relationship between F_TAPS, F_DRA TE, H_DRATE, CK_IN and FIR_CK.

Rounder

The ﬁlter accuracy is limited by the 16-bit data input. To maintain the maximum accuracy, the output of the comb is rounded to 16 bits.

The Rounder performs a symmetric round of the 19-bit output of the last Comb stage. Symmetric rounding is done to prevent the synthesis of a 0Hz spectral component by the rounding process and thus causing a reduction in spurious free dynamic range. Saturation logic is also provided to prevent roll over from the largest positive value to the most negative value after rounding. The output of the last comb ﬁlter stage in the HDF section has a 16-bit integer portion with a 3-bit fractional part in 2's complement format.

FROM DECIMATION REGISTER

CK_DEC

COMB_EN5

RESET

REG

BAA-B

3-199

COMB_EN4

RESET

REG

COMB_EN3

RESET

BAA-B

REG

FIGURE 3. COMB FILTER

COMB_EN2

RESET

BAA-B

REG

BAA-B

COMB_EN1

RESET

REG

TO ROUNDER

BAA-B

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