Intersil Corporation HSP43168 Datasheet

HSP43168

Data Sheet November 1999

Dual FIR Filter

The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR ﬁlters. Each ﬁlter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefﬁcients. The Block Diagram shows two FIR cells each fed by a separate coefﬁcient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be conﬁgured to provide quadrature ﬁltering, complex ﬁltering, 2-D convolution, 1-D/2-D correlations, and interpolating/decimating ﬁlters.

The FIR cells take advantage of symmetry in FIR coefﬁcients by pre-adding data samples prior to multiplication. This allows an 8-tap FIR to be implemented using only 4 multipliers per ﬁlter cell. These cells can be conﬁgured as either a single 16-tap FIR ﬁlter or dual 8-tap FIR ﬁlters. Asymmetric ﬁltering is also supported.

Decimation ofupto 16 is providedto boost theeffective number of filter taps from 2 to 16 times. Further, the Decimation Registers provide the delay necessary for fractional data conversion and 2-D filtering with kernels to 16 x16.

The ﬂexibility of the Dual is further enhanced by 32 sets of user programmable coefﬁcients. Coefﬁcient selection may be changed asynchronously from clock to clock. The ability to toggle between coefﬁcient sets further simpliﬁes applications such as polyphase or adaptive ﬁltering.

The HSP43168 is a low power fully static design implemented in an advanced CMOS process. The conﬁguration of the device is controlled through a standard microprocessor interface.

File Number 2808.8

Features

• Two Independent 8-Tap FIR Filters Conﬁgurable as a Single 16-Tap FIR

• 10-Bit Data and Coefﬁcients

• On-Board Storage for 32 Programmable Coefficient Sets

• Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 19-Bit Data and Coefﬁcients

• Programmable Decimation to 16

• Programmable Rounding on Output

• Standard Microprocessor Interface

Applications

• Quadrature, Complex Filtering

• Image Processing

• Polyphase Filtering

• Adaptive Filtering

Ordering Information

TEMP.

PART NUMBER

HSP43168VC-33 0 to 70 100 Ld MQFP Q100.14x20 HSP43168VC-40 0 to 70 100 Ld MQFP Q100.14x20 HSP43168VC-45 0 to 70 100 Ld MQFP Q100.14x20 HSP43168JC-33 0 to 70 84 Ld PLCC N84.1.15 HSP43168JC-40 0 to 70 84 Ld PLCC N84.1.15 HSP43168JC-45 0 to 70 84 Ld PLCC N84.1.15 HSP43168JI-40 -40 to 85 84 Ld PLCC N84.1.15 HSP43168GC-45 0 to 70 84 Ld CPGA G84.A

RANGE (oC) PACKAGE PKG. NO.

Block Diagram

INA0 - 9

INB0 - 9/ OUT0 - 8

OEL

OEH

CIN0 - 9

A0 - 8

CSEL0 - 4

MUX

COEFFICIENT

BANK A

FIR CELL A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

MUX

MUX/

ADDER

919

1-888-INTERSIL or 407-727-9207

COEFFICIENT

BANK B

FIR CELL B

CONTROL/

CONFIGURATION

OUT9 - 27

Pinouts

84 LEAD CPGA

11 10 9 8 7 6 5 4 3 2 1

GND

RVRS

SHFTEN

MUX0 MUX1

FWRD

TXFR

ACCEN

GND CLK

OEH

OUT27 OUT22 OUT26

OUT24 OUT23 OUT25

BOTTOM VIEW

A4A1

HSP43168

BOTTOM VIEW

A7 CSEL1 CSEL3 CSEL4

CSEL0

CSEL2 CIN9

CIN2 CIN1

INA8 INA9

INA7 INA5

A2A3

CIN8

CIN5

CIN7

CIN6 CIN4

GND

CIN3

CIN0

INA6

HSP43168

PIN 'A1' ID

GND OUT15 OUT14 OUT12

OUT18

OUT19

OUT21

OUT24 OUT23 OUT25

OUT27 OUT22 OUT26

OEH

84 LEAD CPGA

11 10 9 8 7 6 5 4 3 2 1

OUT16

OUT17

OUT20

TOP VIEW

OUT10 OUT11

INB0

OUT9

OEL

HSP43168

INB5

INB7

INA7

INA8

INB6

INB8

INA0

INA3

INA5

INA9

INB4

INB1

GND

INB2OUT13

INB3 INA2

TOP VIEW

CIN2

GND

CLK

CIN1

INB9

INA1

INA4

INA6

CIN0

OUT21 OUT20

OUT19 OUT17

OUT18

GND OUT15 OUT14 OUT12 OUT10 OUT11 INB1 INB4 INB5 INB6

11 10 9 8 7 6 5 4 3 2 1

OUT9

INB3 INA2

OEL

CSEL 3

CSEL 4

CIN 9

CIN 8

109 8 7 6 5 4 3 2 1 848382818079

CIN 7

CIN 6

CIN 5

CIN 4

GND

CIN 3

CIN 2

CIN 1

CIN 0

INA 9

INA 8

INA 7

INA 6

INA 5

INA 4

INA 3

INA 2

INA 1

INA 0

INB 9

33 34 35 36 37 38 39 40 41

INA3 INA4

INA0

INB8

CSEL 1

CSEL 0

CSEL 2

INA1INB7GNDINB2OUT13 INB0OUT16

INB9

84 LEAD PLCC

TOP VIEW

A 6

A 7

A 5

A 8

42 43 44 45 46 47 48 49

CIN9

CSEL3

GND

CIN6

CIN7

CSEL4

ACCEN

TXFR

FWRD

SHFTEN

MUX0 MUX1

RVRS WR

11 10 9 8 7 6 5 4 3 2 1

A 4

A 3

A 2

A 1

A 0

GND

MUX 1

MUX 0

A2A3

A7 CSEL1

CSEL0

CSEL2

767778 75

RVRS

FWD

SHFTEN

TXFR

ACCEN V

CLK

GND

OEH

OUT 27

OUT 26

OUT 25

OUT 24

OUT 23

OUT 22

OUT 21 OUT 20

OUT 19

OUT 18

OUT 17

50 51 52 53

CIN3

CIN4

CIN5

CIN8

A PIN

'A1' ID

INB 8

INB 7

INB 6

INB 5

GND

INB 4

INB 3

INB 2

INB 1

INB 0

OEL

OUT 9

OUT 10

OUT 12

OUT 11

OUT 13

OUT 14

OUT 15

GND

OUT 16

Pinouts (Continued)

HSP43168

100 LEAD MQFP

TOP VIEW

CIN8

CIN7

NC CIN6 CIN5 CIN4 GND GND CIN3 CIN2 CIN1 CIN0 INA9 INA8 INA7 INA6 INA5

INA4 INA3 INA2 INA1 INA0

NC INB9 INB8 INB7

CCVCC

CIN9

CSEL4

99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

CSEL2

CSEL3

CSEL1

CSEL0

GND

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

MUX1 MUX0 RVRS NC FWRD SHIFTEN TXFR ACCEN V

CLK GND GND OEH OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 NC V

GND GND

32 33 34 35 36 37 38 40 42 44 46 47 48 50494543413931

INB6

INB5

GND

INB4

INB3

INB2

INB1

INB0

OEL

OUT9

OUT10

VCCV

OUT11

OUT12

OUT13

OUT14

OUT15

OUT16

HSP43168

Pin Description

SYMBOL TYPE DESCRIPTION

GND Ground.

CIN0-9 I Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB.

A0-8 I Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the

WR I Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of

CSEL0-4 I Coefficient Select. Thisinput determines which of the 32 coefficient sets areto be used by FIR A and B. Thisinput

INA0-9 I Input to FIR A. INA0 is the LSB. INB0-9 I/O Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 are the LSBs of the

OUT9-27 O 19MSBs of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27

SHFTEN I ShiftEnable.This active lowinput enables clockingof data intothe part andshifting of datathrough the Decimation

FWRD I Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALUs through

RVRS I Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALUs through

VCC: +5V power supply pin.

LSB.

WR.

is registered and CSEL0 is the LSB.

output bus, and INB9 is the MSB of these bits.

is the MSB.

Registers.

the “a” input. When high, the “a” inputs to the ALUs are zeroed.

the “b” input. When high, the “b” inputs to the ALUs are zeroed.

TXFR I Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with

the LIFO being written from the forward decimation path (see Figure 1).

MUX0-1 I Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 5 lists the various

configurations.

CLK I Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables

(OEL, OEH) are registered by the rising edge of CLK.

OEL I Output Enable Low. This three-state control enables the LSBs of the output bus to INB1-9 when OEL is low.

OEH I Output Enable High. This three-state control enables OUT9-27 when OEH is low.

ACCEN I Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input

latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the Accumulator.

TXFR

FIR A REVERSE PATH

FIR A FORWARD PATH

SHFTEN

INB1-9/ OUT0-8

INA0-9

INB0

FWRD

RVRS

†FIR B INPUT

SOURCE

DELAY 3

U X

DELAY 3

ALU

REG

DELAY

1-16 ††

DELAY 1-16

††

REG

DELAY 4

DELAY 3

DECIMATION REGISTERS

DELAY

1-16 ††

DELAY

1-16

††

ALU

†DATA REVERSAL ENABLE

M U X

†FIR A ODD/EVEN # TAPS

DELAY 1-16 ††

DELAY 1-16

††

ALU

REG

ALU

REG

DATA FEEDBACK

CIRCUITRY

LIFO A

LIFO B

U X

DELAY 1-16 ††

†ODD/EVEN

SYMMETRY

†MODE SELECT

†ODD/EVEN SYMMETRY †MODE SELECT

M U X

ALU

REG

DECIMATION REGISTERS

DELAY

1-16

††

DELAY

††

1-16

ALU

REG

DELAY 4

DELAY 3

DELAY 1-16

††

M U X

ALU

REG

†FIR B

ODD/EVEN # TAPS

DELAY

1-16

††

DELAY

††

1-16

ALU

REG

DATA FEEDBACK

CIRCUITRY

LIFO A

LIFO B

U X

DELAY

1-16

†DATA REVERSAL ENABLE

FIR B REVERSE PATH FIR B FORWARD PATH

†ODD/EVEN

SYMMETRY

D E M U X

†ODD/EVEN

NUMBER OF TAPS

M U X

HSP43168

CSEL0-4

REG

COEF

BANK

COEF

BANK

DELAY 4

REG

COEF

BANK

REG

COEF

BANK

REG

COEF

BANK

3210

REG

COEF

BANK

REG

COEF

BANK

210

REG

COEF

BANK

CLK

ACCEN

MUX0-1

CIN0-9

A0-8

OEL

OEH

FIR A

ACCUMULATOR

U X

DELAY 5

DELAY 6

CONTROL

ADDER

E G

OUTPUT HOLDING

REG

†MODE SELECT †ODD EVEN SYMMETRY †FIR A ODD/EVEN # TAPS †FIR B ODD/EVEN # TAPS †FIR B INPUT SOURCE †DATA REVERSAL ENABLE †ROUND ENABLE †DECIMATION FACT OR

FIR CELL A FIR CELL B

MUX/

ADDER

DELAY 2

†ROUND ENABLE

FIR B

ACCUMULATOR

U X

ADDER

E G

OUTPUT HOLDING

REG

OUT9-27

†Processor control words

††Decimation factor

FIGURE 1. DUAL FIR FILTER

HSP43168

Functional Description

As shown in Figure 1, the HSP43168 consists of two 4-multiplier FIR ﬁlter cells which process 10-bit data and coefﬁcients. The FIR cells can operate as two independent 8-tap FIR ﬁlters or two 4-tap asymmetric ﬁlters at maximum I/O rates. A single ﬁlter mode is provided which allows the FIR cells to operate as one 16-tap FIR ﬁlter or one 8-tap asymmetric ﬁlter. On board coefﬁcient storage for up to 32 sets of 8 coefﬁcients is provided. The coefﬁcient sets are user selectable and are programmed through a microprocessor interface.Programmable decimation to 16 is also provided. By utilizing Decimation Registers together with the coefﬁcient sets, polyphase ﬁlters are realizable which allow the user to trade data rate for ﬁlter taps. The MUX/Adder can be conﬁgured to either add or multiplex the outputs of the ﬁlter cells depending upon whether the cells are operating in single or dual ﬁlter mode. In addition, a shifter in the MUX/Adder is provided for implementation of ﬁlters with 10-bit data and 20-bit coefﬁcients or vice versa.

The Dual FIR Filter has a “pipeline” delay of 8 CLK periods, once normal ﬁltering operations begin. Five typical ﬁltering operation examples are provided in the Applications Examples Section as a guide to conﬁguration and control of the Dual FIR Filter.

During normal ﬁlter operations, the location and duration of the

TXFR signal assertions are determined by the ﬁlter conﬁguration and operation mode. Once set, these signal parameters must be maintained during normal operation to ensure proper data alignment in the part. Once the part is reset, donot change again.

NOTE: The ﬁxed or periodic relationship between the TXFR signal and CLK must be maintained for valid ﬁlter operation. This relationship can only change when CLK is halted and new conﬁguration control words are loaded into the device.

TXFR unlessyou load the conﬁguration

Preparing the Dual FIR for Operation

Two conﬁguration steps are requiredto prepare the Dual FIR Filter for normal operation: 1) loading the Conﬁguration Control Registers, and 2) loading the FIR Filter Coefﬁcients.

Conﬁguration Control Registers are loaded by placing the control register address on address lines A0-8, placing the conﬁguration data on the conﬁguration input lines CIN0-9, and asserting the assertion). This action creates a rising edge on the which clocks the address and configuration data into the part. The details of the “Load Configuration” process areoutlined in the Microprocessor Interface Section.

FIR Coefficients are loaded by placing the address of the Coefficient Data Bank on the address lines A0-8, placing the FIR 10-bit coefficient values on the configuration input lines CIN0-9 and then asserting the release of the assertion). This action creates a rising edge on the

WR line, which clocks the FIR Coefficient Band address and FIR Coefficient data into the part. The details of the “Load FIR Coefficient” process are outlined in the FIR Filter Cells Section, Coefficient Bank Subsection.

Both the Configuration Load and FIR Coefficient Load can be done as a sequence of asynchronous write commands to the Dual FIR Filter. Once these actions are complete, the part is ready for normal filter operation. The CLK, FWRD, RVRS, ACCEN, and SHFTEN signals must be asserted in a manner determined by the application. MUX0-1 must meet the setup and hold times with respect to clock for proper filter operation. Details of the MUX1-0 control can be found in the Output MUX/Adder Section. Details of the ACCEN control can be found in the Fir Cell Accumulator Section. Bit locations for the various filter control/configuration signals can be found in the Input/Output Formats Section.

WR line (followed by a release of the

WR line,

WR line (followed by a

TXFR,

Microprocessor Interface

The Dual FIRhas a 20 pin write only microprocessor interface for loading data into the Control Block and Coefficient Banks. The interface consists of a 10-bit data bus (CIN0-9), a 9-bit address bus (A0-8), and a write input ( into the on-boardregisters on a rising edge. The configuration control and coefficient data loading is asynchronous to CLK.

WR) to latch the data

Control Block

The Dual FIR is conﬁgured by writing to the registers within the Control Block. Figure 2 shows the timing diagram for writing to the ConﬁgurationControl Registers. These Control Registers are memory mapped to Address 000H (H = Hexadecimal) and 001H on A0-8. The Filter Coefﬁcient Registers are mapped to 1XXH (X = value described in the “Coefﬁcient Banks” chapter of the ALU Section).

RESET

A8-0

C9-0

FIGURE 2. LATCHING C9-0 VALUESINTOADDRESS A8-0

The format of the Control Registers is shown in Table 1 and Table 2. Writing toany of the Control/Conﬁguration Registers causes a reset which lasts for 6 CLK cycles following the assertion of the Control Block will not clear the contentsof the Coefﬁcient

000H

001H

REGISTERS

WR. The reset caused by Writing Registers in

HSP43168

Bank. As shown in Figure 2, either Conﬁguration Control Register can be written to during reset.

T ABLE1. CONFIGURATION/CONTROLWORD 0 BIT DEFINITIONS

CONTROL ADDRESS 000H

BITS FUNCTION DESCRIPTION

3-0 Decimation Factor (N) R = N + 1

0000 = No Decimation. 1111 = Decimation by 16.

4 Mode Select 0 = Single Filter Mode.

1 = Dual Filter Mode. (also 20-Bit Coefficient Filter)

5 Odd/Even Filter

Coefficient Symmetry

6 FIR A Odd/Even

Number of Taps

7 FIR B Odd/Even

Number of Taps

8 FIR B Input Source 0 = Input from INA0-9.

9 Not Used Set to 0 for Proper Operation.

NOTE: Address locations002H to 011H are reserved, and writing to these locations will have unpredictable effects on part conﬁguration.

T ABLE2. CONFIGURATION/CONTROLWORD 1 BIT DEFINITIONS

CONTROL ADDRESS 001H

BITS FUNCTION DESCRIPTION

0 FIR A Input Format 0 = Unsigned.

1 FIR A Coefficient Format (Defined same as FIR A input). 2 FIR B Input Format (Defined same as FIR A input). 3 FIR B Coefficient (Defined same as FIRA input). 4 Data Reversal Enable 0 = Enabled.

8-5 Round Position 0000 = 2

9 Round Enable 0 = Enabled.

NOTE: Address locations 002H to 011H are reserved, and writing to these locations will have unpredictableeffects on part conﬁguration.

0 = Even Symmetric Coefficients. 1 = Odd Symmetric Coefficients.

0 = Odd Number of Taps in Filter. 1 = Even Number of Taps in Filter.

(Defined Same as FIR A Above).

1 = Input from INB0-9.

1 = Two's Complement.

1 = Disabled.

-10.

1011 = 2 (See Figure 4)

1 = Disabled.

The 4 LSBs of the control word loaded at address 000H are used to select the decimation factor. The Decimation Factor is programmed to one less than the number of delays between ﬁlter taps

DF CLK delays between taps()1–=

(EQ. 1)

and B before entering the reverse paths of Filters A and B (see Figure 1). Coefficient symmetry is selected by bit 5. Bits 6 and 7 are programmed to configure the FIR cells for odd or even filter lengths (number of taps). Bit 8 selects the FIR B input source when the FIR cells are configured for independent operation. Bit 9 must be programmed to 0.

NOTE: When the filter is programmed for even-taps, the TXFR signal is delayed by only three CLKS (see Figure 1). For odd-taps, the

TXFR signal is delayed by four CLKS.

The 4 LSBs of the control word loaded at address 001H are used to conﬁgure the format of the FIR cell's data and coefﬁcients. Bit 4 is programmed to enable or disable the reversal of data sample order prior to entering the Reverse Path Decimation Registers. Data reversal is required for symmetric ﬁlter coefﬁcient sets of both even or odd numbers of ﬁlter taps. Asymmetric ﬁlters and some decimated symmetric ﬁlters require the data reversal to be off. Bits 5-9 are used to support programmable rounding on the output.

FIR Filter Cells

Each FIRfilter cell is based on an array of four11x10-bit two's complement multipliers. One input of the multipliers comes from the ALU’s which combine data shifting through the Forward and Re verse Decimation Registers. The second multiplier inputcomes from the user programmablecoefficient bank. The multiplier outputs are fed to an accumulator whose result is passedto the output section where it ismultiplexed or added with the result from the other FIR cell.

Decimation Registers

The Forwardand ReverseDecimation Shift Registerscan be conﬁgured for decimation factors from 1 to 16 (see Table 1, bits 0-3). NOTE: Setting the decimation factor only

affects the Delay Registers between ﬁlter taps, not the ﬁlter controlmultiplexers. Example 4 and Example 5 inthe

Applications Section discuss how to conﬁgure the part for actual decimation applications.

The Reverse Shifting Registers with the data reversal logic are used to takeadvantage of symmetry in linear phase filters by aligning data at the ALUs for pre-addition prior to multiplication by the common coefficient. When the FIR cells are configured in single filter mode, the Decimation Registers in FIR cell A and FIR cell B are cascaded. This extended filter tap delay path allows computation of a filter which is twice the size of that capable using a single cell. The Decimation Registers also provide data storage for polyphase or 2-D filtering applications (See Applications Examples Section).

For example , if the 4 LSBs are prog r ammed with a value of 0010, theForward andReverse ShiftingDecimation Registers are each configured with a delay of 3. Bit 4 is used to select whether the FIR cells operate as two independent filters or one extended length filter . Dual filter mode assumes Filter A and FilterB are separate independentfilters. In thesingle filter mode, thedata is routed through the forw ardpaths of Filters A

The Data FeedbackCircuitry in each FIR cell is responsible for transferring data from the Forward to the Reverse Shifting Decimation Registers.This circuitry feeds blocks of samples into the reverse shifting decimation path in either reversed or non-reversed sample order. The MUX/DEMUX structure at the input to the Feedback Circuitry routes data to the LIFOs or the delay stage depending on the selected

HSP43168

configuration. The MUX on the Feedback Circuitry Output selects which storage element feeds the Reverse Shifting Decimation Registers.

In applications requiring reversal of sample order, the FIR cells are configured with data reversal enabled (see Table 2, CW5, bit 4 = 0). In this mode, data is transferred from the forward to the backward Shifting Registers through a pingponged LIFO structure. While one LIFO is being read into the backward shifting path, the other LIFO is written with data samples. The MUX/DEMUX controls which LIFO is being written, and the MUX on the Feedback Circuitry output controls which LIFO is being read. A low on and

SHIFTEN, switches the LIFOs being read and written,

TXFR

which causes the block of data to be read from the structure in reversedin sample order (See Example4 in the Application Examples Section).

The frequency with which

TXFR is asserted determinessize of the data blocks in which sample order is reversed. For example, if

TXFR is asserted once every three CLKs, blocks of 3 data samples with order reversed, would be fed into the Backward Decimation Registers. NOTE: Altering the

frequency or phase of

TXFR assertion once a ﬁltering

operation has begun will invalidate the ﬁltering result.

In applications which do not require sample order reversal, the FIR cells must be configured with data reversal disabled (see Table 2, CW5, bit 4 = 1). In addition, TXFR must be asserted to ensure proper data flow. In this configuration, data to the backward shifting decimation path is routed though a delaystage instead of the pingpong LIFOs. The number of registers in the delay stage is based on the programmed decimation factor. NOTE: Data

reversal must be disabled and TXFR must be asserted for filtering applications which do not use decimation.

The shifting of data through the Forward and Reverse Decimation Registers is enabled by asserting the input. When

SHFTEN is high, data shifting is disabled, and

SHFTEN

the data sample latched into the parton the previous clockis the last input to the ﬁlter structure. The data sample at the ﬁlter input when

SHFTEN is asserted, will be the next data

sample into the forward decimation path. When operating the FIR cells as two independent ﬁlters, FIR

A receives input data via INA0-9 and FIR B receives data from either INA0-9 or INB0-9 depending on the application (see Table 1).

When the FIR cells are conﬁgured as a single extended length ﬁlter, the forward and reverse decimation paths of the two FIR cells are cascaded. In this mode,data is transferred from the forward decimation path to the reverse decimation path by the Data Feedback Circuitry in FIR B. Thus, the manner in which data is read into the reverse decimation path is determined by FIR B's conﬁguration. When the decimation paths are cascaded, data is routed through the fourth delay stage in FIR A's forward path to FIR B.

The configuration of the FIR cells as even or odd length filters determines the point in the forward decimation path from which data is multiplexed to the Data Feedback Circuitry. For example, if the FIR cell is configured as an odd length filter, data prior to the last register in the third forward decimation stage is routed to the Feedback Circuitry. If the FIR cell is configured as an even length filter, data output from the third forward decimation stage is multiplexed to the Feedback Circuitry.This isrequired to ensure properdata alignment with symmetric filter coefficients (See Application Examples).

ALUs

Data shifting through the forward and reverse decimation paths feed the “a” and “b” inputs of the ALUs respectively. The ALUs perform an “b+a” operation if the FIR cell is conﬁgured for even symmetric coefﬁcients or an “b-a” operation if conﬁgured for odd symmetric coefﬁcients. Control Word 0, Bit 5 is used to set the ALU operation.

Forapplications in which a pre-add or subtract is not required, the “a” or “b” input can be zeroed by disabling RVRS respectively. This has the effect of producing an ALU output which is either “a”, “-a”, or “b” depending on the filter symmetry chosen. For example, if the FIR cell is configured for an even symmetric filter with

FWRD low andRVRS high, the data shifting through the Forward Decimation Registers would appear on the ALU output.

Table 3 details the ALU conﬁgurations, where “a” is the ALU data inputfrom the front decimation delayregisters and “b” is the ALU data from the back decimation delay registers.

TABLE 3. ALU CONFIGURATIONS

ALU

OUT SYMMETRY FWD RVS DESCRIPTION

a+b 0 (Even) 0 0 EvenNumber ofTaps, Even

Symmetry (Example 1) +b 0 (Even) 0 1 Even Symmetry +a 0 (Even) 1 0 Even Symmetry

- 0 (Even) 1 1 Even Symmetry

b-a 1 (Odd) 0 0 Even Number of Taps, Odd

Symmetry (Example 2) +b 1 (Odd) 0 1 Odd Symmetry

-a 1 (Odd) 1 0 Odd Symmetry

- 1 (Odd) 1 1 Odd Symmetry

Coefﬁcient Bank

The output of the ALU is multiplied by a coefﬁcient from one of 32 user programmable coefﬁcient sets. Each set consists of 8 coefﬁcients (4 coefﬁcients for FIR A and 4 for FIR B). CSEL0-4 is used to select a coefﬁcient set to be used. Coefﬁcient sets may be switched every clock to support polyphase ﬁltering operations.

The coefﬁcients are loaded into On-Board Registers using the microprocessor interface, CIN0-9, A0-8, and multiplier within the FIR Cells is driven by a coefﬁcient bank

FWRD or

WR. Each

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