Intersil Corporation HS-82C37ARH Datasheet

August 1995

HS-82C37ARH

Radiation Hardened CMOS High

Performance Programmable DMA Controller

Features

• Radiation Hardened

- Total Dose >10

- Transient Upset > 10

- Latch Up Free EPI-CMOS

• Low Power Consumption

- IDDSB = 50µA Maximum

- IDDOP = 4.0mA/MHz Maximum

• Pin Compatible with NMOS 8237A and the Intersil
82C37A

• High Speed Data Transfers Up To 2.5 MBPS With 5MHz
Clock

• Four Independent Maskable Channels With Autoinitializa­tion Capability

• Expandable to Any Number of Channels

• Memory-to-Memory Transfer Capability

• CMOS Compatible

• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process

• Single 5V Supply

• Military Temperature Range -55

5

RAD (Si)

8

RAD (Si)/s

o

C to +125oC

Description

The Intersil HS-82C37ARH is an enhanced, radiation
hardened CMOS version of the industry standard 8237A
Direct Memory Access (DMA) controller, fabricated using the
Intersil hardened field, self-aligned silicon gate CMOS
process. The HS-82C37ARH offers increased functionality,
improved performance, and dramatically reduced power
consumption for the radiation environment. The high speed,
radiation hardness, and industry standard configuration of
the HS-82C37ARH make it compatible with radiation
hardened microprocessors such as the HS-80C85RH and
the HS-80C86RH.

The HS-82C37ARH can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization
feature. DMA requests may be generated by either
hardware or software, and each channel is independently
programmable with a variety of features for flexible
operation.

Static CMOS circuit design insures low operating power and
allows gated clock operation for an even further reduction of
power. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
The Intersil hardened field CMOS process results in
performance equal to or greater than existing radiation resis­tant products at a fraction of the power.

Ordering Information

PART NUMBER TEMPERATURE RANGE PACKAGE

HS1-82C37ARH-Q -55oC to +125oC 40 Lead SBDIP
HS1-82C37ARH-8 -55oC to +125oC 40 Lead SBDIP
HS1-82C37ARH-Sample +25oC 40 Lead SBDIP
HS9-82C37ARH-Q -55oC to +125oC 42 Lead Ceramic Flatpack
HS9-82C37ARH-8 -55oC to +125oC 42 Lead Ceramic Flatpack
HS9-82C37ARH/Sample +25oC 42 Lead Ceramic Flatpack

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

918

Spec Number

File Number 3042.1

518058

DB NA

HS-82C37ARH

Pinouts

40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

(SBDIP) MIL-STD-1835 CDIP2-T40

TOP VIEW

IOR

IOW

MEMR

MEMW

NC

READY

HLDA

ADSTB

AEN
HRQ

CS

CLK
RESET
DACK2
DACK3

DREQ3
DREQ2
DREQ1
DREQ0

(GND)

VSS

1
2
3
4
5
6
7
8

9

10
11
12
13
14
15
16
17
18
19
20

40

A7

39

A6

38

A5

37

A4

36

EOP

35

A3
A2

34
33

A1

32

A0

31

VDD

30

DB0

29

DB1

28

DB2

27

DB3

26

DB4

25

DACK0

24

DACK1
DB5

23

DB6

22

DB7

21

42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

(FLATPACK) INTERSIL OUTLINE K42.A

TOP VIEW

IOR

IOW

MEMR

MEMW

NC

READY

HLDA

ADSTB

AEN

HRQ

CS

CLK

RESET
DACK2
DACK3

NC

DREQ3
DREQ2
DREQ1
DREQ0

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

24
23
22

A7
A6

A5
A4
EOP
A3
A2
A1
A0
VDD
DB0
DB1

DB2
DB3

DB4
NC

DACK0
DACK1
DB5
DB6
DB7

Functional Diagram

EOP

RESET

CS

READY

CLOCK

4

4

TIMING

AND

CONTROL

PRIORITY

ENCODER

AND

ROTATING

PRIORITY

LOGIC

AEN

ADSTB

MEMR

MEMW

IOR

IOW

DREQ0-

DREQ3

HLDA

HDQ

DACK0-

DACK3

DECREMENTOR INC DECREMENTOR

TEMP WORD

COUNT REG (16)

READ BUFFER

BASE

ADDRESS

(16)

COMMAND (8)

MASK (4)

REQUEST (4)

16 BIT BUS

BASE

WORD

COUNT

(16)

TEMP ADDRESS

REG (16)

16 BIT BUS

BASE

ADDRESS

(16)

WRITE

BUFFER

INTERNAL DATA BUS

MODE
(4 x 6)

BASE

WORD

COUNT

(16)

READ

BUFFER

STATUS (8)

A8-A15

TEMPORARY

(8)

D0-D1

I/O BUFFER

OUTPUT
BUFFER

COMMAND

CONTROL

I/O BUFFER

A0-A3

A4-A7

DB0-DB7

919

Spec Number 518058

HS-82C37ARH

Pin Descriptions

PIN

SYMBOL

VDD 31 VDD: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for de-

GND 20 Ground

CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control HS-82C37ARH

CS 11 I CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for

RESET 13 I RESET: This is an active high input which clears the Command, Status, Request and Temporary Reg-

READY 6 I READY: This signal can be sued to extend the memory read and write pulses from the HS-82C37ARH

HLDA 7 I HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that is has relin-

NUMBER TYPE DESCRIPTION

coupling.

operations. This input may be driven from DC to 5MHz and may be stopped in either high or low state
for standby operation.

CPU communications.

isters, the First/Last Flip-Flop, and the Mode Register Counter. The Mask Register is Set to ignore re­quests. Following a Reset, the controller is in an idle cycle.

to accommodate slow memories or I/O devices. Ready must not make transitions during its specified
set-up and hold times. Ready is ignored in Verify Transfer mode.

quished control of the system busses.

DREQ0-

DREQ3

DB0-

DB7

IOR 1 I/O I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control

IOW 2 I/O I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control

EOP 36 I/O END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information concerning

16-19 I DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs

used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and
DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK
will acknowledge the recognition of DREQ signal. Polarity of DREQ is programmable. Reset initializes
these lines to active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs
should be pulled High or Low (inactive) and the corresponding mask bit set.

21-23
26-30

I/O DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus.

The outputs are enabled in the Program Condition during the I/O Read to output the contents of a reg­ister to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the
CPU is programming the HS-82C37ARH Control Registers. During DMA cycles, the most significant 8
bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In Mem­ory-to-Memory operations, data from the memory enters the HS-82C37ARH on the data bus during the
read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the
data into the new memory location.

signal used by the CPU to read the internal registers. In the Active cycle, it is an output control signal
used by the HS-82C37ARH to access data from a peripheral during a DMA Write transfer.

signal used by the CPU to load information into the HS-82C37ARH. In the Active cycle, it is an output
control signal used by the HS-82C37ARH to load data to the peripheral during a DMA Read transfer.

the completion of DMA services is available at the bidirectional EOP pin.
The HS-82C37ARH allows an external signal to terminate an active DMA service by pulling the EOP
pin low. A pulse is generated by the HS-82C37ARH when terminal count (TC) for any channel is
reached, except for channel 0 in Memory-to-Memory mode. During Memory-to-Memory transfers, EOP
will be output when the TC for channel 1 occurs.
The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor.
When an EOP pulse occurs, whether internally or externally generated, the HS-82C37ARH will termi­nate the service, and if Autoinitialize is enabled, the base registers will be written to the current registers
of that channel. The mask bit and TC bit in the Status Register will be set for the currently active channel
by EOP unless the channel is programmed for Autoinitialize. In that case, the mask bit remains clear.

A0-A3 32-35 I/O Address: The four least significant address lines are bidirectional three-state signals. In the Idle cycle,

they are inputs and are used by the HS-80C86RH to address the internal registers to be loaded or read.
In the Active cycle, they are outputs and provide the lower 4 bits of the output address.

Spec Number 518058

920

HS-82C37ARH

Pin Descriptions

PIN

SYMBOL

A4-A7 37-40 O Address: The four most significant address lines are three-state outputs and provide 4 bits of address.

HRQ 10 O Hold Request: The Hold Request (HRQ) output is used to request control of the system bus. When a

DACK0-

DACK3

AEN 9 O Address Enable: Address Enable enables the 8-bit latch containing the upper 8 address bits onto the

ADSTB 8 O Address Strobe: This is an active high signal used to control latching of the upper address byte. It will

MEMR 3 O Memory Read: The Memory Read signal is an active low three-state output used to access data from

MEMW 4 O Memory Write: The Memory Write is an active low three-state output used to write data to the selected

NUMBER TYPE DESCRIPTION

14,15, 24,

25

(Continued)

These lines are enabled only during the Active cycle.

DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the HS­82C37ARH issues HRQ. The HLDA signal then informs the controller when access to the system bus­ses is permitted. For stand-alone operation where the HS-82C37ARH always controls the busses, HRQ
may be tied to HLDA. This will result in one S0 state before the transfer.

O DMA Acknowledge: DMA acknowledge is used to notify the individual peripherals when one has been

granted a DMA cycle. The sense of these lines is programmable. Reset initializes them to active low.

system address bus. AEN can also be used to disable other system bus drivers during DMA transfers.
AEN is active HIGH.

drive directly the strobe input of external transparent octal latches, such as the 82C82. During block op­erations, ADSTB will only be issued when the upper address byte must be updated, thus speeding op­eration through elimination of S1 states. (See Note 2).

the selected memory location during a DMA Read or a Memory-to-Memory transfer.

memory location during a DMA Write or a Memory-to-Memory transfer.

NC 5 No connect. Pin 5 is open and should not be tested for continuity.

921

Spec Number 518058

Specifications HS-82C37ARH

Absolute Maximum Ratings Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6.5V

Input or Output Voltage Applied . . . . . . . .VSS - 0.3V to VDD + 0.3V

for All Grades

Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Typical Derating Factor. . . . . . . . . . . . 4mA/MHz Increase in IDDOP

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Supply Voltage Range (VDD) . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 38oC/W 5oC/W

Ceramic Flatpack Package . . . . . . . . . . . 72oC/W 10oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.32W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W

If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26.3mW/C

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .13.9mW/C

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V

Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -1.5V to VDD

GROUP A

SUBGROUP TEMPERATURE

JA

LIMITS

θ

JC

UNITSMIN MAX

TTL Output High Voltage VOH1 VDD = 4.5V, IO = -2.5mA,

VIN = 0V or 4.0V

CMOS Output High Volt­age

Output Low Voltage VOL1 VDD = 4.5V, IO = +2.5mA,

Input Leakage Current IIL or IIH VDD = 5.5V, VIN = 0V or

Output Leakage Current IOZL or

Standby Power Supply
Current

Operating Power Supply
Current

Functional Tests FT VDD = 4.5V and 5.5V,

Noise Immunity Functional
Test

VOH2 VDD = 4.5V, IO = -100µA,

VIN = 0V or 4.0V

VIN = 0V or 4.0V

5.5V Pins: 6, 7, 11-13, 16-19

VDD = 5.5V, VIN = 0V or

IOZH

IDDSB VDD = 5.5V, IO = 0mA,

IDDOP VDD = 5.5V, IO = 0mA,

FN VDD = 4.5V and 5.5V, VIN =

5.5V Pins: 1-4, 21-23, 26­30, 32-40

VIN = GND or VDD

VIN = GND or VDD,
f = 5MHz

VIN = GND or VDD,
f = 1MHz

GND or VDD - 1.5V and
VDD = 4.5V, VIN = 0.8V or
VDD

1, 2, 3 +25oC, +125oC,

-55oC

1, 2, 3 +25oC, +125oC,

-55oC

1, 2, 3 +25oC, +125oC,

-55oC

1, 2, 3 +25oC, +125oC,

-55oC

1, 2, 3 +25oC, +125oC,

-55oC

1, 2, 3 +25oC, +125oC,

-55oC

1, 2, 3 +25oC, +125oC,

-55oC

7, 8A, 8B +25oC, +125oC,

-55oC

7, 8A, 8B +25oC, +125oC,

-55oC

3.0 - V

VDD-

0.4

- 0.4 V

-1.0 1.0 µA

-10 10 µA

- +50 µA

-20mA

-- -

-- -

-V

922

Spec Number 518058

Specifications HS-82C37ARH

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

VCC = +5V ±10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range.

PARAMETER SYMBOL

DMA (MASTER) MODE
AEN HIGH from CLK LOW (S1)

Delay Time
DMA (MASTER) MODE (Continued)
AEN LOW from CLK HIGH (SI)

Delay Time
ADR from READ HIGH Hold

Time
DB from ADSTB LOW Hold

Time
ADR from WRITE HIGH Hold

Time
DACK Valid from CLK LOW

Delay Time
EOP HIGH from CLK HIGH

Delay Time
EOP LOW from CLK HIGH

Delay Time

(NOTES 1, 2)

CONDITIONS TEMPERATURE SUBGROUP

TCLAEH VDD = 4.5V +25oC, +125oC,

-55oC

TCHAEL VDD = 4.5V +25oC, +125oC,

-55oC

TRHAX VDD = 4.5V +25oC, +125oC,

-55oC

TSLDZ VDD = 4.5V +25oC, +125oC,

-55oC

TWHAX VDD = 4.5V +25oC, +125oC,

-55oC

TCLDAV VDD = 4.5V +25oC, +125oC,

-55oC

TCHIPH VDD = 4.5V +25oC, +125oC,

-55oC

TCHIPL VDD = 4.5V +25oC, +125oC,

-55oC

LIMITS

UNITSMIN MAX

9, 10, 11 175 ns

9, 10, 11 - 130 ns

9, 10, 11 TCLCL-

100

9, 10, 11 TCLCH-

18

9, 10, 11 TCLCL-

50

9, 10, 11 - 170 ns

9, 10, 11 - 170 ns

9, 10, 11 - 100 ns

-ns

-ns

-ns

ADR Stable from CLK HIGH TCHAV VDD = 4.5V +25oC, +125oC,

-55oC

DB to ADSTB LOW Setup Time TDVSL VDD = 4.5V +25oC, +125oC,

-55oC

Clock HIGH Time
(Transitions 10ns)

Clock LOW Time
(Transitions 10ns)

CLK Cycle Time TCLCL VDD = 4.5V +25oC, +125oC,

CLK HIGH to READ or WRITE
LOW Delay

READ HIGH from CLK HIGH
(S4) Delay Time

WRITE HIGH from CLK HIGH
(S4) Delay Time

HRQ Valid from CLK HIGH
Delay Time

EOP LOW to CLK LOW Setup
Time

EOP Pulse Width TEPLEPH VDD = 4.5V +25oC, +125oC,

TCHCL VDD = 4.5V +25oC, +125oC,

-55oC

TCLCH VDD = 4.5V +25oC, +125oC,

-55oC

-55oC

TCHRWL VDD = 4.5V +25oC, +125oC,

-55oC

TCHRH VDD = 4.5V +25oC, +125oC,

-55oC

TCHWH VDD = 4.5V +25oC, +125oC,

-55oC

TCHRQV VDD = 4.5V +25oC, +125oC,

-55oC

TEPLCL VDD = 4.5V +25oC, +125oC,

-55oC

-55oC

9, 10, 11 - 110 ns

9, 10, 11 TCHCL

+10

9, 10, 11 70 - ns

9, 10, 11 50 - ns

9, 10, 11 200 - ns

9, 10, 11 - 190 ns

9, 10, 11 - 190 ns

9, 10, 11 - 130 ns

9, 10, 11 - 120 ns

9, 10, 11 40 - ns

9, 10, 11 220 - ns

-ns

READ or WRITE Active from
CLK HIGH

TCHRWV VDD = 4.5V +25oC, +125oC,

-55oC

923

9, 10, 11 - 150 ns

Spec Number 518058

Specifications HS-82C37ARH

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

VCC = +5V ±10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range.

(NOTES 1, 2)

PARAMETER SYMBOL

DMA (MASTER) MODE (Continued)
DB Float to Active Delay from

CLK HIGH
HLDA Valid to CLK HIGH Setup

Time
Input Data from MEMR HIGH

Hold Time
Input Data to MEMR HIGH

Setup Time
Output Data from MEMW HIGH

HOLD Time
Output Data Valid to MEMW

HIGH
DREQ to CLK LOW (SI, S4)

Setup Time
CLK LOW to READY Hold Time TCLRYX VDD = 4.5V +25oC, +125oC,

READY to CLK LOW Setup
Time

TCHDV VDD = 4.5V +25oC, +125oC,

TRAVCH VDD = 4.5V +25oC, +125oC,

TMRHDX VDD = 4.5V +25oC, +125oC,

TDVMRH VDD = 4.5V +25oC, +125oC,

TMWHDZ VDD = 4.5V +25oC, +125oC,

TDVMWH VDD = 4.5V +25oC, +125oC,

TDQVCL VDD = 4.5V +25oC, +125oC,

TRYVCL VDD = 4.5V +25oC, +125oC,

CONDITIONS TEMPERATURE SUBGROUP

-55oC

-55oC

-55oC

-55oC

-55oC

-55oC

-55oC

-55oC

-55oC

LIMITS

UNITSMIN MAX

9, 10, 11 - 110 ns

9, 10, 11 75 - ns

9, 10, 11 0 ns

9, 10, 11 155 ns

9, 10, 11 15 ns

9, 10, 11 TCLCL-

35

9, 10, 11 0 - ns

9, 10, 11 20 - ns

9, 10, 11 60 - ns

-ns

ADSTB HIGH from CLK LOW
Delay Time

ADSTB LOW from CLK LOW
Delay Time

READ HIGH Delay fromWRITE
HIGH

READ Pulse Width, Normal
Timing

ADSTB Pulse Width TSHSL VDD = 4.5V +25oC, +125oC,

Extended WRITE Pulse Width TWLWH1 VDD = 4.5V +25oC, +125oC,

WRITE Pulse Width TWLWH2 VDD = 4.5V +25oC, +125oC,

READ Pulse Width,
Compressed

PERIPHERAL (SLAVE) MODE
ADR Valid or CS LOW to IOR

LOW
ADR Valid or CS LOW to IOW

LOW Setup Time 0

TCLSH VDD = 4.5V +25oC, +125oC,

-55oC

TCLSL VDD = 4.5V +25oC, +125oC,

-55oC

TWHRH VDD = 4.5V +25oC, +125oC,

-55oC

TRLRH1 VDD = 4.5V +25oC, +125oC,

-55oC

-55oC

-55oC

-55oC

TRLRH2 VDD = 4.5V +25oC, +125oC,

-55oC

TAVIRL VDD = 4.5V +25oC, +125oC,

-55oC

TAVIWL VDD = 4.5V +25oC, +125oC,

-55oC

9, 10, 11 - 80 ns

9, 10, 11 - 120 ns

9, 10, 11 0 - ns

9, 10, 11 2TCLCL

-50

9, 10, 11 TCLCL -

80

9, 10, 11 2TCLCL

-100

9, 10, 11 TCLCL -

100

9, 10, 11 TCLCL -

50

9, 10, 11 10 - ns

9, 10, 11 0 - ns

-ns

-ns

-ns

-ns

-ns

Data Valid to IOW HIGH Setup
Time

TDVIWH VDD = 4.5V +25oC, +125oC,

-55oC

924

9, 10, 11 150 - ns

Spec Number 518058

Specifications HS-82C37ARH

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

VCC = +5V ±10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range.

(NOTES 1, 2)

PARAMETER SYMBOL

PERIPHERAL (SLAVE) MODE (Continued)
ADR or CS Hold from IOR HIGH TIRHAX VDD = 4.5V +25oC, +125oC,

Data Access from IOR TIRLDV VDD = 4.5V +25oC, +125oC,

RESET to First IOW or IOR TRSLIRWL VDD = 4.5V +25oC, +125oC,

RESET Pulse Width TRSHRSL VDD = 4.5V +25oC, +125oC,

IOR Width TIRLIRH VDD = 4.5V +25oC, +125oC,

ADR or CS HIGH from IOW
HIGH Hold Time

Data from IOW HIGH Hold Time TIWHDX VDD = 4.5V +25oC, +125oC,

IOW Width TIWLIWH VDD = 4.5V +25oC, +125oC,

NOTES:

1. READ refers to both IOR and MEMR, and WRITE refers to both IOW and MEMW, during memory to I/O and I/O to memory transfers

2. AC’s Tested at Worst Case VDD But Guaranteed Over Full Operating Range

TIWHAX VDD = 4.5V +25oC, +125oC,

CONDITIONS TEMPERATURE SUBGROUP

9, 10, 11 0 - ns

-55oC
9, 10, 11 - 150 ns

-55oC
9, 10, 11 2TCLCL - ns

-55oC
9, 10, 11 300 -

-55oC
9, 10, 11 200 - ns

-55oC
9, 10, 11 0 - ns

-55oC
9, 10, 11 10 - ns

-55oC
9, 10, 11 150 - ns

-55oC

LIMITS

UNITSMIN MAX

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS TEMPERATURE

Input Capacitance CIN VDD = Open, f = 1MHz,

All measurements refer­enced to device ground.

Output Capacitance COUT VDD = Open, f = 1MHz,

All measurements refer­enced to device ground.

I/O Capacitance CI/O VDD = Open, f = 1MHz,

All measurements refer-

enced to device ground.
ADR Active to Float Delay from CLK HIGH TCHAZ VDD = 4.5V and 5.5V -55oC < TA < +125oC - 90 ns
READ or WRITE Float Delay from CLK

HIGH
DB Active to Float Delay from CLK HIGH TCHDZ VDD = 4.5V and 5.5V -55oC < TA < +125oC - 170 ns
DB Float Delay from IOR HIGH TIRHDZ VDD = 4.5V and 5.5V -55oC < TA < +125oC10 85 ns
Power Supply HIGH to RESET LOW

Setup Time

NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are

characterized upon initial design release and upon design changes which would affect these characteristics.

TCHRWZ VDD = 4.5V and 5.5V -55oC < TA < +125oC - 120 ns

TPHRSL VDD = 4.5V and 5.5V -55oC < TA < +125oC 500 - ns

TA = +25oC - 15 pF

TA = +25oC - 15 pF

TA = +25oC - 20 pF

UNITSMIN MAX

925

Spec Number 518058

Specifications HS-82C37ARH

TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS

NOTE: See +25oC limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7 and 9).

TABLE 5. BURN-IN DELTA PARAMETERS (+25oC)

PARAMETER SYMBOL DELTA LIMITS

Standby Power Supply Current IDDSB ± 20µA
Output Leakage Current IOZL, IOZH ± 2µA
Input Leakage Current IIH, IIL ± 200nA
Output Low Voltage VOL ± 80mV
TTL Output High Voltage VOH1 ± 600mV
CMOS Output High Voltage VOH2 ± 150mV

TABLE 6. APPLICABLE SUBGROUPS

GROUP A SUBGROUPS

CONFORMANCE

GROUP

Initial Test 100% 5004 1, 7, 9 1 (Note 2) 1, 7, 9
Interim Test 100% 5004 1, 7, 9, ∆ 1,∆ (Note 2) 1, 7, 9
PDA 100% 5004 1, 7, ∆ - 1, 7
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 - 2, 3, 8A, 8B, 10, 11
Group A (Note 1) Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9,

Subgroup B5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆ 1, 2, 3, ∆ (Note 2) N/A
Subgroup B6 Sample 5005 1, 7, 9 - N/A
Group C Sample 5005 N/A N/A 1, 2, 3, 7, 8A, 8B, 9,

Group D Sample 5005 1, 7, 9 - 1, 7, 9
Group E, Subgroup 2 Sample 5005 1, 7, 9 - 1, 7, 9

NOTES:

1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised.

2. Table 5 parameters only

MIL-STD-883

METHOD

TESTED FOR -Q

RECORDED

FOR -Q TESTED FOR -8

10, 11

10, 11

RECORDED

FOR -8

926

Spec Number 518058